Thomas Harte
|
1a44ef0469
|
Introduces Klaus Dorman's 65C02 tests. All failing.
|
2018-08-06 21:48:43 -04:00 |
|
Thomas Harte
|
ebce9a2e51
|
Fixes test target.
|
2018-08-06 21:15:13 -04:00 |
|
Thomas Harte
|
abca38a548
|
Makes an initial removal of PCMPatchedTrack. Farewell, old friend.
|
2018-07-01 22:49:57 -04:00 |
|
Thomas Harte
|
853261364e
|
Generalised CRC generation and created specific subclasses for the CCITT CRC16 and CRC32.
|
2018-05-23 22:21:57 -04:00 |
|
Thomas Harte
|
0b771ce61a
|
Removes all instances of the copyright symbol.
|
2018-05-13 15:19:52 -04:00 |
|
Thomas Harte
|
05e31d7594
|
Mutates testComplicatedTrackSeek into an actual test.
Which frustratingly passes.
|
2018-05-01 19:52:12 -04:00 |
|
Thomas Harte
|
f4097290c2
|
Made various corrections following a quick for-loop constness audit.
|
2018-04-30 22:23:57 -04:00 |
|
Thomas Harte
|
b32538f3c8
|
Adds an additional test.
|
2018-04-30 22:05:44 -04:00 |
|
Thomas Harte
|
e7618bb32e
|
Corrects types (/chickens out).
|
2018-04-30 22:04:05 -04:00 |
|
Thomas Harte
|
e599e65087
|
Switches to use of the TargetList typedef wherever possible.
|
2018-04-14 19:46:38 -04:00 |
|
Thomas Harte
|
389979923e
|
Performs update to and satisfaction of Xcode 9.3's preferred warnings.
|
2018-03-30 10:25:01 -04:00 |
|
Thomas Harte
|
f0f9d5a6af
|
Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
|
2018-03-08 20:30:22 -05:00 |
|
Thomas Harte
|
fdef914137
|
Corrects test target regression.
|
2018-03-06 18:32:21 -05:00 |
|
Thomas Harte
|
66faed4008
|
Gives MachineForTargets complete responsibility for initial machine state.
|
2018-01-25 18:28:19 -05:00 |
|
Thomas Harte
|
21efb32b6f
|
Integrates the static and nascent dynamic analyser namespaces.
|
2018-01-24 21:48:44 -05:00 |
|
Thomas Harte
|
ed564cb810
|
Implements the main four cartridge banking schemes.
Slightly proof of concept for now.
|
2018-01-04 22:18:18 -05:00 |
|
Thomas Harte
|
c8367a017f
|
Cleans up test and makes attempt to factor in cartridge type popularity.
|
2018-01-01 21:21:05 -05:00 |
|
Thomas Harte
|
344a12566b
|
Tweaks a couple of expected cartridge types.
|
2018-01-01 20:14:56 -05:00 |
|
Thomas Harte
|
c07113ea95
|
Ensures no illegal accesses while testing MSX ROM type detection.
Specifically: the static analyser doesn't even correctly identify everything that is an MSX ROM yet, let alone then properly determine type.
|
2018-01-01 17:38:26 -05:00 |
|
Thomas Harte
|
bc2879c412
|
Corrects the MSX ROM unit test.
I.e. the test is correct now, for those SHAs I could find. The static analyser is still wrong just slightly less than half the time.
|
2018-01-01 17:35:13 -05:00 |
|
Thomas Harte
|
db25b4554b
|
Introduces failing tests of the MSX static analyser.
|
2018-01-01 16:38:26 -05:00 |
|
Thomas Harte
|
05b95ea2e0
|
Corrects Xcode tests.
|
2018-01-01 16:04:13 -05:00 |
|
Thomas Harte
|
6e1d69581c
|
Eliminates a variety of end-of-line spaces.
|
2017-11-07 22:54:22 -05:00 |
|
Thomas Harte
|
f95515ae81
|
Eliminates a large number of instance of end-of-line tabs.
|
2017-11-07 22:51:06 -05:00 |
|
Thomas Harte
|
064f1dfdbc
|
Removes usages of deprecated initialiser.
|
2017-10-05 18:10:47 -04:00 |
|
Thomas Harte
|
ff24e1de31
|
Corrects 6522 bridge per has-a-not-is-a template switch.
|
2017-09-04 21:56:21 -04:00 |
|
Thomas Harte
|
7af3de010e
|
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
|
2017-08-23 22:25:31 -04:00 |
|
Thomas Harte
|
ee71be0e7e
|
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
|
2017-08-21 21:56:42 -04:00 |
|
Thomas Harte
|
761afad118
|
Corrected timestamp return, and its testing by the 6502 timing tests.
|
2017-07-27 21:19:16 -04:00 |
|
Thomas Harte
|
37950143fc
|
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
|
2017-07-27 20:17:13 -04:00 |
|
Thomas Harte
|
9257a3f6d7
|
Added test for 16-bit arithmetic, and fixed implementation.
|
2017-07-26 19:04:52 -04:00 |
|
Thomas Harte
|
728143247d
|
Added a test for RLD and RRD. Which already passes.
|
2017-07-26 18:56:35 -04:00 |
|
Thomas Harte
|
6ec4e4e3d7
|
Merge branch 'master' into Memptr
|
2017-07-25 23:01:34 -04:00 |
|
Thomas Harte
|
37ccb9d3b6
|
Fixed 6502 timing tests.
|
2017-07-25 23:00:39 -04:00 |
|
Thomas Harte
|
3c254360ba
|
Completed fixture of the 6502 BCD test.
|
2017-07-25 22:55:45 -04:00 |
|
Thomas Harte
|
3ca51bedc6
|
Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses.
|
2017-07-25 22:48:44 -04:00 |
|
Thomas Harte
|
36076b7ea5
|
Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams.
|
2017-07-25 22:38:26 -04:00 |
|
Thomas Harte
|
df4732be2e
|
Corrected test.
|
2017-07-24 22:33:49 -04:00 |
|
Thomas Harte
|
9435c1e12a
|
The 1540 is now a ClockReceiver.
|
2017-07-24 22:32:41 -04:00 |
|
Thomas Harte
|
2912d7055b
|
The 6532 is now a ClockReceiver.
|
2017-07-24 21:57:24 -04:00 |
|
Thomas Harte
|
13f7aa4063
|
The TIA is now a ClockReceiver.
|
2017-07-24 21:48:34 -04:00 |
|
Thomas Harte
|
b3ae920746
|
Converted the DPLL and disk controller classes to be ClockReceivers.
|
2017-07-24 21:04:47 -04:00 |
|
Thomas Harte
|
e6578defcd
|
It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.
|
2017-07-23 22:22:50 -04:00 |
|
Thomas Harte
|
ace8e30818
|
Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
|
2017-07-23 22:21:39 -04:00 |
|
Thomas Harte
|
b0c2325adc
|
Corrected run call, and accepted that jam handling is gone forever.
|
2017-07-22 22:21:26 -04:00 |
|
Thomas Harte
|
4ea835e50b
|
Added test for EX (SP), rp, which passes.
|
2017-07-22 17:17:32 -04:00 |
|
Thomas Harte
|
6437c43147
|
Added CPI and CPD tests: at last two that pass without requiring implementation changes!
|
2017-07-22 12:38:18 -04:00 |
|
Thomas Harte
|
5928a24803
|
Transcribed missing tests as TODOs.
|
2017-07-22 11:44:17 -04:00 |
|
Thomas Harte
|
20a6bcc676
|
Added tests for the various LD (nn), rr instructions and corrected implementation to pass.
|
2017-07-22 11:39:13 -04:00 |
|
Thomas Harte
|
eaf313b0f6
|
Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
|
2017-07-22 11:20:21 -04:00 |
|
Thomas Harte
|
d51b66c204
|
Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
|
2017-07-21 23:01:35 -04:00 |
|
Thomas Harte
|
660f0e4c40
|
Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.
|
2017-07-21 22:52:25 -04:00 |
|
Thomas Harte
|
7b5f93510b
|
Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.
|
2017-07-16 20:55:57 -04:00 |
|
Thomas Harte
|
8ddd686049
|
Removed redundant variable.
|
2017-07-16 19:04:03 -04:00 |
|
Thomas Harte
|
2fb0aea990
|
Updated the C1540 test vessel to the new world.
|
2017-07-16 17:00:39 -04:00 |
|
Thomas Harte
|
95a6b0f85c
|
Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
|
2017-06-22 21:09:26 -04:00 |
|
Thomas Harte
|
0e0ce379b4
|
Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
|
2017-06-21 20:38:08 -04:00 |
|
Thomas Harte
|
36e8a11505
|
Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
|
2017-06-21 20:32:08 -04:00 |
|
Thomas Harte
|
108da64562
|
Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
|
2017-06-20 22:25:00 -04:00 |
|
Thomas Harte
|
184b371649
|
Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
|
2017-06-20 21:48:50 -04:00 |
|
Thomas Harte
|
27ac342928
|
Corrected conditional call timing, and its test.
|
2017-06-20 20:57:23 -04:00 |
|
Thomas Harte
|
6752f165db
|
Added failing tests for both kinds of CALL.
|
2017-06-19 22:03:29 -04:00 |
|
Thomas Harte
|
e05076b258
|
Added tests for everything except CALL. All passing.
|
2017-06-19 22:00:04 -04:00 |
|
Thomas Harte
|
fadbfdf801
|
Added DJNZ test.
|
2017-06-19 21:31:56 -04:00 |
|
Thomas Harte
|
cb277b8d1e
|
Added JP and JR tests.
|
2017-06-19 21:27:23 -04:00 |
|
Thomas Harte
|
234f14dbbe
|
Tests were at fault; all passing now.
|
2017-06-19 21:14:40 -04:00 |
|
Thomas Harte
|
99ede3a9ef
|
BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
|
2017-06-19 21:04:14 -04:00 |
|
Thomas Harte
|
378233f53d
|
Extended to BITs and SETs, accruing three new failures.
|
2017-06-19 21:01:30 -04:00 |
|
Thomas Harte
|
f903408980
|
Caught up on comments.
|
2017-06-19 20:53:22 -04:00 |
|
Thomas Harte
|
b684254908
|
Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
|
2017-06-19 20:33:34 -04:00 |
|
Thomas Harte
|
351d90ca55
|
Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.
|
2017-06-19 20:04:55 -04:00 |
|
Thomas Harte
|
23177df26a
|
Added various tests of the basic ALU ops.
|
2017-06-19 19:53:26 -04:00 |
|
Thomas Harte
|
ba15371948
|
Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
|
2017-06-19 19:47:00 -04:00 |
|
Thomas Harte
|
8d60734737
|
Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
|
2017-06-19 19:17:54 -04:00 |
|
Thomas Harte
|
002098d496
|
The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
|
2017-06-19 07:45:41 -04:00 |
|
Thomas Harte
|
85c5c4405a
|
Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
|
2017-06-19 07:30:01 -04:00 |
|
Thomas Harte
|
d668879ba6
|
Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
|
2017-06-18 22:03:13 -04:00 |
|
Thomas Harte
|
e1a2580b2a
|
Renamed BusOperation to MachineCycle::Operation.
|
2017-06-17 21:53:45 -04:00 |
|
Thomas Harte
|
b6f51474ff
|
Ensured that -description can handle the newly-captured bus actions.
|
2017-06-17 18:20:30 -04:00 |
|
Thomas Harte
|
0f18768091
|
Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.
|
2017-06-17 18:19:25 -04:00 |
|
Thomas Harte
|
50cd617bd9
|
Ensured test raises only the intentional failure exceptions.
|
2017-06-15 22:33:46 -04:00 |
|
Thomas Harte
|
838b818cd3
|
Finished transcribing first page of machine cycle documentation; several failures contained.
|
2017-06-15 22:19:49 -04:00 |
|
Thomas Harte
|
cf795562bf
|
Continued filling in tests, fleshing out what the test machine captures as a result.
|
2017-06-15 20:59:59 -04:00 |
|
Thomas Harte
|
ac37424878
|
Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
|
2017-06-15 19:06:59 -04:00 |
|
Thomas Harte
|
aed2827e7b
|
Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
|
2017-06-12 22:22:00 -04:00 |
|
Thomas Harte
|
50be3a24fe
|
Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be.
|
2017-06-11 13:30:08 -04:00 |
|
Thomas Harte
|
2190f60a89
|
Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.
|
2017-06-04 15:46:35 -04:00 |
|
Thomas Harte
|
0eebfdb4cc
|
Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.
|
2017-06-04 15:39:37 -04:00 |
|
Thomas Harte
|
7811374b0f
|
Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).
|
2017-06-04 15:07:07 -04:00 |
|
Thomas Harte
|
87095b0578
|
Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures.
|
2017-06-04 14:04:26 -04:00 |
|
Thomas Harte
|
b642d9f712
|
Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
|
2017-06-03 21:54:42 -04:00 |
|
Thomas Harte
|
fd6623b5a5
|
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
|
2017-06-03 21:22:16 -04:00 |
|
Thomas Harte
|
b3da16911f
|
Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.
|
2017-06-03 18:42:54 -04:00 |
|
Thomas Harte
|
e52892f75b
|
Added a test of interrupt mode 1.
|
2017-06-03 18:16:13 -04:00 |
|
Thomas Harte
|
8c41a0f0ed
|
Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
|
2017-06-03 17:53:44 -04:00 |
|
Thomas Harte
|
3e9212aaff
|
Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
|
2017-06-03 17:41:45 -04:00 |
|
Thomas Harte
|
d14902700a
|
Minor syntax and wiring fixes.
|
2017-06-01 22:33:05 -04:00 |
|
Thomas Harte
|
c95c32a9fe
|
Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.
|
2017-06-01 22:31:04 -04:00 |
|
Thomas Harte
|
494ce073b5
|
Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.
|
2017-05-31 19:58:57 -04:00 |
|
Thomas Harte
|
5ff73faf48
|
Ensured Zexall can pass.
|
2017-05-31 19:55:06 -04:00 |
|
Thomas Harte
|
2f7f11e2e5
|
Added diagnosis props.
|
2017-05-31 06:54:25 -04:00 |
|
Thomas Harte
|
5119997122
|
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
|
2017-05-30 22:41:23 -04:00 |
|
Thomas Harte
|
244b5ba3c2
|
Added a proper termination condition for Zexall and, for now, a Mhz counter.
|
2017-05-30 18:32:38 -04:00 |
|
Thomas Harte
|
960de7bd7b
|
Marginally reduced test machine costs based on usage.
|
2017-05-30 11:59:07 -04:00 |
|
Thomas Harte
|
4d4695032c
|
Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end.
|
2017-05-29 21:46:00 -04:00 |
|
Thomas Harte
|
6d22f6fcd5
|
Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being.
|
2017-05-29 17:17:17 -04:00 |
|
Thomas Harte
|
8bfaa487ce
|
Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).
|
2017-05-29 17:13:24 -04:00 |
|
Thomas Harte
|
267b2add9a
|
Adjusted for where FUSE nominally places timestamps. Down to 92 failures.
|
2017-05-29 16:44:07 -04:00 |
|
Thomas Harte
|
d290e3d99e
|
Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)
|
2017-05-29 16:35:00 -04:00 |
|
Thomas Harte
|
a6a4c5a936
|
Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.
|
2017-05-29 15:57:27 -04:00 |
|
Thomas Harte
|
ed7b07c8b1
|
Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct.
|
2017-05-29 11:54:27 -04:00 |
|
Thomas Harte
|
d83dd17738
|
[DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed.
|
2017-05-29 11:40:56 -04:00 |
|
Thomas Harte
|
9ade0dcae3
|
One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison.
|
2017-05-29 11:06:23 -04:00 |
|
Thomas Harte
|
a329d85697
|
Instituted memory value checks, flushing out seven new failures.
|
2017-05-29 11:01:45 -04:00 |
|
Thomas Harte
|
c322410783
|
Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.
|
2017-05-29 10:52:54 -04:00 |
|
Thomas Harte
|
b67331e018
|
Fixing the OUT repetition group reduces the code to one failing test.
|
2017-05-29 10:48:53 -04:00 |
|
Thomas Harte
|
ad56a9215c
|
Implemented IN[I/D]x. 18 failures remaining.
|
2017-05-29 10:12:33 -04:00 |
|
Thomas Harte
|
c56a5344b9
|
Implemented CP[I/D]x.
|
2017-05-29 08:54:00 -04:00 |
|
Thomas Harte
|
409c82ce73
|
Implemented RLD and RRD. 34 failures remaining.
|
2017-05-28 16:46:27 -04:00 |
|
Thomas Harte
|
6e83b7d6df
|
Attempted to add a proper exit condition for Zexall.
|
2017-05-28 15:13:47 -04:00 |
|
Thomas Harte
|
5a4d448cc1
|
Corrected logical flags; now down to 68 failures, all of them on the ED page.
|
2017-05-28 15:09:58 -04:00 |
|
Thomas Harte
|
6b66c8f304
|
Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84.
|
2017-05-28 14:50:51 -04:00 |
|
Thomas Harte
|
035df316aa
|
FUSE seems to have inconsistent ideas about where b3 and b5 come from in more-complicated BIT instructions. So I'm not testing them for now. Within that reality, reduced to 102 failures.
|
2017-05-27 23:54:53 -04:00 |
|
Thomas Harte
|
c7cb47a1d8
|
Readded and then disabled my temporary one-test-only patch. Failures are currently at 237.
|
2017-05-27 21:10:25 -04:00 |
|
Thomas Harte
|
98423c6e41
|
Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues.
|
2017-05-27 16:19:15 -04:00 |
|
Thomas Harte
|
33c3fa21e3
|
Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672.
|
2017-05-27 15:54:24 -04:00 |
|
Thomas Harte
|
9bc2b48d9b
|
Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures.
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2017-05-26 23:23:33 -04:00 |
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Thomas Harte
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e4e71a1e5f
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Switched back to descriptive failures, but put a cap on them.
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2017-05-25 21:08:24 -04:00 |
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Thomas Harte
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fba5af280e
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Shortened failure message, at least for now.
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2017-05-25 21:05:47 -04:00 |
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Thomas Harte
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2cadc706e2
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Now runs FUSE tests, albeit testing only a subset of the results. But enough to get started.
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2017-05-25 21:00:33 -04:00 |
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Thomas Harte
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3c6f63abcc
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Started towards running the FUSE tests. Just need to deal with the memory segments.
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2017-05-25 19:12:59 -04:00 |
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Thomas Harte
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00cd7e7e9c
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After hitting my head against the wall of trying to use [NS]Scanner as a parser some more, have given up and transcoded the two tests files to JSON.
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2017-05-25 18:20:13 -04:00 |
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Thomas Harte
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055c860b43
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Sealed off RegisterState as immutable, and started trying to parse the .expected file.
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2017-05-23 22:32:36 -04:00 |
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Thomas Harte
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454c8628c3
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Implemented an additional constructor for RegisterStates, pulling it out into file-level scope and implementing Equatable.
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2017-05-23 22:05:33 -04:00 |
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Thomas Harte
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a23a6db4d6
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Tidied up, creating a holder for RegisterState and giving it deserialisation logic. This makes sense because a register state will also need to be taken from the outputScanner, and from the machine.
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2017-05-23 08:13:24 -04:00 |
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Thomas Harte
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6575091a78
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Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.
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2017-05-22 21:50:34 -04:00 |
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Thomas Harte
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9e25d014d2
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Made an attempt to log bus activity for comparison with FUSE results.
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2017-05-22 19:49:38 -04:00 |
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Thomas Harte
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41d5dd8679
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Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
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2017-05-22 19:24:11 -04:00 |
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Thomas Harte
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22afa509ca
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Got to a parsing and towards an attempt to run FUSE tests.
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2017-05-22 19:14:46 -04:00 |
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Thomas Harte
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3fb3cc8269
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Got explicit about encodings.
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2017-05-21 22:53:06 -04:00 |
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Thomas Harte
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e3e461d7cb
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Added a test class for running the FUSE tests. With nothing much in it.
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2017-05-21 22:49:24 -04:00 |
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Thomas Harte
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c16fccb317
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Fixed file names.
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2017-05-21 22:43:07 -04:00 |
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Thomas Harte
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b9cffdf2bd
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Imported the FUSE tests.
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2017-05-21 22:42:20 -04:00 |
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Thomas Harte
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d910405648
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Added enough infrastructure to be able to react to the two CP/M calls this cares about.
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2017-05-19 21:53:39 -04:00 |
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Thomas Harte
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62b432c046
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Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.
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2017-05-19 21:20:28 -04:00 |
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Thomas Harte
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a3dafa9056
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Abbreviated uses of enumerations.
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2017-05-17 21:44:08 -04:00 |
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Thomas Harte
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64d6ee1be5
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Adjusted slightly to adapt to latest Swift warnings.
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2017-05-17 07:49:48 -04:00 |
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Thomas Harte
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1378ab7278
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Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access.
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2017-05-17 07:36:06 -04:00 |
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Thomas Harte
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87a021ec2d
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Made further attempt to get as fas as having the Z80 attempt to do something.
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2017-05-16 22:19:40 -04:00 |
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Thomas Harte
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189317b80c
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Added enough of a Z80 test machine to bridge up into Swift.
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2017-05-16 22:05:42 -04:00 |
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