Thomas Harte
|
b684254908
|
Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
|
2017-06-19 20:33:34 -04:00 |
|
Thomas Harte
|
351d90ca55
|
Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.
|
2017-06-19 20:04:55 -04:00 |
|
Thomas Harte
|
23177df26a
|
Added various tests of the basic ALU ops.
|
2017-06-19 19:53:26 -04:00 |
|
Thomas Harte
|
ba15371948
|
Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
|
2017-06-19 19:47:00 -04:00 |
|
Thomas Harte
|
8d60734737
|
Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
|
2017-06-19 19:17:54 -04:00 |
|
Thomas Harte
|
002098d496
|
The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
|
2017-06-19 07:45:41 -04:00 |
|
Thomas Harte
|
85c5c4405a
|
Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
|
2017-06-19 07:30:01 -04:00 |
|
Thomas Harte
|
50cd617bd9
|
Ensured test raises only the intentional failure exceptions.
|
2017-06-15 22:33:46 -04:00 |
|
Thomas Harte
|
838b818cd3
|
Finished transcribing first page of machine cycle documentation; several failures contained.
|
2017-06-15 22:19:49 -04:00 |
|
Thomas Harte
|
cf795562bf
|
Continued filling in tests, fleshing out what the test machine captures as a result.
|
2017-06-15 20:59:59 -04:00 |
|
Thomas Harte
|
ac37424878
|
Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
|
2017-06-15 19:06:59 -04:00 |
|