Thomas Harte
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d79aac3081
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Shuffle the personality enum into the 'public' header.
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2022-12-31 15:01:11 -05:00 |
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Thomas Harte
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8d5547dc9e
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Minor further style improvements.
... as I refamiliarise myself.
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2022-12-29 22:09:14 -05:00 |
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Thomas Harte
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5d89293c92
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Improve const ness, primarily of reverse_table .
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2022-12-29 11:29:19 -05:00 |
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Thomas Harte
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711f7b2d75
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C++17 makes this a single step.
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2022-12-27 22:50:12 -05:00 |
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Thomas Harte
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dca8c51384
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Prefer to avoid a macro.
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2022-12-27 22:36:27 -05:00 |
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Thomas Harte
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462b7dcbfa
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Add Mega Drive VRAM size.
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2022-12-27 22:28:43 -05:00 |
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Thomas Harte
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2ab4b351ca
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Extend enum.
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2022-12-27 22:20:47 -05:00 |
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Thomas Harte
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99ced5476f
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Add quick clock-rate notes.
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2022-12-26 22:56:45 -05:00 |
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Thomas Harte
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fea8fecf11
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Continue DMA requests if writing, even after a phase mismatch.
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2022-09-15 16:46:22 -04:00 |
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Thomas Harte
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beca7a01c2
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Treat a phase mismatch as ending DMA.
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2022-09-15 16:34:06 -04:00 |
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Thomas Harte
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2d8e260671
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Take a shot at the phase mismatch IRQ.
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2022-09-15 16:24:06 -04:00 |
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Thomas Harte
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04f5d29ed9
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Improve logging, factor out phase_matches per TODO comment.
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2022-09-15 16:14:14 -04:00 |
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Thomas Harte
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df29a50738
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Attempt to support the DMA interface.
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2022-08-31 15:33:48 -04:00 |
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Thomas Harte
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ea4bf5f31a
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Provide card's SCSI ID.
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2022-08-23 15:05:36 -04:00 |
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Thomas Harte
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8f2e94a1d8
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Switch name back to emphasise _async_.
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2022-07-16 14:41:04 -04:00 |
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Thomas Harte
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bf03bda314
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Generalise AsyncTaskQueue, DeferringAsyncTaskQueue and AsyncUpdater into a single template.
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2022-07-14 16:39:26 -04:00 |
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Thomas Harte
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55af6681af
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Avoid unnecessary get_port_input calls.
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2021-11-24 17:15:48 -05:00 |
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Thomas Harte
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2a7a42ff8f
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Add header for assert .
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2021-11-24 16:28:18 -05:00 |
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Thomas Harte
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0ad1529f3f
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Retain delegate bit length for non-self-clocked data.
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2021-11-24 16:15:27 -05:00 |
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Thomas Harte
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0df8173536
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Merge branch 'master' into Amiga
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2021-11-24 08:58:03 -05:00 |
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Thomas Harte
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f5d3d6bcea
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Splits the lowpass filter into push and pull variants.
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2021-11-21 15:37:29 -05:00 |
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Thomas Harte
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4fc25fb798
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Adds basic shift input.
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2021-11-07 05:18:54 -08:00 |
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Thomas Harte
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941d9a46a2
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Makes a better effort at exposition; better implements clocked line.
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2021-11-07 05:18:40 -08:00 |
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Thomas Harte
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ecfe68d70f
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Introduce the principle that a Serial::Line can be two-wire — clock + data.
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2021-11-06 16:54:20 -07:00 |
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Thomas Harte
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f102d8a4b4
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Extend to allow full-[byte/word/dword] writes, in LSB or MSB order.
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2021-11-06 12:01:32 -07:00 |
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Thomas Harte
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6d34432988
|
Starts to build in a serial line for input.
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2021-11-04 18:54:28 -07:00 |
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Thomas Harte
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b827b9e33e
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Add necessary shift storage.
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2021-11-03 19:26:45 -07:00 |
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Thomas Harte
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29e5ecc282
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Add TODOs rather than complete stop on shift register acccesses.
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2021-11-02 18:19:31 -07:00 |
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Thomas Harte
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9ecd43238f
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Correct 8520 TOD setting and getting.
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2021-10-30 12:02:43 -07:00 |
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Thomas Harte
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5ffe71346c
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Eliminate interrupt magic constants.
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2021-10-29 19:04:06 -07:00 |
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Thomas Harte
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d9d20d9d30
|
Walk back slightly.
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2021-10-14 18:02:58 -07:00 |
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Thomas Harte
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689bfbbdb3
|
Be overt in initialiser list.
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2021-10-14 16:57:26 -07:00 |
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Thomas Harte
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eb157f15f3
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Adds index hole interrupt.
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2021-10-09 04:08:59 -07:00 |
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Thomas Harte
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73e45511dc
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Add missing #include.
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2021-10-04 05:26:38 -07:00 |
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Thomas Harte
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e47eab1d40
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Merge branch 'master' into Amiga
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2021-09-14 20:27:59 -04:00 |
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Thomas Harte
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dfcd1508c9
|
Establishes valid initial BRAM.
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2021-09-10 19:56:20 -04:00 |
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Thomas Harte
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0ca4631279
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Switch to zero-initialised state; be more careful about resetting data.
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2021-09-09 23:08:13 -04:00 |
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Thomas Harte
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a6221ca322
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Reload data only if an output is found.
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2021-09-09 22:07:03 -04:00 |
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Thomas Harte
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f8380d2d4c
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Add 8250 feature of 'count, regardless'.
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2021-08-08 22:32:41 -04:00 |
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Thomas Harte
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1f9e41e9cb
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Ensure TOD isn't firing from power-on.
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2021-08-08 18:51:58 -04:00 |
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Thomas Harte
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98bd6fc240
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Adds a further logging hint.
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2021-08-06 23:16:06 -04:00 |
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Thomas Harte
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b9f78f5d33
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Fix final timer B test.
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2021-08-03 22:27:23 -04:00 |
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Thomas Harte
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b4ec9d70da
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Adds the CNT input.
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2021-08-03 22:19:41 -04:00 |
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Thomas Harte
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dd91d793d9
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Correct typo.
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2021-08-03 21:45:44 -04:00 |
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Thomas Harte
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8e51e8eb77
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Does just a touch of 6526 TOD work.
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2021-08-03 21:13:08 -04:00 |
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Thomas Harte
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6210605bc7
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Transfers full TOD responsibility onto the chip-specific templates.
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2021-08-03 19:10:09 -04:00 |
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Thomas Harte
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0245b040b0
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Splits TOD storage by model.
TOD storage will probably end up being a full-on class.
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2021-08-03 18:50:58 -04:00 |
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Thomas Harte
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8795719c18
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This counts reloads, most accurately.
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2021-08-03 17:12:08 -04:00 |
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Thomas Harte
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6bbbf43341
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At least attempts to chain correctly.
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2021-08-03 17:03:58 -04:00 |
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Thomas Harte
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ee6039bfa5
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Writes to a timer _during reload_ now have effect.
Net: one CIA test passed.
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2021-08-03 16:57:05 -04:00 |
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Thomas Harte
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ef58ce6277
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Gets a bit more rigorous about the clocking stage.
Albeit without advancing relative to the test.
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2021-08-02 21:04:00 -04:00 |
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Thomas Harte
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15de5e98c4
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Adds [partial] test for whether counters are linked.
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2021-08-02 20:17:37 -04:00 |
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Thomas Harte
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38848ca2db
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Rationalises reload logic and cuts storage.
Failure point is now chaining, I think.
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2021-08-02 20:14:01 -04:00 |
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Thomas Harte
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77c627e822
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Ensure that reading the interrupt flags really clears the master bit.
Also makes some guesses on one-shot and reload timing. Alas the test isn't in itself specific enough to be more systematic here.
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2021-08-02 07:47:08 -04:00 |
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Thomas Harte
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c640132699
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Reinstates clocking.
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2021-08-01 21:35:08 -04:00 |
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Thomas Harte
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57dd38aef2
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Reintroduces reload-on-off, adds interrupt delay.
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2021-08-01 21:09:02 -04:00 |
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Thomas Harte
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460a6cb6fe
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Attempts a more literal implementation.
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2021-08-01 18:14:10 -04:00 |
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Thomas Harte
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3d160ce85f
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Add another potential warning.
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2021-07-30 18:21:38 -04:00 |
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Thomas Harte
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759007ffc1
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Attempts to route CIA interrupts.
|
2021-07-28 19:36:30 -04:00 |
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Thomas Harte
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37a55c3a77
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Corrects 6526 interrupt control write.
This seems to imply that the 6526 should be interrupting too.
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2021-07-28 19:26:02 -04:00 |
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Thomas Harte
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bcb7bb5cce
|
Improves logging further.
To investigate the new perpetual loop.
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2021-07-26 17:02:30 -04:00 |
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Thomas Harte
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34d4420e8c
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Correct reading of top byte of counter 2.
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2021-07-25 20:41:15 -04:00 |
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Thomas Harte
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fcd6b7b0ea
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Takes further aim at the conters.
I think test cases are needed, probably.
|
2021-07-24 16:06:49 -04:00 |
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Thomas Harte
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ceca32ceb3
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Takes a guess at one-shot mode.
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2021-07-24 15:53:18 -04:00 |
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Thomas Harte
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77a8ddb95c
|
Edges towards working counters.
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2021-07-23 22:43:47 -04:00 |
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Thomas Harte
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c733a4dbf8
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Beefs up interrupt awareness.
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2021-07-23 21:58:52 -04:00 |
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Thomas Harte
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d898a43dff
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Implements time-of-day counters, provisionally.
Interrupts to do.
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2021-07-23 21:24:07 -04:00 |
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Thomas Harte
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6123349b79
|
Stubs in control registers and disables exit-on-miss.
I think I may be running up against the limits of stubbing now. Probably time to implement some stuff.
|
2021-07-22 19:28:01 -04:00 |
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Thomas Harte
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56b62a5e49
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Adds a dummy interrupt control register.
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2021-07-22 16:09:32 -04:00 |
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Thomas Harte
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a030d9935e
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Adds port input.
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2021-07-18 20:25:04 -04:00 |
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Thomas Harte
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c425dec4d5
|
Makes some attempt to get as far as the overlay being disabled.
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2021-07-18 17:17:41 -04:00 |
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Thomas Harte
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67d53601d5
|
Latch and return data direction.
Albeit with no port-handling effect yet.
|
2021-07-18 12:23:47 -04:00 |
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Thomas Harte
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622cca0acf
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Adds sufficient address decoding to print a more helpful exit message.
|
2021-07-18 12:13:56 -04:00 |
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Thomas Harte
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48999c03a5
|
Adds concept of time, captured port handler.
|
2021-07-18 11:49:10 -04:00 |
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Thomas Harte
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377cc7bdcd
|
Start to introduce a 6526/8250.
|
2021-07-18 11:36:13 -04:00 |
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Thomas Harte
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a5d0976c2d
|
Eliminate unused #includes.
|
2021-07-18 11:35:57 -04:00 |
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Thomas Harte
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ae05010255
|
Improve indentation.
|
2021-07-18 11:29:26 -04:00 |
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Thomas Harte
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66cacbd0e0
|
Be overt about the type being supplied.
|
2021-07-18 11:28:18 -04:00 |
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Thomas Harte
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c8699d9770
|
Correct Disk II sleeping test to allow for spin-down.
|
2021-07-16 17:12:57 -04:00 |
|
Thomas Harte
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69c0734975
|
WD1770: switch motor on even if spin-up is disabled.
|
2021-06-21 23:26:55 -04:00 |
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Thomas Harte
|
1d5144b912
|
Correct no-interrupt signal.
|
2021-06-04 22:38:07 -04:00 |
|
Thomas Harte
|
b7a62e0121
|
Adds SZX support.
Tweaking exposed Spectrum state object as relevant.
|
2021-04-26 20:47:28 -04:00 |
|
Thomas Harte
|
3348167c46
|
Ensures AY registers are conveyed.
|
2021-04-26 17:39:11 -04:00 |
|
Thomas Harte
|
73c8157197
|
Retain 6850 time tracking at all times.
|
2021-04-20 22:26:43 -04:00 |
|
Thomas Harte
|
af1dc2d3b2
|
Switches to correct non-value sentinel.
|
2021-04-20 21:56:58 -04:00 |
|
Thomas Harte
|
1266bbb224
|
Makes the TMS a sequence-point-generating JustInTimeActor.
|
2021-04-05 21:02:37 -04:00 |
|
Thomas Harte
|
8a11a5832c
|
Uses GI::AY38910::Utility far and wide.
|
2021-03-26 23:19:47 -04:00 |
|
Thomas Harte
|
f37f89a7d3
|
Merge branch 'master' into ZXSpectrum
|
2021-03-21 22:44:37 -04:00 |
|
Thomas Harte
|
58be770eaa
|
Factors out some boilerplate.
When I'm confident this is correct, I can fix up the other call sites.
|
2021-03-21 00:14:48 -04:00 |
|
Thomas Harte
|
650b9a139b
|
Tweak Master System blue scale.
|
2021-03-19 08:38:21 -04:00 |
|
Thomas Harte
|
6839e9e3b3
|
Ensures no double definition of NDEBUG.
|
2021-03-07 12:52:54 -05:00 |
|
Thomas Harte
|
86fd47545d
|
Silences.
|
2021-03-03 20:51:33 -05:00 |
|
Thomas Harte
|
71a107fe75
|
Silences the IWM again, for now.
|
2021-02-23 21:57:19 -05:00 |
|
Thomas Harte
|
a3e98907ca
|
Removes temporary printf.
|
2021-02-14 21:03:54 -05:00 |
|
Thomas Harte
|
ee5f45c979
|
Merge branch 'master' into AppleIIgs
|
2020-12-29 22:16:23 -05:00 |
|
Thomas Harte
|
dfe4e49110
|
Ensure proper in-memory ordering of the b72a2c70 ROM.
|
2020-12-29 22:08:48 -05:00 |
|
Thomas Harte
|
8ace258fbc
|
Tackles outstanding GCC warnings.
|
2020-11-22 21:43:56 -05:00 |
|
Thomas Harte
|
9b45c5a1cd
|
Resolves out-of-bounds reads.
|
2020-11-21 22:36:10 -05:00 |
|
Thomas Harte
|
4a42de4f18
|
Attempts to add 5.25" drive support to the IIgs.
I want to try some classic software.
|
2020-11-20 21:37:17 -05:00 |
|
Thomas Harte
|
98347cb1c3
|
Starts in the direction of audio support.
|
2020-11-18 18:39:11 -05:00 |
|