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Author SHA1 Message Date
Thomas Harte
bdb5abe47b Record updated version number. 2024-09-08 21:34:02 -04:00
Thomas Harte
dbe0ebc93e
Merge pull request #1400 from TomHarte/DelegateOrderTest 
Fix order of `if` tests.
 2024-09-08 21:30:44 -04:00
Thomas Harte
1c2f66e855 Fix order of if tests. 2024-09-08 21:23:58 -04:00
Thomas Harte
7eee3f9e5e
Merge pull request #1399 from TomHarte/ElectronULARedux 
Replace Electron graphics generation with FPGA transcription.
 2024-09-08 21:23:09 -04:00
Thomas Harte
b7f069e1bd Add a colour burst. 2024-09-08 21:12:45 -04:00
Thomas Harte
51c8396e32 Fix faulty centring. 2024-09-08 21:06:59 -04:00
Thomas Harte
0efe649ca5 Post pixel clock. 2024-09-08 20:57:43 -04:00
Thomas Harte
75db0018bc Add note on provenance. 2024-09-08 20:20:03 -04:00
Thomas Harte
2a9e1ea045 Use normal member naming convention. 2024-09-08 20:16:43 -04:00
Thomas Harte
8feb8aaadc Reintroduce cropping, even if faulty. 2024-09-06 22:12:19 -04:00
Thomas Harte
b8f4385501 Fix palette generation. 2024-09-06 21:47:13 -04:00
Thomas Harte
d8b6d87a1c Attempt colour. 2024-09-06 21:36:05 -04:00
Thomas Harte
f10702b3ca Edge towards proper serialisation. 2024-09-06 21:01:30 -04:00
Thomas Harte
88248d7062 Fix base address, delays. 2024-09-06 20:55:26 -04:00
Thomas Harte
5ca1659bcc Do just enough to get 1bpp fixed-palette pixels. 2024-09-06 20:36:27 -04:00
Thomas Harte
59530a12fd Sub in basic transliteration of hoglet's FPGA. 2024-09-06 20:21:46 -04:00
Thomas Harte
aab2dd68b6 Substitute in a real-time video generator. 2024-09-06 20:18:29 -04:00
Thomas Harte
83f5065642 Update version. 2024-08-26 21:38:49 -04:00
Thomas Harte
7e3a331eba
Merge pull request #1394 from TomHarte/ElectronFlicker 
Electron: don't miss interrupts early in the frame.
 2024-08-26 21:28:53 -04:00
Thomas Harte
b5932edff3 Avoid missed interrupts on wraparound. 2024-08-26 21:13:49 -04:00
Thomas Harte
12846317cb Short-circuit non-interrupts. 2024-08-26 21:13:25 -04:00
Thomas Harte
051f0546c7
Merge pull request #1393 from TomHarte/ZXAnalysis 
Improve Spectrum +3 disk analysis.
 2024-08-24 21:45:45 -04:00
Thomas Harte
eece8c54a4 Factgor out and reuse is-ZX test. 2024-08-22 21:17:35 -04:00
Thomas Harte
69ba94e379 Add some CP/M smarts to +3 disk analysis. 2024-08-20 21:43:31 -04:00
Thomas Harte
0de7057d6f Use standard algorithm. 2024-08-20 20:45:43 -04:00
Thomas Harte
3dcbb40c55
Merge pull request #1391 from TomHarte/SSLandCSL 
Treat second argument to key_delay as optional.
 2024-08-14 19:56:18 -05:00
Thomas Harte
91b263f0cf Treat second argument as optional. 2024-08-14 20:55:33 -04:00
Thomas Harte
bcd558867d
Merge pull request #1387 from TomHarte/SSLandCSL 
CPC: implement CSL and SSM to run Shaker tests.
 2024-08-14 19:55:18 -05:00
Thomas Harte
a9c8ef642c Correct original author's typo. 2024-08-14 18:55:35 -04:00
Thomas Harte
43887b42b1 Allow vsync on line 0. 2024-08-07 23:05:26 -04:00
Thomas Harte
30b1b36e63 Test digits individually; CSLs autolink. 2024-08-07 22:44:48 -04:00
Thomas Harte
ef11262721 Expand test membership. 2024-08-07 22:15:43 -04:00
Thomas Harte
2d049f5fdc Implement reset, correct file names. 2024-08-07 22:00:24 -04:00
Thomas Harte
05f0a122f4 Blank out border. 2024-08-05 22:06:23 -04:00
Thomas Harte
1977675a73 Add some measure of graphics output. 2024-08-05 21:48:40 -04:00
Thomas Harte
4ceaab7c26 Merge branch 'master' into SSLandCSL 2024-07-26 22:08:11 -04:00
Thomas Harte
6c33177548
Merge pull request #1389 from TomHarte/6502JAM 
Correct 6502 JAM bus activity.
 2024-07-26 22:07:40 -04:00
Thomas Harte
76ca607021 Add a graceful end for JAM. 2024-07-26 21:45:17 -04:00
Thomas Harte
59e1a5e5f6 Correct 6502 JAM behaviour. 2024-07-26 21:43:54 -04:00
Thomas Harte
4f55b2a554 Merge branch 'SSLandCSL' of github.com:TomHarte/CLK into SSLandCSL 2024-07-08 00:24:22 +02:00
Thomas Harte
78b2a89554 Add header for std::vector. 2024-07-08 00:20:54 +02:00
Thomas Harte
1e84a735e6 Add header for std::vector. 2024-07-08 00:18:53 +02:00
Thomas Harte
9e8801d867 Add header for std::variant. 2024-07-08 00:17:39 +02:00
Thomas Harte
0e58f7fa69 Merge branch 'master' into SSLandCSL 2024-07-05 14:54:47 -04:00
Thomas Harte
94058d498c
Merge pull request #1388 from TomHarte/6502BBSBBR 
Correct 65c02 BBS/BBR bus activity.
 2024-07-05 14:51:31 -04:00
Thomas Harte
2621bcc005 Switch to 5/6/7 BBS/BBR timing. 2024-07-05 13:44:31 -04:00
Thomas Harte
e750866ab6 Remove phoney mid-BBR/BBS access. 2024-07-02 22:01:02 -04:00
Thomas Harte
00b3007b9f Switch byte order. 2024-07-02 21:51:00 -04:00
Thomas Harte
dbc0ecde31 Catch SSM events. 2024-06-30 21:26:16 -04:00
Thomas Harte
0e30e2d865 Add CSL side of execution. 2024-06-30 20:19:02 -04:00