Thomas Harte
c7f27b2db4
Renames MFM.[c/h]pp as per its new remit: encoding only.
2017-09-24 21:40:43 -04:00
Thomas Harte
2a08bd9ecc
Factors shifting plus stateful [M]FM token recognition out of the MFMDiskController.
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Given the proliferation of MFM-related classes, establishes a subdirectory for them.
2017-09-24 20:07:56 -04:00
Thomas Harte
698e4fe550
Tidies the Disk file hierarchy.
2017-09-22 22:39:23 -04:00
Thomas Harte
d6a5f9a29e
Revokes unnecessary change.
2017-09-16 18:24:13 -04:00
Thomas Harte
0d84b4b9dd
Removes some redundant end_writing calls.
2017-09-16 17:09:17 -04:00
Thomas Harte
98751e6ac8
Ensures that all result phases are exactly the intended length by replacing accumulation with assignment.
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Also attempts a different version of control mark behaviour. Experiments.
2017-09-15 22:59:26 -04:00
Thomas Harte
35fe4d50d4
Adds command termination upon drive becoming unready, and copies head and drive selection into ST0.
2017-09-15 20:26:41 -04:00
Thomas Harte
4d4a0cf1d2
Puts the disk controller back into the loop with knowledge about reading mode, and uses that knowledge to cut off the PLL.
2017-09-14 22:30:40 -04:00
Thomas Harte
b62f3e726a
Adds a start-of-execution-phase get-out for drives that aren't ready.
2017-09-12 20:43:53 -04:00
Thomas Harte
2f13517f38
Adjusts the 1770 not to talk directly to the drive about motor status.
2017-09-11 22:10:56 -04:00
Thomas Harte
d3c385b471
Separates the 8272's drive selection signalling from actual drive ownership.
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Thereby returns working motor control to the CPC.
2017-09-11 21:25:26 -04:00
Thomas Harte
96bf133924
Withdraws requirement for DiskController users to specify a PLL multiplier or to provide rotation speed.
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In the latter case because it's no longer of any interest to the controller, and in the former because I'd rather it be picked automatically.
2017-09-10 22:56:05 -04:00
Thomas Harte
0622187ddf
Strips Controller of all capabilities now housed on the Drive.
2017-09-10 19:23:23 -04:00
Thomas Harte
90c7056d12
Started devolving timed event loop logic down to the drives, moving them closer to modelling real life.
2017-09-10 14:43:20 -04:00
Thomas Harte
ff510f3b84
Explicitly disallows copying of VIAs, and marks the constructor as noexcept.
2017-09-05 21:21:23 -04:00
Thomas Harte
7fd6699e0b
Corrects comment indentation.
2017-09-05 21:15:15 -04:00
Thomas Harte
450712f39c
Improves and corrects 6522 header documentation.
2017-09-04 14:32:34 -04:00
Thomas Harte
24b3faa427
Deconstitutes the 6522 into component parts, templated and non-templated.
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Adjusts the Oric, Vic-20 and C-1540 accordingly, albeit with the quickest possible solutions.
2017-09-04 14:26:04 -04:00
Thomas Harte
b30bb2a234
Adds an initial implementation of display skew, as a completely live property.
2017-08-29 22:16:40 -04:00
Thomas Harte
334afbc710
Removes const from get_status and get_register, as both may now logically mutate the object.
2017-08-27 18:13:55 -04:00
Thomas Harte
17c13624e5
Improved comments.
2017-08-27 18:11:40 -04:00
Thomas Harte
113349d272
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 18:10:07 -04:00
Thomas Harte
bdda701207
Reverts previous unevidenced change.
2017-08-26 22:58:16 -04:00
Thomas Harte
487fe83dca
Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.
2017-08-26 17:54:54 -04:00
Thomas Harte
6c5a03187b
Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test.
2017-08-26 17:22:48 -04:00
Thomas Harte
7d7aa2f5d5
Eliminates repetition of the unpacking of register 3 into a horizontal sync count.
2017-08-26 14:37:03 -04:00
Thomas Harte
28550c0227
Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
2017-08-26 13:56:23 -04:00
Thomas Harte
6e99169348
Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
2017-08-26 12:59:59 -04:00
Thomas Harte
3caa4705ca
Limits sync counter size.
2017-08-26 12:31:19 -04:00
Thomas Harte
039aed1bd1
Switches the two sync counters to upward-going rather than downward, as a more likely match to the way the rest of the 6845 implementation.
2017-08-25 21:26:01 -04:00
Thomas Harte
a914eadc85
Ensured that register 6 is checked on every loop.
2017-08-22 22:17:45 -04:00
Thomas Harte
e956740c56
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-22 21:54:48 -04:00
Thomas Harte
e88a51e75e
Worked logic all the way down to the CPC. If the 8272 announces that it is asleep, it is now no longer clocked. Also very slightly cut down on IRQ line chatter to the Z80.
2017-08-20 12:05:00 -04:00
Thomas Harte
2d9efccc98
Introduced a master 'is sleeping' flag. I'm starting to think there's a pattern forming here.
2017-08-20 10:43:53 -04:00
Thomas Harte
8ce46b6e49
Having spotted that I was using my single-character loop counter names incorrectly (quelle surprise!), got a bit more explicit. Also flattened into a single loop so that I can break rather than returning.
2017-08-20 10:32:09 -04:00
Thomas Harte
669e0caff5
Ensured the head_unload_delay values are properly seeded, and generalised the quick escape.
2017-08-19 22:06:56 -04:00
Thomas Harte
e208f03636
Corrects the US colour palette, effectively undoing what was a mistaken adjustment for the time when Oric-centric phase alignment was built into the CRT based on a false calculation that it wouldn't affect the machines that generate chrominance functionally.
2017-08-16 09:58:34 -04:00
Thomas Harte
cc9d23f23b
Inverted meaning of register_masks, as it's a bit weird that the mask is inverted immediately upon usage. It's a left-over from thinking the unused bits should be 1s; unit tests reveal they should be 0s. Comment updated appropriately.
2017-08-16 09:29:48 -04:00
Thomas Harte
1a831bcf9b
Quick fix: supply the port being written to correctly.
2017-08-16 09:15:57 -04:00
Thomas Harte
82367a2246
Added documentation.
2017-08-16 09:14:56 -04:00
Thomas Harte
3947347d88
Introduces active input handling for the AY and uses it in the CPC to give proper, active keyboard input, rather than push-on-select, which was only ever a temporary hack. Also maps a few more keys for the Amstrad.
2017-08-15 22:47:17 -04:00
Thomas Harte
aefbafa18d
Centralised the 8272's actions of setting the non-DMA execution flag, picking the drive and head and loading the head for accessing commands, and switched error flag if read ID doesn't find anything.
2017-08-15 21:49:10 -04:00
Thomas Harte
d12c834f9c
Increased amount reported.
2017-08-15 20:35:33 -04:00
Thomas Harte
56de5cb2b3
Removed one further logging event.
2017-08-15 20:18:32 -04:00
Thomas Harte
709257a0c5
Quick fix: also treat reception of sync as a reason not to stop looking for a data address mark.
2017-08-15 20:16:56 -04:00
Thomas Harte
75a9d2bb33
Started withdrawing logging, reduced index hole count back to the correct number and tried to increase read_data rigour.
2017-08-15 20:12:01 -04:00
Thomas Harte
73080d6c36
Added an easy way for disk controllers to clamp termination of written data exactly to the index hole.
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This commit also temporarily provides a whole load of extra logging and minor logic improvements from the 8272. I'm mid-flow on finding a particularly vicious error in its handling of writing; wait for the pull request. But, at least: now waits for the first part of a post-ID gap before writing data, and attempts partially to handle appearance of the index hole during writing a track. More work to do on that though.
2017-08-15 16:05:10 -04:00
Thomas Harte
9d77f33611
Dealt with another source of repeating magic constants: the command numbers.
2017-08-15 11:06:10 -04:00
Thomas Harte
7d132f81f7
Increased logging by quite a distance and made an attempt once again to allow the processor some time to supply the first byte when writing before declaring overrun.
2017-08-15 10:50:28 -04:00
Thomas Harte
6553bf05b4
Corrected multi-sector reads: ensured the incremented sector number isn't replaced by the original, and that the controller returns to scanning mode.
2017-08-14 22:27:31 -04:00
