93 Commits

Author	SHA1	Message	Date
Thomas Harte	888148d282	Reduce chatter.	2025-09-17 21:35:34 -04:00
Thomas Harte	7bba0b82ef	Correct video address generation.	2025-09-17 21:26:13 -04:00
Thomas Harte	a99ed0e557	Add break key.	2025-09-17 17:26:28 -04:00
Thomas Harte	654981fb03	Clean up.	2025-09-17 17:24:08 -04:00
Thomas Harte	25b15fcdd1	Switch to map-based mapping.	2025-09-17 11:34:55 -04:00
Thomas Harte	1106fbb5ef	Implement circular scan.	2025-09-17 10:44:53 -04:00
Thomas Harte	b3c057f911	Increase logging, play about more.	2025-09-16 23:14:05 -04:00
Thomas Harte	1c33e9ead9	Attempt row scanning.	2025-09-16 23:03:25 -04:00
Thomas Harte	d78f35b940	Take a swing at scanning versus not.	2025-09-16 22:29:00 -04:00
Thomas Harte	18b32dbba3	Attempt keyboard input.	2025-09-16 21:51:25 -04:00
Thomas Harte	26e40564dc	Establish keyboard state.	2025-09-16 21:11:27 -04:00
Thomas Harte	b6e8421a0a	Hard-code Mode 0 but hence get some pixels.	2025-09-16 20:57:21 -04:00
Thomas Harte	a1f33d3fc6	Redisable test code.	2025-09-16 17:54:42 -04:00
Thomas Harte	683fea675e	Add ACIA. ... Probably with incorrect clock, and connected to nothing.	2025-09-16 17:50:54 -04:00
Thomas Harte	811a010a60	Fix: keys are now unpressed. ... Some sort of text is now 'output' (though not yet displayed by the emulator) and then an endless loop on the ACIA begins. So the next PR will need to add that.	2025-09-16 17:25:13 -04:00
Thomas Harte	019526332d	Declare no tube, optimistically watch for characters.	2025-09-16 16:25:41 -04:00
Thomas Harte	84d6bb47ea	Log more.	2025-09-16 15:32:42 -04:00
Thomas Harte	512179d92a	Handle clock-rate change correctly in onward signalling.	2025-09-16 13:04:03 -04:00
Thomas Harte	04344a3723	The OS isn't writeable.	2025-09-16 12:47:55 -04:00
Thomas Harte	d032207473	Made some attempt at 1Mhz CRTC clocking.	2025-09-16 12:46:44 -04:00
Thomas Harte	b33dc2779d	Correct RAM visibility.	2025-09-16 12:24:48 -04:00
Thomas Harte	28699a1af5	Correct clock selection bit.	2025-09-16 09:15:08 -04:00
Thomas Harte	ff3fe135a3	Convince myself that this isn't a case of present but invisible content.	2025-09-16 07:36:59 -04:00
Thomas Harte	34330baaa0	Add comment on keyboard.	2025-09-15 23:42:47 -04:00
Thomas Harte	28d8aab7e5	Forward Port A correctly.	2025-09-15 23:36:07 -04:00
Thomas Harte	6a91c89126	Introduce a colour burst.	2025-09-15 23:32:20 -04:00
Thomas Harte	c350f6fe5e	Fix interrupting sync.	2025-09-15 23:28:38 -04:00
Thomas Harte	493bf0a666	Proceed to a solid blank display.	2025-09-15 23:27:04 -04:00
Thomas Harte	0305203e61	Wire up vertical sync interrupt.	2025-09-15 23:21:06 -04:00
Thomas Harte	71d7b1dfad	Add a ticking-but-diconnected CRTC.	2025-09-15 23:16:42 -04:00
Thomas Harte	39c2db38b7	Improve logged IO detail.	2025-09-15 22:29:22 -04:00
Thomas Harte	f499de3622	Add sideways ROM paging.	2025-09-15 22:26:02 -04:00
Thomas Harte	e8a16a8fce	Attempt to incorporate SN76489.	2025-09-15 22:17:40 -04:00
Thomas Harte	81f2952c97	Log just enough to see that this looks like an SN76489 write.	2025-09-15 22:03:37 -04:00
Thomas Harte	dcf9de1a01	Add IO access to the 6522s.	2025-09-15 21:26:36 -04:00
Thomas Harte	95f57f4eeb	Add VIA instances, flesh out 1Mhz space.	2025-09-15 21:23:34 -04:00
Thomas Harte	cbaf841f13	Add 1Mhz bus transitions.	2025-09-15 20:00:29 -04:00
Thomas Harte	8c3b3d98f6	Add error output.	2025-09-15 17:53:41 -04:00
Thomas Harte	b6d5af81b5	Attempt to flesh out the 6502 space.	2025-09-15 17:44:07 -04:00
Thomas Harte	0358853d5a	Permit 6502 to spin forever, doing nothing.	2025-09-15 17:14:17 -04:00
Thomas Harte	ccace48d5a	Declare clock rate, at least.	2025-09-15 14:54:10 -04:00
Thomas Harte	193203bbf7	Wire up enough Mac GUI to get to an empty husk.	2025-09-15 14:53:19 -04:00
Thomas Harte	6713baf86b	Add BBC Micro class	2025-09-14 21:57:09 -04:00