Thomas Harte
1d288b08b6
Attempts the two most basic forms of DOC output.
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Sans interrupts. Or register reads of any variety.
2020-11-19 21:19:27 -05:00
Thomas Harte
34794223b4
For now, at least, c800–cfff is always built-in ROM.
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Otherwise I probably need to extend my c3 logic to cover the other built-in cards (?)
2020-11-18 19:49:45 -05:00
Thomas Harte
98347cb1c3
Starts in the direction of audio support.
2020-11-18 18:39:11 -05:00
Thomas Harte
bb80e53021
Reduces frequency of video flushes.
2020-11-16 21:55:41 -05:00
Thomas Harte
6dfad6a44b
Slightly reduces logging.
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Hopefully soon I can tear the whole lot out.
2020-11-16 21:46:19 -05:00
Thomas Harte
9206ab5dc3
Adds notes to self; implements get_next_sequence_point for video, allowing per-line interrupts.
2020-11-16 14:42:50 -05:00
Thomas Harte
7e39550fc0
Attempts to make JustInTimeActor sequence-point aware.
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With the objective of chopping out a lot of future boilerplate.
2020-11-15 21:58:18 -05:00
Thomas Harte
cdacf280e1
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 16:08:29 -05:00
Thomas Harte
1538a02e18
Better explains concern.
2020-11-14 19:27:20 -05:00
Thomas Harte
f9cec9a102
Attempts also to implement 1Mhz access costs.
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Subject to TODO, and same observation as before: this is as to my current understanding only.
2020-11-14 19:23:01 -05:00
Thomas Harte
adda3d8f42
Attempts a 'full' model of 2.8Mhz access timing.
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i.e. full to my current understanding.
2020-11-14 19:10:41 -05:00
Thomas Harte
ec3ff0da12
Steps towards proper calculation of time.
2020-11-14 18:39:16 -05:00
Thomas Harte
73c38b3b0d
Collapses nested conditionals.
2020-11-14 18:23:31 -05:00
Thomas Harte
edc8050b36
Adds activity indicators.
2020-11-14 18:00:06 -05:00
Thomas Harte
715a1b9cd6
Ensures safe shutdown.
2020-11-12 21:44:51 -05:00
Thomas Harte
86310849eb
Corrects IWM clocking.
2020-11-12 18:09:31 -05:00
Thomas Harte
a2a928e262
Takes a guess at the format of IIgs .po files; wires them through to the actual machine.
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... which still declines to boot.
2020-11-12 18:01:26 -05:00
Thomas Harte
3813e00ca3
Adds the Apple II toggle speaker.
2020-11-11 21:04:38 -05:00
Thomas Harte
a15af1df5e
Attempts to use the other bit of disk drive control, the 5.25"/3.5" select.
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For the record, the ROM thinks it finds some Smartport devices and then attempts to talk to them. Since none is present, it blocks forever.
2020-11-11 17:55:50 -05:00
Thomas Harte
8024bbd721
Provides minor extra detail.
2020-11-11 17:08:56 -05:00
Thomas Harte
ece9382a4e
Also attaches IWM select line.
2020-11-10 18:59:23 -05:00
Thomas Harte
20fd5adb24
Makes a first effort at attaching an IWM.
2020-11-10 18:38:23 -05:00
Thomas Harte
abb350ff5b
Stubs in audio toggle and disk control.
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It appears that ROM 01 now fails because reading the disk interface register doesn't do as expected. ROM 03 starts hitting what should be the IWM and dies in a surplus of logging.
2020-11-09 22:21:52 -05:00
Thomas Harte
54352cb1cb
Stubs in a couple more registers.
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PC now hits $0000. Likely a bug.
2020-11-09 21:54:25 -05:00
Thomas Harte
0ae49b356a
Seems to do enough padding out to get me to my second failing ADB command.
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That's better than failing at the first.
2020-11-09 19:05:48 -05:00
Thomas Harte
287bfeb924
Hacks in 40-column text.
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Hot gossip: my IIgs is reporting a system error. A clue!
2020-11-08 17:01:23 -05:00
Thomas Harte
3bb3d8c5c1
Adds text colour register.
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Oddly this isn't currently being set. So probably another latent fault elsewhere.
2020-11-07 23:14:50 -05:00
Thomas Harte
a51f4122f0
Attempts to respect border colour.
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Though for now my display is just a sea of purple.
2020-11-07 22:03:05 -05:00
Thomas Harte
d37ba62343
Makes first, faltering steps towards video display.
2020-11-07 20:42:34 -05:00
Thomas Harte
699fb0aa4b
Switches to just-in-time video, for easy access to a clock divider.
2020-11-07 19:40:26 -05:00
Thomas Harte
613d4b7c8b
Migrates character ROM handling; supplies one for the IIgs.
2020-11-07 17:45:03 -05:00
Thomas Harte
6b29e1f598
Corrects accesses to switch values.
2020-11-05 21:25:06 -05:00
Thomas Harte
282d0f1ebb
For debugging, adds a dump of anything in the [presumably] text buffer.
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Nothing is there.
2020-11-05 18:17:21 -05:00
Thomas Harte
f466cbadec
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 17:56:20 -05:00
Thomas Harte
46ee98639e
Stubs in $c010.
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Also reduces memory map logging.
2020-11-04 21:35:11 -05:00
Thomas Harte
cc6c0d535c
Stubs in some of the sound GLU registers.
2020-11-04 21:29:44 -05:00
Thomas Harte
78b57e73d5
Hacks in a lying vertical blank value.
2020-11-04 21:18:27 -05:00
Thomas Harte
9e2a6526d1
Corrects interpretation of bit 3 of the state register.
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And attempts to be a bit more careful with the language card in general.
2020-11-04 21:15:10 -05:00
Thomas Harte
d3c7253981
Shifts size-limiting of X and Y to transitions and mutations, away from reads.
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Primarily to remove potential bug-causing complexity — this is easier to debug. But let's see.
2020-11-04 20:35:41 -05:00
Thomas Harte
0178aaee2b
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte.
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(Rather than a preserved but ignored top byte)
2020-11-02 18:55:28 -05:00
Thomas Harte
53f60f7c87
Adds some notes for a pending ADB implementation.
2020-11-01 14:49:04 -05:00
Thomas Harte
2da71acefd
Stubs in the ADB GLU.
2020-10-31 21:00:15 -04:00
Thomas Harte
45f5896b76
Stubs video switches into the IIgs.
2020-10-31 20:39:32 -04:00
Thomas Harte
531a3bb7e6
Ensures RAM is zero-initialised, for now, to aid in repeatable bug finding.
2020-10-31 20:03:23 -04:00
Thomas Harte
e4459b6256
Adds power-on bit to speed register.
2020-10-30 21:50:39 -04:00
Thomas Harte
2be817a6a1
Maps in "the interrupt ROM addresses".
2020-10-30 21:42:43 -04:00
Thomas Harte
a833bb892b
Increases logging substantially.
2020-10-30 20:11:55 -04:00
Thomas Harte
034056d0cd
Adds full 8-bit clock addressing; stubs clock into the IIgs.
2020-10-29 21:38:36 -04:00
Thomas Harte
5a8b8478d2
Corrects unhandled IO assert.
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The IIgs proper is actually waiting on communication with the RTC.
2020-10-28 22:14:02 -04:00
Thomas Harte
6c54699c44
Connects up an SCC.
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Thereby putting my IIgs into its first perpetual loop. Trying to do something with the SCC I haven't implemented yet perhaps?
2020-10-28 22:07:34 -04:00
