Thomas Harte
d8ed8b66f3
Improves carry/extend for ROXL and ROXR.
2019-05-06 21:14:16 -04:00
Thomas Harte
e6ed50383c
Corrects PEA and MOVE.l (An)[+], (xxx).L; also adds an extra test that caught the latter.
2019-05-05 22:47:54 -04:00
Thomas Harte
a873ec97eb
Also previously missing: vector.h.
2019-05-03 14:43:31 -04:00
Thomas Harte
cc8a65780e
Adds further missing includes.
2019-05-03 14:42:36 -04:00
Thomas Harte
c117deb43b
Introduces a couple of missing #includes.
2019-05-03 14:37:05 -04:00
Thomas Harte
291e91375f
Takes a shot at the synchronous bus.
2019-05-03 14:20:59 -04:00
Thomas Harte
1d9608efc7
Alters the order of interrupt bus activity, to bring it into line with a real 68000.
2019-05-02 15:25:43 -04:00
Thomas Harte
bb07206c55
Corrects internet response to work as currently implemented.
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Also makes corrections to the bus error and address error exceptions.
2019-05-01 21:59:06 -04:00
Thomas Harte
f6ac407e4d
Takes further steps towards supporting interrupts.
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Specifically:
* introduces the necessary bus signalling; and
* adds corresponding functional steps.
Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 15:19:24 -04:00
Thomas Harte
078c3135df
The 5/3 split of microcycles appears not accurately to model when lines are tested.
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Therefore I've reverted to a more normative 4:4 form.
2019-04-30 22:09:13 -04:00
Thomas Harte
31bb770fdd
Implement STOPpages, waits for DTack, and bus and address error exceptions.
2019-04-30 19:24:22 -04:00
Thomas Harte
eb4233e2fd
Joins some commonalities, shaving about 150 lines of code.
2019-04-29 22:37:23 -04:00
Thomas Harte
6b4c656849
Reverses order of instruction instantiation, reducing total bus step heft by about 11%.
...
... since that means inserting more complicated instructions before simpler ones in general, making subset finds more likely.
2019-04-29 22:20:18 -04:00
Thomas Harte
1b8fada6aa
Restores accidentally-cropped functionality.
2019-04-29 22:10:00 -04:00
Thomas Harte
977f9ee831
Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time.
2019-04-29 22:08:16 -04:00
Thomas Harte
16fb3b49a5
It leads to a TODO, but implemented decoding and initial setup of STOPpages.
2019-04-29 19:30:00 -04:00
Thomas Harte
05d1eda422
Fixes crossed-over decoding of EORI and ORI.
2019-04-29 17:45:52 -04:00
Thomas Harte
31f318ad43
Fixes MOVE.bw #, (xxx).w.
2019-04-29 17:41:46 -04:00
Thomas Harte
c466b6f9e7
Factors out the [unit testing] stuff of being a trace-checking 68000 bus handler.
2019-04-29 16:11:01 -04:00
Thomas Harte
d9071ee9f1
Starts sketching out the asynchronous bus.
2019-04-29 13:45:53 -04:00
Thomas Harte
97e118abfa
Corrects accidental exclusion of MOVE.bw (xxx).w, [(xxx).w/(xxx).l].
2019-04-28 23:25:46 -04:00
Thomas Harte
412f091d76
Implements a missing form of BTST.
2019-04-28 23:20:50 -04:00
Thomas Harte
ca1f669e64
Implements MOVEP.
...
371 is now the alleged number of missing opcodes. But I'd dare imagine it's more like three or four.
2019-04-28 22:52:54 -04:00
Thomas Harte
0298b1b3b7
Implements LINK and UNLINK.
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Also starts excluding opcodes that I can't determine the mapping of from the list of those tested against.
Due to those two things together, the latter incomplete: 627 opcodes outstanding. But only STOP and MOVEP remain on my list of things to implement prior to exceptions.
2019-04-28 17:12:31 -04:00
Thomas Harte
4b1324de77
Takes a run at TRAPV.
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... to leave 1466 as the unimplemented count.
2019-04-28 15:52:58 -04:00
Thomas Harte
8e8dce9bec
Attempts an implementation of CHK.
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1467 is now the official count of things to implement, though I'm starting to get suspicious.
2019-04-28 15:47:21 -04:00
Thomas Harte
f4350522bf
Implements NBCD.
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Now outstanding: 1891.
2019-04-27 21:29:50 -04:00
Thomas Harte
e2abb66a11
Adds missing addressing modes for ADDA and SUBA.
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... reducing missing opcodes to 1941.
2019-04-27 17:22:26 -04:00
Thomas Harte
ab5fcab9bf
Attempts an implementation of ADDX and SUBX.
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Leaving 2005 non-[A/F]-line instructions.
2019-04-27 16:57:47 -04:00
Thomas Harte
e75b386f7d
Attempts DIVU and DIVS.
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Reportedly leaving 10965 operations now unimplemented.
2019-04-26 22:22:35 -04:00
Thomas Harte
796203859f
Implements PEA.
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This decreases the unimplemented count by 28 from 11841 to 11813.
2019-04-26 13:49:59 -04:00
Thomas Harte
a3b6d2d16e
Corrects test and resolves all instances of opcodes that are valid but shouldn't be.
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The converse case will require implementation of the remaining instructions.
2019-04-25 22:54:58 -04:00
Thomas Harte
dab9bb6575
Implements EXT.
2019-04-25 18:22:19 -04:00
Thomas Harte
c132bda01c
Implements MOVE from SR.
2019-04-25 14:39:32 -04:00
Thomas Harte
4e25bcfcdc
Corrects decoding of AND/OR x, Dn.
2019-04-25 14:19:13 -04:00
Thomas Harte
5725db9234
Corrects calculated-address TAS.
2019-04-25 12:42:05 -04:00
Thomas Harte
8557e563bc
Takes a run at TAS, clarifying bus cycles.
2019-04-25 12:19:40 -04:00
Thomas Harte
002796e5f5
Takes a run at BSET and BCHG.
2019-04-24 23:01:32 -04:00
Thomas Harte
582e4acc11
Implements ANDI/ORI/EOR to SR/CCR.
2019-04-24 17:38:59 -04:00
Thomas Harte
10f75acf71
Causes EXG to function.
2019-04-24 16:32:16 -04:00
Thomas Harte
75a7f7ab22
Inserts missing program fetch for CMPI.bw #, (d8/16...).
2019-04-24 14:45:24 -04:00
Thomas Harte
0bb6b498ce
Simplifies and fixes post-inc MOVE behaviour.
2019-04-24 13:14:25 -04:00
Thomas Harte
958d44a20d
Causes SWAP actually to perform.
2019-04-24 13:06:12 -04:00
Thomas Harte
bb9424d944
Corrects byte increment/decrement actions for A7.
2019-04-24 13:01:08 -04:00
Thomas Harte
033b8e6b36
ADD/SUBQ #, An shouldn't set flags.
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Also, temporarily at least, adds a new means for observing CPU behaviour.
2019-04-24 09:59:54 -04:00
Thomas Harte
7c3ea7b2ea
Resolves additional byte accesses being signalled as word.
2019-04-23 21:23:20 -04:00
Thomas Harte
a08043ae88
Ensures that MOVE.b #, (xxx).l writes only a byte.
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Also rearranges some of the temporary logging functionality.
2019-04-23 19:01:58 -04:00
Thomas Harte
55073b0a52
Corrects a bunch of MOVEs to (d8/16, PC/An, [Xn]).
2019-04-21 22:55:23 -04:00
Thomas Harte
44eb4e51ed
Ensures DBcc properly signals program fetches.
2019-04-21 22:54:20 -04:00
Thomas Harte
b78ea7d24c
Further simplifies CMPA.
2019-04-20 21:23:36 -04:00
