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Commit Graph

27 Commits

Author SHA1 Message Date
Thomas Harte
85c6fb1430 Explained refresh cycles to the all-RAM Z80. 2017-06-19 07:36:11 -04:00
Thomas Harte
d668879ba6 Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates. 2017-06-18 22:03:13 -04:00
Thomas Harte
e1a2580b2a Renamed BusOperation to MachineCycle::Operation. 2017-06-17 21:53:45 -04:00
Thomas Harte
aed2827e7b Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected. 2017-06-12 22:22:00 -04:00
Thomas Harte
8c41a0f0ed Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine. 2017-06-03 17:53:44 -04:00
Thomas Harte
3e9212aaff Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed. 2017-06-03 17:41:45 -04:00
Thomas Harte
d14902700a Minor syntax and wiring fixes. 2017-06-01 22:33:05 -04:00
Thomas Harte
494ce073b5 Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging. 2017-05-31 19:58:57 -04:00
Thomas Harte
2f7f11e2e5 Added diagnosis props. 2017-05-31 06:54:25 -04:00
Thomas Harte
5119997122 Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function. 2017-05-30 22:41:23 -04:00
Thomas Harte
da65bae86e Switched to supplying the bus operation by reference, go guarantee that it isn't null. 2017-05-30 19:24:58 -04:00
Thomas Harte
d290e3d99e Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!) 2017-05-29 16:35:00 -04:00
Thomas Harte
a6a4c5a936 Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures. 2017-05-29 15:57:27 -04:00
Thomas Harte
6b66c8f304 Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84. 2017-05-28 14:50:51 -04:00
Thomas Harte
6575091a78 Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly. 2017-05-22 21:50:34 -04:00
Thomas Harte
41d5dd8679 Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured. 2017-05-22 19:24:11 -04:00
Thomas Harte
f2aae72cc2 Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least. 2017-05-21 20:43:36 -04:00
Thomas Harte
fe8db1873c Added 16-bit ADC and SBC table entries; once again extended logging. 2017-05-21 20:32:06 -04:00
Thomas Harte
08206eea56 This logging has outlived its usefulness for now. 2017-05-21 09:47:53 -04:00
Thomas Harte
103c863534 Through temporarily dramatically increased logging, fixed conditional JP. 2017-05-20 23:03:52 -04:00
Thomas Harte
6766845e21 Filled in most of the loads. 2017-05-19 22:57:43 -04:00
Thomas Harte
62b432c046 Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes. 2017-05-19 21:20:28 -04:00
Thomas Harte
11d05fb3b8 Expanded a little on operations, added an implementation or two. 2017-05-19 19:18:35 -04:00
Thomas Harte
5d3ebcb35a Made a first attempt at LD HL, (nn). 2017-05-17 22:42:30 -04:00
Thomas Harte
17ffd604bf Made an attempt to get the Z80 at least as far as rejecting an opcode. 2017-05-17 21:45:23 -04:00
Thomas Harte
7190f927b7 Factored out the stuff that both all-RAM processors would share, rather than duplicating it. 2017-05-16 21:28:17 -04:00
Thomas Harte
d559d8b901 Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it. 2017-05-16 21:19:17 -04:00