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11,219 Commits 8 Branches 121 Tags 496 MiB
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1260 Commits

Author SHA1 Message Date
Thomas Harte
1c1ce625a7 Vector reads signal VDA. 2022-06-24 10:37:39 -04:00
Thomas Harte
069a057a94 Resolve assumption of arithmetic shifts. 2022-06-24 07:26:07 -04:00
Thomas Harte
4ed3b21bf3 Decimal SBC tweak: negative partial results don't cause carry. 2022-06-23 21:58:09 -04:00
Thomas Harte
a23b0f5122 Map STA (d), y to correct calculator. 2022-06-23 20:57:47 -04:00
Thomas Harte
da552abf75 Fix BIT overflow flag. 2022-06-23 15:24:51 -04:00
Thomas Harte
380b5141fb Be overt about conversion wanted here. 2022-06-23 13:03:26 -04:00
Thomas Harte
66775b2c4e Always consume a second cycle in 16-bit mode. 2022-06-23 12:46:51 -04:00
Thomas Harte
2c12a7d968 Make absolutely sure there's no address bit 24. 2022-06-23 12:12:02 -04:00
Thomas Harte
5a97c09238 Flip internal presumption on the BRK flag. 2022-06-23 11:23:00 -04:00
Thomas Harte
3112376943 Don't include DBR in direct indexed indirect. 2022-06-23 11:03:37 -04:00
Thomas Harte
ecfd17a259 Report a 1 in the stack pointer high byte when in emulation mode. 
It has one internally, it just wasn't previously exposed via this method.
 2022-06-22 15:55:34 -04:00
Thomas Harte
a72dd96dc6 Page boundary crossing is free outside of emulation mode. 2022-06-22 15:31:30 -04:00
Thomas Harte
944e5ebbfa Take another run at IO addresses. 2022-06-22 15:28:11 -04:00
Thomas Harte
76767110b7 Fix overflow for 8-bit calculations; essentially a revert for ADC. 2022-06-22 15:18:47 -04:00
Thomas Harte
7dcfa9eb65 65816: improve decimal calculations, posted IO addresses, read/write during redundant read-modify-write cycle. 2022-06-21 14:33:06 -04:00
Thomas Harte
ec98736bd7 Ensure IO cycles don't produce an address of (PC+1). 2022-06-21 11:41:05 -04:00
Thomas Harte
586ef4810b Add restart_operation_fetch, to aid with testing. 2022-06-18 16:25:57 -04:00
Thomas Harte
a0bc332fe6 Taking a second parse, prefer non-lookup-table solutions. 2022-06-17 11:55:38 -04:00
Thomas Harte
b0ab5b7b62 Simplify Microcycle helpers. 2022-06-16 21:34:24 -04:00
Thomas Harte
dc8103ea82 Fix return address following a STOP. 2022-06-16 15:10:35 -04:00
Thomas Harte
7d00b50e13 Fix upper/lower_data_select; simplify value8_low. 2022-06-15 21:11:31 -04:00
Thomas Harte
12b058867e Correct very minor typo. 2022-06-15 19:34:54 -04:00
Thomas Harte
8ff09a1923 Fix value8_high. 2022-06-15 19:34:49 -04:00
Thomas Harte
62fa0991ed Disallow copying, add some basic asserts. 2022-06-15 19:34:43 -04:00
Thomas Harte
24823233ff Add spurious interrupt support. 2022-06-15 11:00:27 -04:00
Thomas Harte
bd056973ba Don't allow STOP state to block execution. 2022-06-15 10:56:45 -04:00
Thomas Harte
5420fd5aa3 Fix: new status word is still in prefetch. 2022-06-15 10:54:34 -04:00
Thomas Harte
93615f6647 Apply new status before entering STOP loop. 2022-06-15 10:50:03 -04:00
Thomas Harte
0ace9634ce Fix MOVEA. 2022-06-14 21:56:48 -04:00
Thomas Harte
48d51759cd At huge copy-and-paste cost, fix MOVE.l. 2022-06-14 21:22:28 -04:00
Thomas Harte
bfd0b683bf Extend MOVE.b fix to cover MOVE.w. 2022-06-14 17:04:11 -04:00
Thomas Harte
61e0f60e94 Add specialised MOVE.b to correct bus sequencing. 
This is a bit of a trial balloon; .w and .l to come.
 2022-06-13 21:49:00 -04:00
Thomas Harte
7fa715e37a Provide more thorough documentation. 2022-06-13 15:27:23 -04:00
Thomas Harte
e066546c13 Resolve PEA timing errors. 2022-06-13 14:08:42 -04:00
Thomas Harte
4a75691005 Avoid double conditional for CalcEffectiveAddressIdleFor8bitDisplacementAndPreDec. 2022-06-13 10:27:22 -04:00
Thomas Harte
8ada73b283 Use the outer switch for addressing mode dispatch, saving a lot of syntax. 2022-06-13 08:57:49 -04:00
Thomas Harte
2a9a05785c Bus and address error don't affect interrupt level. 2022-06-11 21:10:24 -04:00
Thomas Harte
c3345dd839 Fix MOVEM timing. 2022-06-10 21:52:07 -04:00
Thomas Harte
aec4bf9d45 Correct TAS timing. 2022-06-10 15:57:35 -04:00
Thomas Harte
f8643a62e6 Change RTE and RTR read order. 2022-06-09 21:47:28 -04:00
Thomas Harte
64053d697f Take improved guess at address error stacking order. 2022-06-09 16:17:09 -04:00
Thomas Harte
da8e6737c6 Fix standard exception stack write order. 2022-06-08 16:15:11 -04:00
Thomas Harte
670201fcc2 Reset time debt upon 'reset'. 2022-06-08 16:03:16 -04:00
Thomas Harte
ab35016aae Clear any time debt upon phoney reset. 2022-06-08 15:12:32 -04:00
Thomas Harte
6efb9b24e0 Ensure that a phoney reset gets the proper vector. 2022-06-08 14:44:15 -04:00
Thomas Harte
079c3fd263 Abort address error-causing exceptions before they begin. 2022-06-08 14:43:31 -04:00
Thomas Harte
8cbf929671 Don't duplicate work that the RESET program already does. 2022-06-08 11:42:56 -04:00
Thomas Harte
9009645cea Add 'reset' functions. 2022-06-07 16:55:39 -04:00
Thomas Harte
a4baa33e2f Ensure RTE triggers a stack pointer change if needed. 2022-06-06 16:08:50 -04:00
Thomas Harte
cfafbfd141 Fix interrupt acknowledge cycle: signals and data size. 2022-06-04 21:23:57 -04:00
Thomas Harte
542126194a Capture interrupt input at the end of an access cycle, not the beginning. 
All still a guess.
 2022-06-03 15:39:53 -04:00
Thomas Harte
02b6ea6c46 Factor out would-accept-interrupt test, per uncertainty re: level 7. 2022-06-03 08:31:56 -04:00
Thomas Harte
6fcaf3571e Fix bus/address error exception frame: order and contents. 2022-06-03 08:27:49 -04:00
Thomas Harte
f8e933438e Add missing tail cost. 2022-06-02 12:26:25 -04:00
Thomas Harte
2bd20446bb Merge branch '68000Mk2' of github.com:TomHarte/CLK into 68000Mk2 2022-06-02 05:39:32 -04:00
Thomas Harte
659e4f6987 Include fixed cost of rolls. Which includes providing slightly more information to did_shift. 2022-06-01 20:30:51 -04:00
Thomas Harte
cd5f3c90c2 Ensure proper resumption after a forced exit in will_perform. 2022-06-01 15:27:09 -04:00
Thomas Harte
91a6911a51 Correct ADDA/SUBA timing. 2022-06-01 15:03:03 -04:00
Thomas Harte
0857dd0ae5 Include fixed base cost in MULU and MULS. 2022-06-01 14:05:23 -04:00
Thomas Harte
62ed1ca2fd Fix MOVE CCR permissions. 2022-06-01 09:22:47 -04:00
Thomas Harte
d1298c8863 Correct MOVE timing without breaking PEA, LEA, etc. 2022-06-01 09:06:08 -04:00
Thomas Harte
75e85b80aa Factor out the common stuff of exception state. 2022-06-01 08:20:33 -04:00
Thomas Harte
d6f72d9862 Avoid runtime checking of instruction supervisor requirements. 2022-05-29 14:56:44 -04:00
Thomas Harte
dbf7909b85 Fix timing of CMPM. 2022-05-29 14:49:42 -04:00
Thomas Harte
57aa8d2f17 Correct timing of ADDQ. 2022-05-29 14:34:06 -04:00
Thomas Harte
35e73b77f4 Fix interrupt stack frame. 2022-05-27 21:55:17 -04:00
Thomas Harte
d17d77714f Remove outdated TODO. 2022-05-27 15:40:06 -04:00
Thomas Harte
e8dd8215ba Tweak per empirical results. 2022-05-27 15:39:02 -04:00
Thomas Harte
e11990e453 Make an attempt at DIVS timing. 2022-05-27 15:38:54 -04:00
Thomas Harte
165ebe8ae3 Add time calculation for MULU and MULS. 2022-05-27 15:38:14 -04:00
Thomas Harte
e746637bee Fill in dynamic cost of shifts. 2022-05-27 15:38:08 -04:00
Thomas Harte
67b340fa5e Fix interrupt request address. 2022-05-27 10:33:36 -04:00
Thomas Harte
c97245e626 Fix CalcEA timing; make MOVEfromSR a read-modify-write. 2022-05-27 10:32:28 -04:00
Thomas Harte
367ad8079a Add a call to set register state with population of the prefetch. 2022-05-25 20:22:05 -04:00
Thomas Harte
80c1bedffb Eliminate false prefetch for BSR. 2022-05-25 16:32:02 -04:00
Thomas Harte
56ad6d24ee Fix ANDI/ORI/EORI to CCR/SR timing. 2022-05-25 16:20:26 -04:00
Thomas Harte
4ad0e04c23 Fix macro for n being an expression. 2022-05-25 16:05:45 -04:00
Thomas Harte
ee58301a46 Add RaiseException macro. 2022-05-25 15:45:09 -04:00
Thomas Harte
72425fc2e1 Fix bus data size of MOVE.b xx, -(An). 2022-05-25 13:00:36 -04:00
Thomas Harte
a5f2dfbc0c Initialise registers to 0 for better testability. 
TODO: is this the real initial state?
 2022-05-25 11:47:42 -04:00
Thomas Harte
5db6a937cb Have TRAP and TRAPV push the next instruction address to the stack. 2022-05-25 11:47:21 -04:00
Thomas Harte
9709b9b1b1 Standard exceptions don't raise the interrupt level. 2022-05-25 11:37:39 -04:00
Thomas Harte
5872e0ea4a Resolve MOVE.l xx, -(An) write target. 2022-05-25 08:15:18 -04:00
Thomas Harte
f43d27541b Avoid attempt to establish operand flags for undefined opcodes. 2022-05-24 15:53:12 -04:00
Thomas Harte
0f7cb2fa5a Attempt to honour the trace flag. 2022-05-24 15:47:47 -04:00
Thomas Harte
01e93ba916 Make an attempt at bus/address error. 2022-05-24 15:42:50 -04:00
Thomas Harte
780954f27b Add TRAP, TRAPV. 2022-05-24 15:14:46 -04:00
Thomas Harte
6f048de973 Pull unrecognised instruction handling into the usual switch table. 2022-05-24 12:42:34 -04:00
Thomas Harte
0dfaa7d9cf Interrupt fixes: supply proper address, raise level, fetch from vector. 2022-05-24 12:16:06 -04:00
Thomas Harte
eab720f6ea Ensure proper transition from unrecognised instructions. 2022-05-24 12:16:00 -04:00
Thomas Harte
a7e8aef9d3 Add MOVEA, be slightly more careful about next_operand_. 2022-05-24 11:30:09 -04:00
Thomas Harte
df54f1f1b7 Update TODO. 2022-05-24 11:06:05 -04:00
Thomas Harte
9e3c2b68d7 Eliminate potential future implicit conversion warnings. 2022-05-24 11:05:24 -04:00
Thomas Harte
3349bcaaed Attempt interrupt support. 2022-05-24 10:53:59 -04:00
Thomas Harte
3a4fb81242 Add a dummy STOP state. 2022-05-24 10:25:40 -04:00
Thomas Harte
1df3ad0671 Ensure TAS responds to VPA, BERR. 2022-05-24 09:17:58 -04:00
Thomas Harte
523cdd859b Add bus and address error, and VPA checks. 2022-05-24 09:08:31 -04:00
Thomas Harte
b037c76da6 Add public interface for everything except HALT and BUS REQ/etc. 
... neither of which are used by machines I currently implement.
 2022-05-23 20:55:01 -04:00
Thomas Harte
9cac4ca317 Add MOVE to/from USP. 2022-05-23 20:42:41 -04:00
Thomas Harte
34e5f39571 Ensure that running exactly up to a boundary gives the bus handler the next microcycle to contemplate. 2022-05-23 15:11:33 -04:00
Thomas Harte
e0a279344c Codify the existence of special cases, implement NOP and RESET. 2022-05-23 15:09:46 -04:00
Thomas Harte
e2f4db3e45 Shuffle more of the flow controller methods into their proper place. 2022-05-23 12:06:14 -04:00
Thomas Harte
c1837af84a Add notes to self on work remaining. 2022-05-23 11:02:31 -04:00
Thomas Harte
a87f6a28c9 Fix LINK A7. 2022-05-23 10:43:17 -04:00
Thomas Harte
98325325b1 Fix UNLINK A7. 2022-05-23 10:27:44 -04:00
Thomas Harte
26bf66e3f8 Fix shifts and rolls. 2022-05-23 10:09:46 -04:00
Thomas Harte
363cd97154 Resolve double definition of did_shift. 2022-05-23 10:07:24 -04:00
Thomas Harte
c6b3281274 Attempt the shifts and rolls. 2022-05-23 09:29:19 -04:00
Thomas Harte
1e8adc2bd9 Fix MOVEP to R. 2022-05-23 09:00:37 -04:00
Thomas Harte
c73021cf3c Implement MOVE. 2022-05-23 08:46:06 -04:00
Thomas Harte
1b3acf9cd8 Eliminate assumption. 2022-05-23 08:18:37 -04:00
Thomas Harte
c8ede400eb Fix RTE. 2022-05-22 21:17:28 -04:00
Thomas Harte
269263eecf Implement RTE, RTS, RTR. 2022-05-22 21:16:38 -04:00
Thomas Harte
faef5633f8 Ensure MOVE from SR has an effective address to write to. 2022-05-22 20:52:00 -04:00
Thomas Harte
7d1f1a3175 Implement MOVE [to/from] [CCR/SR]. 2022-05-22 19:45:22 -04:00
Thomas Harte
4e34727195 Fully implement TAS. 2022-05-22 16:14:03 -04:00
Thomas Harte
1dd6ed6ae3 Implement TAS Dn, with detour for other TASes. 2022-05-22 16:08:30 -04:00
Thomas Harte
3b68b9a83b Implement PEA. 2022-05-22 11:27:38 -04:00
Thomas Harte
4279ce87ea Implement LEA. 2022-05-22 08:29:12 -04:00
Thomas Harte
3c1c4f89e9 Add MULU/S functionality, though not timing. 2022-05-22 08:02:32 -04:00
Thomas Harte
4a6512f5d5 Reduce dispatch boilerplate. 2022-05-22 07:39:16 -04:00
Thomas Harte
284f23c6ea Implement JMP. 2022-05-22 07:16:38 -04:00
Thomas Harte
11a9a5c126 Use common macros for the two forms of Perform. 2022-05-22 07:08:14 -04:00
Thomas Harte
4993801741 Add missing prefetch to BSET, BCHG, BCLR. 2022-05-21 21:05:05 -04:00
Thomas Harte
4b35899a12 Bcc: properly establish offset. 2022-05-21 20:59:34 -04:00
Thomas Harte
1304e930eb DBcc is two-operand. 2022-05-21 20:06:03 -04:00
Thomas Harte
94288d5a94 Excludes DBcc from standard operand fetch. 2022-05-21 19:53:28 -04:00
Thomas Harte
3811ab1b82 Fix the two 8bit-with-displacement effective address Calc steps. 2022-05-21 16:20:01 -04:00
Thomas Harte
f97d2a0eb9 Add DIVU/DIVS, at least as far as getting the correct numeric result. 2022-05-21 15:56:09 -04:00
Thomas Harte
2258434326 Ensure proper return addresses are calculated for JSR. 2022-05-21 14:28:44 -04:00
Thomas Harte
e46a3c4046 Implement JSR. 2022-05-21 10:29:36 -04:00
Thomas Harte
0e4cfde657 Fix MOVEM predec. 2022-05-21 08:17:39 -04:00
Thomas Harte
4bd9c36922 Fix postincrement mode. 2022-05-20 21:01:23 -04:00
Thomas Harte
256da43fe5 Fix MOVEM other than postinc and predec. 2022-05-20 20:47:54 -04:00
Thomas Harte
a818650027 Add a faulty attempt at MOVEM. 2022-05-20 18:48:19 -04:00
Thomas Harte
9d79e64f5c Add a mere calculate effective address pathway. 
Plus a lot of waffle to try to justify the further code duplication.
 2022-05-20 16:23:52 -04:00
Thomas Harte
ee942c5c17 Fix PC-relative fetches. 2022-05-20 14:42:51 -04:00
Thomas Harte
d157819c49 Implement the various to-[SR/CCR] actions, which do a 'repeat' prefetch. 
(which isn't exactly a repeat, at least in the SR cases, because the function code might have changed)
 2022-05-20 14:29:14 -04:00
Thomas Harte
2d91fb5441 Implement MOVEP. 2022-05-20 14:22:32 -04:00
Thomas Harte
81431a5453 Attempt BTST, BCHG, BCLR and BSET. 2022-05-20 12:58:45 -04:00
Thomas Harte
b4978d1452 Implement BSR, adding one more test file to the working set. 2022-05-20 12:40:35 -04:00
Thomas Harte
45e9648b8c Implement Bcc. 2022-05-20 12:04:43 -04:00
Thomas Harte
4327af3760 DBcc: add write-back. 2022-05-20 11:37:18 -04:00
Thomas Harte
860cc63e21 Attempt DBcc. 2022-05-20 11:32:06 -04:00
Thomas Harte
452dd3ccfd Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000. 2022-05-20 11:20:23 -04:00
Thomas Harte
e5c1621382 Add missing fallthrough, patterns for all ADDs and SUBs. 2022-05-20 07:02:02 -04:00
Thomas Harte
1ee9c585ca Fix segue into second operand. 2022-05-19 19:38:42 -04:00
Thomas Harte
efe5a5ac26 Signal will_perform even for invalid instructions. 2022-05-19 18:50:43 -04:00
Thomas Harte
334e3ec529 Add privilege and instruction error exceptions; permit two operands to be stored. 2022-05-19 16:55:16 -04:00
Thomas Harte
282c4121d6 CLR also follows the NEGX/NEG/NOT pattern. 2022-05-19 16:30:08 -04:00