Thomas Harte
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f2aae72cc2
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Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least.
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2017-05-21 20:43:36 -04:00 |
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Thomas Harte
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fe8db1873c
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Added 16-bit ADC and SBC table entries; once again extended logging.
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2017-05-21 20:32:06 -04:00 |
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Thomas Harte
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08206eea56
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This logging has outlived its usefulness for now.
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2017-05-21 09:47:53 -04:00 |
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Thomas Harte
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103c863534
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Through temporarily dramatically increased logging, fixed conditional JP.
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2017-05-20 23:03:52 -04:00 |
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Thomas Harte
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6766845e21
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Filled in most of the loads.
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2017-05-19 22:57:43 -04:00 |
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Thomas Harte
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62b432c046
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Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.
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2017-05-19 21:20:28 -04:00 |
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Thomas Harte
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11d05fb3b8
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Expanded a little on operations, added an implementation or two.
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2017-05-19 19:18:35 -04:00 |
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Thomas Harte
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5d3ebcb35a
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Made a first attempt at LD HL, (nn).
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2017-05-17 22:42:30 -04:00 |
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Thomas Harte
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17ffd604bf
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Made an attempt to get the Z80 at least as far as rejecting an opcode.
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2017-05-17 21:45:23 -04:00 |
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Thomas Harte
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7190f927b7
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Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
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2017-05-16 21:28:17 -04:00 |
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Thomas Harte
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d559d8b901
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Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
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2017-05-16 21:19:17 -04:00 |
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