Thomas Harte
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fadbfdf801
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Added DJNZ test.
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2017-06-19 21:31:56 -04:00 |
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Thomas Harte
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cb277b8d1e
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Added JP and JR tests.
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2017-06-19 21:27:23 -04:00 |
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Thomas Harte
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234f14dbbe
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Tests were at fault; all passing now.
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2017-06-19 21:14:40 -04:00 |
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Thomas Harte
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99ede3a9ef
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BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
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2017-06-19 21:04:14 -04:00 |
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Thomas Harte
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378233f53d
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Extended to BITs and SETs, accruing three new failures.
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2017-06-19 21:01:30 -04:00 |
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Thomas Harte
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f903408980
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Caught up on comments.
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2017-06-19 20:53:22 -04:00 |
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Thomas Harte
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b684254908
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Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
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2017-06-19 20:33:34 -04:00 |
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Thomas Harte
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351d90ca55
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Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.
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2017-06-19 20:04:55 -04:00 |
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Thomas Harte
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23177df26a
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Added various tests of the basic ALU ops.
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2017-06-19 19:53:26 -04:00 |
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Thomas Harte
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ba15371948
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Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
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2017-06-19 19:47:00 -04:00 |
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Thomas Harte
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8d60734737
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Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
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2017-06-19 19:17:54 -04:00 |
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Thomas Harte
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002098d496
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The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
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2017-06-19 07:45:41 -04:00 |
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Thomas Harte
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85c5c4405a
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Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
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2017-06-19 07:30:01 -04:00 |
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Thomas Harte
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d668879ba6
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Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
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2017-06-18 22:03:13 -04:00 |
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Thomas Harte
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e1a2580b2a
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Renamed BusOperation to MachineCycle::Operation.
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2017-06-17 21:53:45 -04:00 |
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Thomas Harte
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b6f51474ff
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Ensured that -description can handle the newly-captured bus actions.
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2017-06-17 18:20:30 -04:00 |
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Thomas Harte
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0f18768091
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Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.
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2017-06-17 18:19:25 -04:00 |
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Thomas Harte
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50cd617bd9
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Ensured test raises only the intentional failure exceptions.
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2017-06-15 22:33:46 -04:00 |
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Thomas Harte
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838b818cd3
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Finished transcribing first page of machine cycle documentation; several failures contained.
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2017-06-15 22:19:49 -04:00 |
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Thomas Harte
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cf795562bf
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Continued filling in tests, fleshing out what the test machine captures as a result.
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2017-06-15 20:59:59 -04:00 |
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Thomas Harte
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ac37424878
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Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
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2017-06-15 19:06:59 -04:00 |
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Thomas Harte
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aed2827e7b
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Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
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2017-06-12 22:22:00 -04:00 |
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Thomas Harte
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a48616a138
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Fixed reference to Swift-world MachineDocument for the ZX81 file type.
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2017-06-12 18:51:11 -04:00 |
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Thomas Harte
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8222aac9e3
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Added an official declaration of support for ZX81 files.
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2017-06-11 21:40:41 -04:00 |
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Thomas Harte
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77aa3c187e
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Rebranded ZX80O as ZX80O81P, with an eye to making it accept ZX81 .p files. Adjusted the initial selection part of the static analyser appropriately.
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2017-06-11 21:38:32 -04:00 |
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Thomas Harte
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8116f85479
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Allowed the static analyser to specify a ZX80 or 81, and a memory model. Neither is respected yet in the machine.
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2017-06-11 19:12:20 -04:00 |
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Thomas Harte
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50be3a24fe
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Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be.
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2017-06-11 13:30:08 -04:00 |
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Thomas Harte
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7e10c7f9d8
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Relocated the ZX80/81 concept of a 'file' out from Tape into Data, given that it's an exact duplicate of memory.
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2017-06-08 19:09:51 -04:00 |
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Thomas Harte
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60300851ea
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Started sketching out a tape parser for ZX80 and '81 files. I think this'll help me to verify whether the .O input is working.
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2017-06-07 10:12:13 -04:00 |
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Thomas Harte
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8c66e1d99d
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Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data.
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2017-06-06 17:53:23 -04:00 |
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Thomas Harte
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cc4cb45e9d
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Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court.
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2017-06-06 09:25:18 -04:00 |
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Thomas Harte
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c485c460f7
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Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.
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2017-06-04 18:08:35 -04:00 |
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Thomas Harte
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b0a7c58287
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Fixed project to point to the XIB I actually want to keep; fixed that XIB to have the correct contents.
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2017-06-04 17:57:37 -04:00 |
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Thomas Harte
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d2637123c4
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Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.
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2017-06-04 17:55:19 -04:00 |
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Thomas Harte
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02b7c3d1b0
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Added the necessary wiring to get into a ZX80/81-oriented part of the static analyser, which could in principle post a ZX80 target.
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2017-06-04 17:04:06 -04:00 |
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Thomas Harte
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8c1769f157
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Made a quick attempt at serialising from ZX80 .O to waves.
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2017-06-04 16:59:26 -04:00 |
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Thomas Harte
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655809517c
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Ensured that there is a subclass of file that is entrusted to load .O/.80 files, and that the code routes such files to it, noting that it should consider whether a ZX80 is required.
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2017-06-04 16:37:03 -04:00 |
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Thomas Harte
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2190f60a89
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Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.
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2017-06-04 15:46:35 -04:00 |
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Thomas Harte
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0eebfdb4cc
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Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.
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2017-06-04 15:39:37 -04:00 |
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Thomas Harte
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7811374b0f
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Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).
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2017-06-04 15:07:07 -04:00 |
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Thomas Harte
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87095b0578
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Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures.
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2017-06-04 14:04:26 -04:00 |
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Thomas Harte
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b642d9f712
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Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
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2017-06-03 21:54:42 -04:00 |
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Thomas Harte
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fd6623b5a5
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Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
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2017-06-03 21:22:16 -04:00 |
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Thomas Harte
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b304c3a4b9
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Eliminated the 6502's reliance on the micro-op scheduler.
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2017-06-03 20:30:07 -04:00 |
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Thomas Harte
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b3da16911f
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Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.
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2017-06-03 18:42:54 -04:00 |
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Thomas Harte
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e52892f75b
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Added a test of interrupt mode 1.
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2017-06-03 18:16:13 -04:00 |
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Thomas Harte
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8c41a0f0ed
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Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
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2017-06-03 17:53:44 -04:00 |
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Thomas Harte
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3e9212aaff
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Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
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2017-06-03 17:41:45 -04:00 |
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Thomas Harte
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d14902700a
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Minor syntax and wiring fixes.
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2017-06-01 22:33:05 -04:00 |
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Thomas Harte
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c95c32a9fe
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Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.
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2017-06-01 22:31:04 -04:00 |
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