192 Commits

Author	SHA1	Message	Date
Thomas Harte	fadbfdf801	Added DJNZ test.	2017-06-19 21:31:56 -04:00
Thomas Harte	cb277b8d1e	Added JP and JR tests.	2017-06-19 21:27:23 -04:00
Thomas Harte	234f14dbbe	Tests were at fault; all passing now.	2017-06-19 21:14:40 -04:00
Thomas Harte	99ede3a9ef	BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).	2017-06-19 21:04:14 -04:00
Thomas Harte	378233f53d	Extended to BITs and SETs, accruing three new failures.	2017-06-19 21:01:30 -04:00
Thomas Harte	f903408980	Caught up on comments.	2017-06-19 20:53:22 -04:00
Thomas Harte	b684254908	Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.	2017-06-19 20:33:34 -04:00
Thomas Harte	351d90ca55	Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.	2017-06-19 20:04:55 -04:00
Thomas Harte	23177df26a	Added various tests of the basic ALU ops.	2017-06-19 19:53:26 -04:00
Thomas Harte	ba15371948	Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.	2017-06-19 19:47:00 -04:00
Thomas Harte	8d60734737	Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.	2017-06-19 19:17:54 -04:00
Thomas Harte	002098d496	The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.	2017-06-19 07:45:41 -04:00
Thomas Harte	85c5c4405a	Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.	2017-06-19 07:30:01 -04:00
Thomas Harte	d668879ba6	Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.	2017-06-18 22:03:13 -04:00
Thomas Harte	e1a2580b2a	Renamed BusOperation to MachineCycle::Operation.	2017-06-17 21:53:45 -04:00
Thomas Harte	b6f51474ff	Ensured that -description can handle the newly-captured bus actions.	2017-06-17 18:20:30 -04:00
Thomas Harte	0f18768091	Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.	2017-06-17 18:19:25 -04:00
Thomas Harte	50cd617bd9	Ensured test raises only the intentional failure exceptions.	2017-06-15 22:33:46 -04:00
Thomas Harte	838b818cd3	Finished transcribing first page of machine cycle documentation; several failures contained.	2017-06-15 22:19:49 -04:00
Thomas Harte	cf795562bf	Continued filling in tests, fleshing out what the test machine captures as a result.	2017-06-15 20:59:59 -04:00
Thomas Harte	ac37424878	Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.	2017-06-15 19:06:59 -04:00
Thomas Harte	aed2827e7b	Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.	2017-06-12 22:22:00 -04:00
Thomas Harte	50be3a24fe	Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be.	2017-06-11 13:30:08 -04:00
Thomas Harte	2190f60a89	Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.	2017-06-04 15:46:35 -04:00
Thomas Harte	0eebfdb4cc	Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.	2017-06-04 15:39:37 -04:00
Thomas Harte	7811374b0f	Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).	2017-06-04 15:07:07 -04:00
Thomas Harte	87095b0578	Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures.	2017-06-04 14:04:26 -04:00
Thomas Harte	b642d9f712	Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.	2017-06-03 21:54:42 -04:00
Thomas Harte	fd6623b5a5	Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.	2017-06-03 21:22:16 -04:00
Thomas Harte	b3da16911f	Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.	2017-06-03 18:42:54 -04:00
Thomas Harte	e52892f75b	Added a test of interrupt mode 1.	2017-06-03 18:16:13 -04:00
Thomas Harte	8c41a0f0ed	Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.	2017-06-03 17:53:44 -04:00
Thomas Harte	3e9212aaff	Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.	2017-06-03 17:41:45 -04:00
Thomas Harte	d14902700a	Minor syntax and wiring fixes.	2017-06-01 22:33:05 -04:00
Thomas Harte	c95c32a9fe	Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.	2017-06-01 22:31:04 -04:00
Thomas Harte	494ce073b5	Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.	2017-05-31 19:58:57 -04:00
Thomas Harte	5ff73faf48	Ensured Zexall can pass.	2017-05-31 19:55:06 -04:00
Thomas Harte	2f7f11e2e5	Added diagnosis props.	2017-05-31 06:54:25 -04:00
Thomas Harte	5119997122	Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.	2017-05-30 22:41:23 -04:00
Thomas Harte	244b5ba3c2	Added a proper termination condition for Zexall and, for now, a Mhz counter.	2017-05-30 18:32:38 -04:00
Thomas Harte	960de7bd7b	Marginally reduced test machine costs based on usage.	2017-05-30 11:59:07 -04:00
Thomas Harte	4d4695032c	Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end.	2017-05-29 21:46:00 -04:00
Thomas Harte	6d22f6fcd5	Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being.	2017-05-29 17:17:17 -04:00
Thomas Harte	8bfaa487ce	Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).	2017-05-29 17:13:24 -04:00
Thomas Harte	267b2add9a	Adjusted for where FUSE nominally places timestamps. Down to 92 failures.	2017-05-29 16:44:07 -04:00
Thomas Harte	d290e3d99e	Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)	2017-05-29 16:35:00 -04:00
Thomas Harte	a6a4c5a936	Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.	2017-05-29 15:57:27 -04:00
Thomas Harte	ed7b07c8b1	Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct.	2017-05-29 11:54:27 -04:00
Thomas Harte	d83dd17738	[DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed.	2017-05-29 11:40:56 -04:00
Thomas Harte	9ade0dcae3	One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison.	2017-05-29 11:06:23 -04:00