Thomas Harte
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74817f6664
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With a history of three pulses, this can track up a 10% sine variation in a 1010101 stream. So I guess this'll do for now?
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2016-07-14 19:54:48 -04:00 |
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Thomas Harte
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ac1bc588dd
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Improved factoring and increased window of testing, causing both the fast and slow tests to show framing errors.
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2016-07-14 07:12:02 -04:00 |
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Thomas Harte
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d1fe07f14d
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Added test of perfect DPLL input timing.
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2016-07-12 21:42:23 -04:00 |
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Thomas Harte
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d8334edf4a
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Started trying to clean up, including commuting the C1540 source file name to match its class name but mainly by adding documentation.
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2016-07-10 07:46:20 -04:00 |
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Thomas Harte
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656cd211d7
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Was transmitting bit levels backwards (probably?); 1540 now acknowledges byte received.
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2016-07-09 18:06:49 -04:00 |
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Thomas Harte
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01746f0512
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This is probably a valid test. But I'm not completely sure. Time to figure out what's happening on the 1540 end.
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2016-07-09 18:01:04 -04:00 |
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Thomas Harte
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cd84c35552
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Whoops, one bit too short.
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2016-07-09 17:51:46 -04:00 |
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Thomas Harte
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cd362b46b3
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This is a valid attempt to send a whole byte, I think.
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2016-07-09 17:51:04 -04:00 |
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Thomas Harte
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3560babd7e
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Got back to a failing test, now while trying to transmit a whole byte. Good stuff!
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2016-07-09 17:39:51 -04:00 |
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Thomas Harte
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66caa3c6dc
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Fixed setup of bridge class.
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2016-07-09 17:23:43 -04:00 |
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Thomas Harte
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bf03985ea4
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Here's an instantly failing test...
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2016-07-09 17:22:10 -04:00 |
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Thomas Harte
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da6fe2e983
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This should be enough of a shell to write some actual tests.
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2016-07-09 15:47:53 -04:00 |
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Thomas Harte
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865eb421cd
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Quick on-disk tidy up.
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2016-07-09 15:44:55 -04:00 |
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Thomas Harte
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7cc4bf3fe7
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Hit and hope is getting me nowhere. Time to unit test this thing.
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2016-07-09 15:40:25 -04:00 |
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Thomas Harte
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b322baff2f
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Added CLI/SEI pair test.
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2016-06-29 19:42:39 -04:00 |
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Thomas Harte
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db7c6430b5
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Fixed Klaus Dormann termination condition.
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2016-06-29 19:16:34 -04:00 |
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Thomas Harte
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6419d9c485
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Added a single IRQ test case, discovering that I'm two cycles short. Whoops!
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2016-06-28 21:29:43 -04:00 |
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Thomas Harte
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d5e50f5ea0
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Got a bit more explicit about how ports are identified on the 6522.
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2016-06-26 12:30:01 -04:00 |
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Thomas Harte
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25a5455d33
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Completed bridge interface.
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2016-06-20 21:07:01 -04:00 |
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Thomas Harte
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fe17d1778c
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Expanded 6532 tests substantially, beefing up implementation to match.
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2016-06-20 21:02:42 -04:00 |
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Thomas Harte
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d5aaad396e
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Added a TODO on my lack of knowledge.
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2016-06-19 20:13:31 -04:00 |
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Thomas Harte
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7cf6008e7c
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Started some very basic RIOT unit tests; corrected to pass.
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2016-06-19 20:12:47 -04:00 |
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Thomas Harte
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f4915c5ad6
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Fixed test and added basic implementation of data direction.
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2016-06-18 17:17:03 -04:00 |
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Thomas Harte
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eea850cd12
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Added a deliberately failing data direction test.
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2016-06-18 16:40:01 -04:00 |
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Thomas Harte
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2282b59768
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Added a quick latching test, and shortened test messages, albeit that they're still displeasingly boilerplate.
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2016-06-18 16:10:46 -04:00 |
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Thomas Harte
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5d26cd85a3
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Wrote test case for what appears to be correct timer behaviour if those were acting in isolation. Ensured implementation matches test case.
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2016-06-18 14:30:23 -04:00 |
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Thomas Harte
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394902f409
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Switched to clocking the 6522 by the half-cycle. Very trivial test now passes.
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2016-06-18 13:57:10 -04:00 |
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Thomas Harte
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06fb2ff1c7
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Started endeavouring to sketch out the boilerplate for writing a 6522 test harness. Added a default implementation of synchronise to the 6522 too, since not everybody is going to want one.
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2016-06-18 09:28:46 -04:00 |
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Thomas Harte
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9b64f64db7
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Attempted to normalise some style decisions.`
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2016-04-24 22:32:24 -04:00 |
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Thomas Harte
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675070c5dd
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Very, _very_ minor: switched to normal C++ constructor syntax for simple variable initialisation.
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2015-12-06 16:53:37 -05:00 |
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Thomas Harte
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cc98534f94
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Added test for NOP, discovering the undocumented ones to be the incorrect length.
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2015-08-13 07:32:50 +01:00 |
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Thomas Harte
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6616265d93
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Fixed collision tests, added a few more timing tests.
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2015-08-13 03:33:45 +01:00 |
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Thomas Harte
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dd0f17130a
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Found and fixed some timing errors in absolute indexed and in (indirect), y addressing modes: neither is able in write or read-modify-write modes to shave a cycle as then can when reading.
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2015-08-13 02:58:39 +01:00 |
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Thomas Harte
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975836c30f
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Added a quick snippet test, discovering that I've cut a cycle from read/modify/writes.
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2015-08-13 02:18:41 +01:00 |
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Thomas Harte
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503d684af0
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Added a couple of timing tests, both of which seem to pass for now.
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2015-08-13 01:55:23 +01:00 |
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Thomas Harte
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e8f70398c1
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Added one basic timing test, for now: implied nop should be two cycles.
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2015-08-13 01:06:56 +01:00 |
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Thomas Harte
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d19f8ed507
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Removed the implicit reset upon 6502 startup, adding a reset line. Hence all tests now pass again. Added an empty shell for timing tests, the all-RAM 6502 now counting bus cycles.
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2015-08-13 00:51:06 +01:00 |
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Thomas Harte
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53dd5c8f16
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Trying to fix my RDY line emulation. Switched to PAL timings, at least temporarily, since it's starting to make a difference.
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2015-07-31 16:44:53 -04:00 |
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Thomas Harte
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20c2d98b9a
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Converted remaining spaces to real tabs.
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2015-07-30 20:51:32 -04:00 |
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Thomas Harte
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6252f6030f
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Switched to idiomatic source name, ensured latest project name is in all appropriate header places, threw texture coordinates slightly into the shader mix.
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2015-07-26 15:25:11 -04:00 |
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Thomas Harte
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5160b6bbb8
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Separated out different test suites into different XCTest subclasses.
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2015-07-16 20:52:16 -04:00 |
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Thomas Harte
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24c0579b94
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Shuffled things and guessed at things until the Xcode project was happy being subservient to the project proper.
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2015-07-16 20:27:31 -04:00 |
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