Merge pull request #750 from TomHarte/CatchupCap

Avoids trying to paper over huge gaps in running time.

.editorconfig

@@ -0,0 +1,6 @@
+[*]
+charset = utf-8
+indent_style = tab
+indent_size = 4
+trim_trailing_whitespace = true
+

.github/workflows/ccpp.yml

@@ -0,0 +1,22 @@
+name: SDL/Ubuntu
+
+on:
+  push:
+    branches: 
+      - master
+
+  pull_request:
+    branches: 
+      - master
+
+jobs:
+  build:
+
+    runs-on: ubuntu-latest
+    
+    steps:
+    - uses: actions/checkout@v1
+    - name: Install dependencies
+      run: sudo apt-get --allow-releaseinfo-change update; sudo apt-get install libsdl2-dev scons
+    - name: Make
+      run: cd OSBindings/SDL; scons

.travis.yml

@@ -1,13 +0,0 @@
-# language: objective-c
-# osx_image: xcode8.2
-# xcode_project: OSBindings/Mac/Clock Signal.xcodeproj
-# xcode_scheme: Clock Signal
-# xcode_sdk: macosx10.12
-
-language: cpp
-before_install:
-	- sudo apt-get install libsdl2-dev
-script: cd OSBindings/SDL && scons
-compiler:
-	- clang
-	- gcc

Activity/Observer.hpp

@@ -24,13 +24,13 @@ namespace Activity {
 class Observer {
 	public:
 		/// Announces to the receiver that there is an LED of name @c name.
-		virtual void register_led(const std::string &name) = 0;
+		virtual void register_led(const std::string &name) {}
 
 		/// Announces to the receiver that there is a drive of name @c name.
-		virtual void register_drive(const std::string &name) = 0;
+		virtual void register_drive(const std::string &name) {}
 
 		/// Informs the receiver of the new state of the LED with name @c name.
-		virtual void set_led_status(const std::string &name, bool lit) = 0;
+		virtual void set_led_status(const std::string &name, bool lit) {}
 
 		enum class DriveEvent {
 			StepNormal,
@@ -39,11 +39,10 @@ class Observer {
 		};
 
 		/// Informs the receiver that the named event just occurred for the drive with name @c name.
-		virtual void announce_drive_event(const std::string &name, DriveEvent event) = 0;
+		virtual void announce_drive_event(const std::string &name, DriveEvent event) {}
 
 		/// Informs the receiver of the motor-on status of the drive with name @c name.
-		virtual void set_drive_motor_status(const std::string &name, bool is_on) = 0;
-
+		virtual void set_drive_motor_status(const std::string &name, bool is_on) {}
 };
 
 }

Analyser/Dynamic/ConfidenceCounter.hpp

@@ -22,7 +22,7 @@ namespace Dynamic {
 class ConfidenceCounter: public ConfidenceSource {
 	public:
 		/*! @returns The computed probability, based on the history of events. */
-		float get_confidence() override;
+		float get_confidence() final;
 
 		/*! Records an event that implies this is the appropriate class: pushes probability up towards 1.0. */
 		void add_hit();

Analyser/Dynamic/ConfidenceSummary.hpp

@@ -32,7 +32,7 @@ class ConfidenceSummary: public ConfidenceSource {
 			const std::vector<float> &weights);
 
 		/*! @returns The weighted sum of all sources. */
-		float get_confidence() override;
+		float get_confidence() final;
 
 	private:
 		std::vector<ConfidenceSource *> sources_;

Analyser/Dynamic/MultiMachine/Implementation/MultiCRTMachine.cpp

@@ -13,7 +13,7 @@
 
 using namespace Analyser::Dynamic;
 
-MultiCRTMachine::MultiCRTMachine(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines, std::mutex &machines_mutex) :
+MultiCRTMachine::MultiCRTMachine(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines, std::recursive_mutex &machines_mutex) :
 	machines_(machines), machines_mutex_(machines_mutex), queues_(machines.size()) {
 	speaker_ = MultiSpeaker::create(machines);
 }
@@ -25,7 +25,7 @@ void MultiCRTMachine::perform_parallel(const std::function<void(::CRTMachine::Ma
 	std::condition_variable condition;
 	std::mutex mutex;
 	{
-		std::lock_guard<std::mutex> machines_lock(machines_mutex_);
+		std::lock_guard<decltype(machines_mutex_)> machines_lock(machines_mutex_);
 		std::lock_guard<std::mutex> lock(mutex);
 		outstanding_machines = machines_.size();
 
@@ -46,29 +46,25 @@ void MultiCRTMachine::perform_parallel(const std::function<void(::CRTMachine::Ma
 }
 
 void MultiCRTMachine::perform_serial(const std::function<void (::CRTMachine::Machine *)> &function) {
-	std::lock_guard<std::mutex> machines_lock(machines_mutex_);
+	std::lock_guard<decltype(machines_mutex_)> machines_lock(machines_mutex_);
 	for(const auto &machine: machines_) {
-		CRTMachine::Machine *crt_machine = machine->crt_machine();
+		CRTMachine::Machine *const crt_machine = machine->crt_machine();
 		if(crt_machine) function(crt_machine);
 	}
 }
 
-void MultiCRTMachine::setup_output(float aspect_ratio) {
-	perform_serial([=](::CRTMachine::Machine *machine) {
-		machine->setup_output(aspect_ratio);
-	});
+void MultiCRTMachine::set_scan_target(Outputs::Display::ScanTarget *scan_target) {
+	scan_target_ = scan_target;
+
+	CRTMachine::Machine *const crt_machine = machines_.front()->crt_machine();
+	if(crt_machine) crt_machine->set_scan_target(scan_target);
 }
 
-void MultiCRTMachine::close_output() {
-	perform_serial([=](::CRTMachine::Machine *machine) {
-		machine->close_output();
-	});
-}
+Outputs::Display::ScanStatus MultiCRTMachine::get_scan_status() const {
+	CRTMachine::Machine *const crt_machine = machines_.front()->crt_machine();
+	if(crt_machine) crt_machine->get_scan_status();
 
-Outputs::CRT::CRT *MultiCRTMachine::get_crt() {
-	std::lock_guard<std::mutex> machines_lock(machines_mutex_);
-	CRTMachine::Machine *crt_machine = machines_.front()->crt_machine();
-	return crt_machine ? crt_machine->get_crt() : nullptr;
+	return Outputs::Display::ScanStatus();
 }
 
 Outputs::Speaker::Speaker *MultiCRTMachine::get_speaker() {
@@ -84,6 +80,14 @@ void MultiCRTMachine::run_for(Time::Seconds duration) {
 }
 
 void MultiCRTMachine::did_change_machine_order() {
+	if(scan_target_) scan_target_->will_change_owner();
+
+	perform_serial([=](::CRTMachine::Machine *machine) {
+		machine->set_scan_target(nullptr);
+	});
+	CRTMachine::Machine *const crt_machine = machines_.front()->crt_machine();
+	if(crt_machine) crt_machine->set_scan_target(scan_target_);
+
 	if(speaker_) {
 		speaker_->set_new_front_machine(machines_.front().get());
 	}

Analyser/Dynamic/MultiMachine/Implementation/MultiCRTMachine.hpp

@@ -31,7 +31,7 @@ namespace Dynamic {
 */
 class MultiCRTMachine: public CRTMachine::Machine {
 	public:
-		MultiCRTMachine(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines, std::mutex &machines_mutex);
+		MultiCRTMachine(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines, std::recursive_mutex &machines_mutex);
 
 		/*!
 			Informs the MultiCRTMachine that the order of machines has changed; the MultiCRTMachine
@@ -53,19 +53,19 @@ class MultiCRTMachine: public CRTMachine::Machine {
 		}
 
 		// Below is the standard CRTMachine::Machine interface; see there for documentation.
-		void setup_output(float aspect_ratio) override;
-		void close_output() override;
-		Outputs::CRT::CRT *get_crt() override;
-		Outputs::Speaker::Speaker *get_speaker() override;
-		void run_for(Time::Seconds duration) override;
+		void set_scan_target(Outputs::Display::ScanTarget *scan_target) final;
+		Outputs::Display::ScanStatus get_scan_status() const final;
+		Outputs::Speaker::Speaker *get_speaker() final;
+		void run_for(Time::Seconds duration) final;
 
 	private:
-		void run_for(const Cycles cycles) override {}
+		void run_for(const Cycles cycles) final {}
 		const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines_;
-		std::mutex &machines_mutex_;
+		std::recursive_mutex &machines_mutex_;
 		std::vector<Concurrency::AsyncTaskQueue> queues_;
 		MultiSpeaker *speaker_ = nullptr;
 		Delegate *delegate_ = nullptr;
+		Outputs::Display::ScanTarget *scan_target_ = nullptr;
 
 		/*!
 			Performs a parallel for operation across all machines, performing the supplied

Analyser/Dynamic/MultiMachine/Implementation/MultiConfigurable.hpp

@@ -28,10 +28,10 @@ class MultiConfigurable: public Configurable::Device {
 		MultiConfigurable(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines);
 
 		// Below is the standard Configurable::Device interface; see there for documentation.
-		std::vector<std::unique_ptr<Configurable::Option>> get_options() override;
-		void set_selections(const Configurable::SelectionSet &selection_by_option) override;
-		Configurable::SelectionSet get_accurate_selections() override;
-		Configurable::SelectionSet get_user_friendly_selections() override;
+		std::vector<std::unique_ptr<Configurable::Option>> get_options() final;
+		void set_selections(const Configurable::SelectionSet &selection_by_option) final;
+		Configurable::SelectionSet get_accurate_selections() final;
+		Configurable::SelectionSet get_user_friendly_selections() final;
 
 	private:
 		std::vector<Configurable::Device *> devices_;

Analyser/Dynamic/MultiMachine/Implementation/MultiConfigurationTarget.cpp

@@ -1,29 +0,0 @@
-//
-//  MultiConfigurationTarget.cpp
-//  Clock Signal
-//
-//  Created by Thomas Harte on 29/01/2018.
-//  Copyright 2018 Thomas Harte. All rights reserved.
-//
-
-#include "MultiConfigurationTarget.hpp"
-
-using namespace Analyser::Dynamic;
-
-MultiConfigurationTarget::MultiConfigurationTarget(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines) {
-	for(const auto &machine: machines) {
-		ConfigurationTarget::Machine *configuration_target = machine->configuration_target();
-		if(configuration_target) targets_.push_back(configuration_target);
-	}
-}
-
-void MultiConfigurationTarget::configure_as_target(const Analyser::Static::Target *target) {
-}
-
-bool MultiConfigurationTarget::insert_media(const Analyser::Static::Media &media) {
-	bool inserted = false;
-	for(const auto &target : targets_) {
-		inserted |= target->insert_media(media);
-	}
-	return inserted;
-}

Analyser/Dynamic/MultiMachine/Implementation/MultiConfigurationTarget.hpp

@@ -1,42 +0,0 @@
-//
-//  MultiConfigurationTarget.hpp
-//  Clock Signal
-//
-//  Created by Thomas Harte on 29/01/2018.
-//  Copyright 2018 Thomas Harte. All rights reserved.
-//
-
-#ifndef MultiConfigurationTarget_hpp
-#define MultiConfigurationTarget_hpp
-
-#include "../../../../Machines/ConfigurationTarget.hpp"
-#include "../../../../Machines/DynamicMachine.hpp"
-
-#include <memory>
-#include <vector>
-
-namespace Analyser {
-namespace Dynamic {
-
-/*!
-	Provides a class that multiplexes the configuration target interface to multiple machines.
-
-	Makes a static internal copy of the list of machines; makes no guarantees about the
-	order of delivered messages.
-*/
-struct MultiConfigurationTarget: public ConfigurationTarget::Machine {
-	public:
-		MultiConfigurationTarget(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines);
-
-		// Below is the standard ConfigurationTarget::Machine interface; see there for documentation.
-		void configure_as_target(const Analyser::Static::Target *target) override;
-		bool insert_media(const Analyser::Static::Media &media) override;
-
-	private:
-		std::vector<ConfigurationTarget::Machine *> targets_;
-};
-
-}
-}
-
-#endif /* MultiConfigurationTarget_hpp */

Analyser/Dynamic/MultiMachine/Implementation/MultiJoystickMachine.cpp

@@ -25,14 +25,14 @@ class MultiJoystick: public Inputs::Joystick {
 			}
 		}
 
-		std::vector<DigitalInput> get_inputs() override {
-			std::vector<DigitalInput> inputs;
-
-			for(const auto &joystick: joysticks_) {
-				std::vector<DigitalInput> joystick_inputs = joystick->get_inputs();
-				for(const auto &input: joystick_inputs) {
-					if(std::find(inputs.begin(), inputs.end(), input) != inputs.end()) {
-						inputs.push_back(input);
+		std::vector<Input> &get_inputs() final {
+			if(inputs.empty()) {
+				for(const auto &joystick: joysticks_) {
+					std::vector<Input> joystick_inputs = joystick->get_inputs();
+					for(const auto &input: joystick_inputs) {
+						if(std::find(inputs.begin(), inputs.end(), input) != inputs.end()) {
+							inputs.push_back(input);
+						}
 					}
 				}
 			}
@@ -40,18 +40,26 @@ class MultiJoystick: public Inputs::Joystick {
 			return inputs;
 		}
 
-		void set_digital_input(const DigitalInput &digital_input, bool is_active) override {
+		void set_input(const Input &digital_input, bool is_active) final {
 			for(const auto &joystick: joysticks_) {
-				joystick->set_digital_input(digital_input, is_active);
+				joystick->set_input(digital_input, is_active);
 			}
 		}
-		void reset_all_inputs() override {
+
+		void set_input(const Input &digital_input, float value) final {
+			for(const auto &joystick: joysticks_) {
+				joystick->set_input(digital_input, value);
+			}
+		}
+
+		void reset_all_inputs() final {
 			for(const auto &joystick: joysticks_) {
 				joystick->reset_all_inputs();
 			}
 		}
 
 	private:
+		std::vector<Input> inputs;
 		std::vector<Inputs::Joystick *> joysticks_;
 };
 
@@ -73,6 +81,6 @@ MultiJoystickMachine::MultiJoystickMachine(const std::vector<std::unique_ptr<::M
 	}
 }
 
-std::vector<std::unique_ptr<Inputs::Joystick>> &MultiJoystickMachine::get_joysticks() {
+const std::vector<std::unique_ptr<Inputs::Joystick>> &MultiJoystickMachine::get_joysticks() {
 	return joysticks_;
 }

Analyser/Dynamic/MultiMachine/Implementation/MultiJoystickMachine.hpp

@@ -28,7 +28,7 @@ class MultiJoystickMachine: public JoystickMachine::Machine {
 		MultiJoystickMachine(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines);
 
 		// Below is the standard JoystickMachine::Machine interface; see there for documentation.
-		std::vector<std::unique_ptr<Inputs::Joystick>> &get_joysticks() override;
+		const std::vector<std::unique_ptr<Inputs::Joystick>> &get_joysticks() final;
 
 	private:
 		std::vector<std::unique_ptr<Inputs::Joystick>> joysticks_;

Analyser/Dynamic/MultiMachine/Implementation/MultiKeyboardMachine.cpp

@@ -10,7 +10,8 @@
 
 using namespace Analyser::Dynamic;
 
-MultiKeyboardMachine::MultiKeyboardMachine(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines) {
+MultiKeyboardMachine::MultiKeyboardMachine(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines) :
+	keyboard_(machines_) {
 	for(const auto &machine: machines) {
 		KeyboardMachine::Machine *keyboard_machine = machine->keyboard_machine();
 		if(keyboard_machine) machines_.push_back(keyboard_machine);
@@ -35,9 +36,34 @@ void MultiKeyboardMachine::type_string(const std::string &string) {
 	}
 }
 
-void MultiKeyboardMachine::keyboard_did_change_key(Inputs::Keyboard *keyboard, Inputs::Keyboard::Key key, bool is_pressed) {
+Inputs::Keyboard &MultiKeyboardMachine::get_keyboard() {
+	return keyboard_;
+}
+
+MultiKeyboardMachine::MultiKeyboard::MultiKeyboard(const std::vector<::KeyboardMachine::Machine *> &machines)
+	: machines_(machines) {
 	for(const auto &machine: machines_) {
-		uint16_t mapped_key = machine->get_keyboard_mapper()->mapped_key_for_key(key);
-		if(mapped_key != KeyNotMapped) machine->set_key_state(mapped_key, is_pressed);
+		observed_keys_.insert(machine->get_keyboard().observed_keys().begin(), machine->get_keyboard().observed_keys().end());
+		is_exclusive_ |= machine->get_keyboard().is_exclusive();
 	}
 }
+
+void MultiKeyboardMachine::MultiKeyboard::set_key_pressed(Key key, char value, bool is_pressed) {
+	for(const auto &machine: machines_) {
+		machine->get_keyboard().set_key_pressed(key, value, is_pressed);
+	}
+}
+
+void MultiKeyboardMachine::MultiKeyboard::reset_all_keys() {
+	for(const auto &machine: machines_) {
+		machine->get_keyboard().reset_all_keys();
+	}
+}
+
+const std::set<Inputs::Keyboard::Key> &MultiKeyboardMachine::MultiKeyboard::observed_keys() {
+	return observed_keys_;
+}
+
+bool MultiKeyboardMachine::MultiKeyboard::is_exclusive() {
+	return is_exclusive_;
+}

Analyser/Dynamic/MultiMachine/Implementation/MultiKeyboardMachine.hpp

@@ -25,17 +25,33 @@ namespace Dynamic {
 	order of delivered messages.
 */
 class MultiKeyboardMachine: public KeyboardMachine::Machine {
+	private:
+		std::vector<::KeyboardMachine::Machine *> machines_;
+
+		class MultiKeyboard: public Inputs::Keyboard {
+			public:
+				MultiKeyboard(const std::vector<::KeyboardMachine::Machine *> &machines);
+
+				void set_key_pressed(Key key, char value, bool is_pressed) final;
+				void reset_all_keys() final;
+				const std::set<Key> &observed_keys() final;
+				bool is_exclusive() final;
+
+			private:
+				const std::vector<::KeyboardMachine::Machine *> &machines_;
+				std::set<Key> observed_keys_;
+				bool is_exclusive_ = false;
+		};
+		MultiKeyboard keyboard_;
+
 	public:
 		MultiKeyboardMachine(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines);
 
 		// Below is the standard KeyboardMachine::Machine interface; see there for documentation.
-		void clear_all_keys() override;
-		void set_key_state(uint16_t key, bool is_pressed) override;
-		void type_string(const std::string &) override;
-		void keyboard_did_change_key(Inputs::Keyboard *keyboard, Inputs::Keyboard::Key key, bool is_pressed) override;
-
-	private:
-		std::vector<::KeyboardMachine::Machine *> machines_;
+		void clear_all_keys() final;
+		void set_key_state(uint16_t key, bool is_pressed) final;
+		void type_string(const std::string &) final;
+		Inputs::Keyboard &get_keyboard() final;
 };
 
 }

Analyser/Dynamic/MultiMachine/Implementation/MultiMediaTarget.cpp

@@ -0,0 +1,26 @@
+//
+//  MultiMediaTarget.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 29/01/2018.
+//  Copyright 2018 Thomas Harte. All rights reserved.
+//
+
+#include "MultiMediaTarget.hpp"
+
+using namespace Analyser::Dynamic;
+
+MultiMediaTarget::MultiMediaTarget(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines) {
+	for(const auto &machine: machines) {
+		MediaTarget::Machine *media_target = machine->media_target();
+		if(media_target) targets_.push_back(media_target);
+	}
+}
+
+bool MultiMediaTarget::insert_media(const Analyser::Static::Media &media) {
+	bool inserted = false;
+	for(const auto &target : targets_) {
+		inserted |= target->insert_media(media);
+	}
+	return inserted;
+}

Analyser/Dynamic/MultiMachine/Implementation/MultiMediaTarget.hpp

@@ -0,0 +1,41 @@
+//
+//  MultiMediaTarget.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 29/01/2018.
+//  Copyright 2018 Thomas Harte. All rights reserved.
+//
+
+#ifndef MultiMediaTarget_hpp
+#define MultiMediaTarget_hpp
+
+#include "../../../../Machines/MediaTarget.hpp"
+#include "../../../../Machines/DynamicMachine.hpp"
+
+#include <memory>
+#include <vector>
+
+namespace Analyser {
+namespace Dynamic {
+
+/*!
+	Provides a class that multiplexes the media target interface to multiple machines.
+
+	Makes a static internal copy of the list of machines; makes no guarantees about the
+	order of delivered messages.
+*/
+struct MultiMediaTarget: public MediaTarget::Machine {
+	public:
+		MultiMediaTarget(const std::vector<std::unique_ptr<::Machine::DynamicMachine>> &machines);
+
+		// Below is the standard MediaTarget::Machine interface; see there for documentation.
+		bool insert_media(const Analyser::Static::Media &media) final;
+
+	private:
+		std::vector<MediaTarget::Machine *> targets_;
+};
+
+}
+}
+
+#endif /* MultiMediaTarget_hpp */

Analyser/Dynamic/MultiMachine/Implementation/MultiSpeaker.cpp

@@ -37,9 +37,9 @@ float MultiSpeaker::get_ideal_clock_rate_in_range(float minimum, float maximum)
 	return ideal / static_cast<float>(speakers_.size());
 }
 
-void MultiSpeaker::set_output_rate(float cycles_per_second, int buffer_size) {
+void MultiSpeaker::set_computed_output_rate(float cycles_per_second, int buffer_size) {
 	for(const auto &speaker: speakers_) {
-		speaker->set_output_rate(cycles_per_second, buffer_size);
+		speaker->set_computed_output_rate(cycles_per_second, buffer_size);
 	}
 }
 
@@ -53,7 +53,7 @@ void MultiSpeaker::speaker_did_complete_samples(Speaker *speaker, const std::vec
 		std::lock_guard<std::mutex> lock_guard(front_speaker_mutex_);
 		if(speaker != front_speaker_) return;
 	}
-	delegate_->speaker_did_complete_samples(this, buffer);
+	did_complete_samples(this, buffer);
 }
 
 void MultiSpeaker::speaker_did_change_input_clock(Speaker *speaker) {

Analyser/Dynamic/MultiMachine/Implementation/MultiSpeaker.hpp

@@ -39,12 +39,12 @@ class MultiSpeaker: public Outputs::Speaker::Speaker, Outputs::Speaker::Speaker:
 
 		// Below is the standard Outputs::Speaker::Speaker interface; see there for documentation.
 		float get_ideal_clock_rate_in_range(float minimum, float maximum) override;
-		void set_output_rate(float cycles_per_second, int buffer_size) override;
+		void set_computed_output_rate(float cycles_per_second, int buffer_size) override;
 		void set_delegate(Outputs::Speaker::Speaker::Delegate *delegate) override;
 
 	private:
-		void speaker_did_complete_samples(Speaker *speaker, const std::vector<int16_t> &buffer) override;
-		void speaker_did_change_input_clock(Speaker *speaker) override;
+		void speaker_did_complete_samples(Speaker *speaker, const std::vector<int16_t> &buffer) final;
+		void speaker_did_change_input_clock(Speaker *speaker) final;
 		MultiSpeaker(const std::vector<Outputs::Speaker::Speaker *> &speakers);
 
 		std::vector<Outputs::Speaker::Speaker *> speakers_;

Analyser/Dynamic/MultiMachine/MultiMachine.cpp

@@ -7,6 +7,7 @@
 //
 
 #include "MultiMachine.hpp"
+#include "../../../Outputs/Log.hpp"
 
 #include <algorithm>
 
@@ -15,10 +16,10 @@ using namespace Analyser::Dynamic;
 MultiMachine::MultiMachine(std::vector<std::unique_ptr<DynamicMachine>> &&machines) :
 	machines_(std::move(machines)),
 	configurable_(machines_),
-	configuration_target_(machines_),
 	crt_machine_(machines_, machines_mutex_),
 	joystick_machine_(machines),
-	keyboard_machine_(machines_) {
+	keyboard_machine_(machines_),
+	media_target_(machines_) {
 	crt_machine_.set_delegate(this);
 }
 
@@ -26,11 +27,11 @@ Activity::Source *MultiMachine::activity_source() {
 	return nullptr; // TODO
 }
 
-ConfigurationTarget::Machine *MultiMachine::configuration_target() {
+MediaTarget::Machine *MultiMachine::media_target() {
 	if(has_picked_) {
-		return machines_.front()->configuration_target();
+		return machines_.front()->media_target();
 	} else {
-		return &configuration_target_;
+		return &media_target_;
 	}
 }
 
@@ -58,6 +59,11 @@ KeyboardMachine::Machine *MultiMachine::keyboard_machine() {
 	}
 }
 
+MouseMachine::Machine *MultiMachine::mouse_machine() {
+	// TODO.
+	return nullptr;
+}
+
 Configurable::Device *MultiMachine::configurable_device() {
 	if(has_picked_) {
 		return machines_.front()->configurable_device();
@@ -73,15 +79,13 @@ bool MultiMachine::would_collapse(const std::vector<std::unique_ptr<DynamicMachi
 }
 
 void MultiMachine::multi_crt_did_run_machines() {
-	std::lock_guard<std::mutex> machines_lock(machines_mutex_);
-#ifdef DEBUG
+	std::lock_guard<decltype(machines_mutex_)> machines_lock(machines_mutex_);
+#ifndef NDEBUG
 	for(const auto &machine: machines_) {
 		CRTMachine::Machine *crt = machine->crt_machine();
-		printf("%0.2f ", crt->get_confidence());
-		crt->print_type();
-		printf("; ");
+		LOGNBR(PADHEX(2) << crt->get_confidence() << " " << crt->debug_type() << "; ");
 	}
-	printf("\n");
+	LOGNBR(std::endl);
 #endif
 
 	DynamicMachine *front = machines_.front().get();

Analyser/Dynamic/MultiMachine/MultiMachine.hpp

@@ -12,10 +12,10 @@
 #include "../../../Machines/DynamicMachine.hpp"
 
 #include "Implementation/MultiConfigurable.hpp"
-#include "Implementation/MultiConfigurationTarget.hpp"
 #include "Implementation/MultiCRTMachine.hpp"
 #include "Implementation/MultiJoystickMachine.hpp"
 #include "Implementation/MultiKeyboardMachine.hpp"
+#include "Implementation/MultiMediaTarget.hpp"
 
 #include <memory>
 #include <mutex>
@@ -50,25 +50,26 @@ class MultiMachine: public ::Machine::DynamicMachine, public MultiCRTMachine::De
 		static bool would_collapse(const std::vector<std::unique_ptr<DynamicMachine>> &machines);
 		MultiMachine(std::vector<std::unique_ptr<DynamicMachine>> &&machines);
 
-		Activity::Source *activity_source() override;
-		ConfigurationTarget::Machine *configuration_target() override;
-		CRTMachine::Machine *crt_machine() override;
-		JoystickMachine::Machine *joystick_machine() override;
-		KeyboardMachine::Machine *keyboard_machine() override;
-		Configurable::Device *configurable_device() override;
-		void *raw_pointer() override;
+		Activity::Source *activity_source() final;
+		Configurable::Device *configurable_device() final;
+		CRTMachine::Machine *crt_machine() final;
+		JoystickMachine::Machine *joystick_machine() final;
+		MouseMachine::Machine *mouse_machine() final;
+		KeyboardMachine::Machine *keyboard_machine() final;
+		MediaTarget::Machine *media_target() final;
+		void *raw_pointer() final;
 
 	private:
-		void multi_crt_did_run_machines() override;
+		void multi_crt_did_run_machines() final;
 
 		std::vector<std::unique_ptr<DynamicMachine>> machines_;
-		std::mutex machines_mutex_;
+		std::recursive_mutex machines_mutex_;
 
 		MultiConfigurable configurable_;
-		MultiConfigurationTarget configuration_target_;
 		MultiCRTMachine crt_machine_;
 		MultiJoystickMachine joystick_machine_;
 		MultiKeyboardMachine keyboard_machine_;
+		MultiMediaTarget media_target_;
 
 		void pick_first();
 		bool has_picked_ = false;

Analyser/Machines.hpp

@@ -15,8 +15,11 @@ enum class Machine {
 	AmstradCPC,
 	AppleII,
 	Atari2600,
+	AtariST,
 	ColecoVision,
 	Electron,
+	Macintosh,
+	MasterSystem,
 	MSX,
 	Oric,
 	Vic20,

Analyser/Static/Acorn/Disk.cpp

@@ -10,7 +10,7 @@
 
 #include "../../../Storage/Disk/Controller/DiskController.hpp"
 #include "../../../Storage/Disk/Encodings/MFM/Parser.hpp"
-#include "../../../NumberTheory/CRC.hpp"
+#include "../../../Numeric/CRC.hpp"
 
 #include <algorithm>
 
@@ -18,7 +18,7 @@ using namespace Analyser::Static::Acorn;
 
 std::unique_ptr<Catalogue> Analyser::Static::Acorn::GetDFSCatalogue(const std::shared_ptr<Storage::Disk::Disk> &disk) {
 	// c.f. http://beebwiki.mdfs.net/Acorn_DFS_disc_format
-	std::unique_ptr<Catalogue> catalogue(new Catalogue);
+	auto catalogue = std::make_unique<Catalogue>();
 	Storage::Encodings::MFM::Parser parser(false, disk);
 
 	Storage::Encodings::MFM::Sector *names = parser.get_sector(0, 0, 0);
@@ -75,7 +75,7 @@ std::unique_ptr<Catalogue> Analyser::Static::Acorn::GetDFSCatalogue(const std::s
 	return catalogue;
 }
 std::unique_ptr<Catalogue> Analyser::Static::Acorn::GetADFSCatalogue(const std::shared_ptr<Storage::Disk::Disk> &disk) {
-	std::unique_ptr<Catalogue> catalogue(new Catalogue);
+	auto catalogue = std::make_unique<Catalogue>();
 	Storage::Encodings::MFM::Parser parser(true, disk);
 
 	Storage::Encodings::MFM::Sector *free_space_map_second_half = parser.get_sector(0, 0, 1);

Analyser/Static/Acorn/StaticAnalyser.cpp

@@ -58,7 +58,7 @@ static std::vector<std::shared_ptr<Storage::Cartridge::Cartridge>>
 }
 
 Analyser::Static::TargetList Analyser::Static::Acorn::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
-	std::unique_ptr<Target> target(new Target);
+	auto target = std::make_unique<Target>();
 	target->machine = Machine::Electron;
 	target->confidence = 0.5; // TODO: a proper estimation
 	target->has_dfs = false;
@@ -69,13 +69,13 @@ Analyser::Static::TargetList Analyser::Static::Acorn::GetTargets(const Media &me
 	target->media.cartridges = AcornCartridgesFrom(media.cartridges);
 
 	// if there are any tapes, attempt to get data from the first
-	if(media.tapes.size() > 0) {
+	if(!media.tapes.empty()) {
 		std::shared_ptr<Storage::Tape::Tape> tape = media.tapes.front();
 		std::vector<File> files = GetFiles(tape);
 		tape->reset();
 
 		// continue if there are any files
-		if(files.size()) {
+		if(!files.empty()) {
 			bool is_basic = true;
 
 			// protected files are always for *RUNning only
@@ -103,7 +103,7 @@ Analyser::Static::TargetList Analyser::Static::Acorn::GetTargets(const Media &me
 		}
 	}
 
-	if(media.disks.size() > 0) {
+	if(!media.disks.empty()) {
 		std::shared_ptr<Storage::Disk::Disk> disk = media.disks.front();
 		std::unique_ptr<Catalogue> dfs_catalogue, adfs_catalogue;
 		dfs_catalogue = GetDFSCatalogue(disk);

Analyser/Static/Acorn/Tape.cpp

@@ -10,13 +10,13 @@
 
 #include <deque>
 
-#include "../../../NumberTheory/CRC.hpp"
+#include "../../../Numeric/CRC.hpp"
 #include "../../../Storage/Tape/Parsers/Acorn.hpp"
 
 using namespace Analyser::Static::Acorn;
 
 static std::unique_ptr<File::Chunk> GetNextChunk(const std::shared_ptr<Storage::Tape::Tape> &tape, Storage::Tape::Acorn::Parser &parser) {
-	std::unique_ptr<File::Chunk> new_chunk(new File::Chunk);
+	auto new_chunk = std::make_unique<File::Chunk>();
 	int shift_register = 0;
 
 // TODO: move this into the parser
@@ -90,7 +90,7 @@ static std::unique_ptr<File> GetNextFile(std::deque<File::Chunk> &chunks) {
 	if(!chunks.size()) return nullptr;
 
 	// accumulate chunks for as long as block number is sequential and the end-of-file bit isn't set
-	std::unique_ptr<File> file(new File);
+	auto file = std::make_unique<File>();
 
 	uint16_t block_number = 0;
 

Analyser/Static/AmstradCPC/StaticAnalyser.cpp

@@ -181,7 +181,7 @@ static bool CheckBootSector(const std::shared_ptr<Storage::Disk::Disk> &disk, co
 
 Analyser::Static::TargetList Analyser::Static::AmstradCPC::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
 	TargetList destination;
-	std::unique_ptr<Target> target(new Target);
+	auto target = std::make_unique<Target>();
 	target->machine = Machine::AmstradCPC;
 	target->confidence = 0.5;
 

Analyser/Static/AppleII/StaticAnalyser.cpp

@@ -10,7 +10,7 @@
 #include "Target.hpp"
 
 Analyser::Static::TargetList Analyser::Static::AppleII::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
-	auto target = std::unique_ptr<Target>(new Target);
+	auto target = std::make_unique<Target>();
 	target->machine = Machine::AppleII;
 	target->media = media;
 

Analyser/Static/AppleII/Target.hpp

@@ -18,7 +18,9 @@ namespace AppleII {
 struct Target: public ::Analyser::Static::Target {
 	enum class Model {
 		II,
-		IIplus
+		IIplus,
+		IIe,
+		EnhancedIIe
 	};
 	enum class DiskController {
 		None,
@@ -26,7 +28,7 @@ struct Target: public ::Analyser::Static::Target {
 		ThirteenSector
 	};
 
-	Model model = Model::IIplus;
+	Model model = Model::IIe;
 	DiskController disk_controller = DiskController::None;
 };
 

Analyser/Static/Atari2600/StaticAnalyser.cpp

@@ -12,9 +12,10 @@
 
 #include "../Disassembler/6502.hpp"
 
-using namespace Analyser::Static::Atari;
+using namespace Analyser::Static::Atari2600;
+using Target = Analyser::Static::Atari2600::Target;
 
-static void DeterminePagingFor2kCartridge(Analyser::Static::Atari::Target &target, const Storage::Cartridge::Cartridge::Segment &segment) {
+static void DeterminePagingFor2kCartridge(Target &target, const Storage::Cartridge::Cartridge::Segment &segment) {
 	// if this is a 2kb cartridge then it's definitely either unpaged or a CommaVid
 	uint16_t entry_address, break_address;
 
@@ -48,10 +49,10 @@ static void DeterminePagingFor2kCartridge(Analyser::Static::Atari::Target &targe
 	// caveat: false positives aren't likely to be problematic; a false positive is a 2KB ROM that always addresses
 	// itself so as to land in ROM even if mapped as a CommaVid and this code is on the fence as to whether it
 	// attempts to modify itself but it probably doesn't
-	if(has_wide_area_store) target.paging_model = Analyser::Static::Atari::Target::PagingModel::CommaVid;
+	if(has_wide_area_store) target.paging_model = Target::PagingModel::CommaVid;
 }
 
-static void DeterminePagingFor8kCartridge(Analyser::Static::Atari::Target &target, const Storage::Cartridge::Cartridge::Segment &segment, const Analyser::Static::MOS6502::Disassembly &disassembly) {
+static void DeterminePagingFor8kCartridge(Target &target, const Storage::Cartridge::Cartridge::Segment &segment, const Analyser::Static::MOS6502::Disassembly &disassembly) {
 	// Activision stack titles have their vectors at the top of the low 4k, not the top, and
 	// always list 0xf000 as both vectors; they do not repeat them, and, inexplicably, they all
 	// issue an SEI as their first instruction (maybe some sort of relic of the development environment?)
@@ -60,12 +61,12 @@ static void DeterminePagingFor8kCartridge(Analyser::Static::Atari::Target &targe
 		(segment.data[8191] != 0xf0 || segment.data[8189] != 0xf0 || segment.data[8190] != 0x00 || segment.data[8188] != 0x00) &&
 		segment.data[0] == 0x78
 	) {
-		target.paging_model = Analyser::Static::Atari::Target::PagingModel::ActivisionStack;
+		target.paging_model = Target::PagingModel::ActivisionStack;
 		return;
 	}
 
 	// make an assumption that this is the Atari paging model
-	target.paging_model = Analyser::Static::Atari::Target::PagingModel::Atari8k;
+	target.paging_model = Target::PagingModel::Atari8k;
 
 	std::set<uint16_t> internal_accesses;
 	internal_accesses.insert(disassembly.internal_stores.begin(), disassembly.internal_stores.end());
@@ -85,13 +86,13 @@ static void DeterminePagingFor8kCartridge(Analyser::Static::Atari::Target &targe
 		tigervision_access_count += masked_address == 0x3f;
 	}
 
-	if(parker_access_count > atari_access_count) target.paging_model = Analyser::Static::Atari::Target::PagingModel::ParkerBros;
-	else if(tigervision_access_count > atari_access_count) target.paging_model = Analyser::Static::Atari::Target::PagingModel::Tigervision;
+	if(parker_access_count > atari_access_count) target.paging_model = Target::PagingModel::ParkerBros;
+	else if(tigervision_access_count > atari_access_count) target.paging_model = Target::PagingModel::Tigervision;
 }
 
-static void DeterminePagingFor16kCartridge(Analyser::Static::Atari::Target &target, const Storage::Cartridge::Cartridge::Segment &segment, const Analyser::Static::MOS6502::Disassembly &disassembly) {
+static void DeterminePagingFor16kCartridge(Target &target, const Storage::Cartridge::Cartridge::Segment &segment, const Analyser::Static::MOS6502::Disassembly &disassembly) {
 	// make an assumption that this is the Atari paging model
-	target.paging_model = Analyser::Static::Atari::Target::PagingModel::Atari16k;
+	target.paging_model = Target::PagingModel::Atari16k;
 
 	std::set<uint16_t> internal_accesses;
 	internal_accesses.insert(disassembly.internal_stores.begin(), disassembly.internal_stores.end());
@@ -106,17 +107,17 @@ static void DeterminePagingFor16kCartridge(Analyser::Static::Atari::Target &targ
 		mnetwork_access_count += masked_address >= 0x1fe0 && masked_address < 0x1ffb;
 	}
 
-	if(mnetwork_access_count > atari_access_count) target.paging_model = Analyser::Static::Atari::Target::PagingModel::MNetwork;
+	if(mnetwork_access_count > atari_access_count) target.paging_model = Target::PagingModel::MNetwork;
 }
 
-static void DeterminePagingFor64kCartridge(Analyser::Static::Atari::Target &target, const Storage::Cartridge::Cartridge::Segment &segment, const Analyser::Static::MOS6502::Disassembly &disassembly) {
+static void DeterminePagingFor64kCartridge(Target &target, const Storage::Cartridge::Cartridge::Segment &segment, const Analyser::Static::MOS6502::Disassembly &disassembly) {
 	// make an assumption that this is a Tigervision if there is a write to 3F
 	target.paging_model =
 		(disassembly.external_stores.find(0x3f) != disassembly.external_stores.end()) ?
-			Analyser::Static::Atari::Target::PagingModel::Tigervision : Analyser::Static::Atari::Target::PagingModel::MegaBoy;
+			Target::PagingModel::Tigervision : Target::PagingModel::MegaBoy;
 }
 
-static void DeterminePagingForCartridge(Analyser::Static::Atari::Target &target, const Storage::Cartridge::Cartridge::Segment &segment) {
+static void DeterminePagingForCartridge(Target &target, const Storage::Cartridge::Cartridge::Segment &segment) {
 	if(segment.data.size() == 2048) {
 		DeterminePagingFor2kCartridge(target, segment);
 		return;
@@ -140,16 +141,16 @@ static void DeterminePagingForCartridge(Analyser::Static::Atari::Target &target,
 			DeterminePagingFor8kCartridge(target, segment, disassembly);
 		break;
 		case 10495:
-			target.paging_model = Analyser::Static::Atari::Target::PagingModel::Pitfall2;
+			target.paging_model = Target::PagingModel::Pitfall2;
 		break;
 		case 12288:
-			target.paging_model = Analyser::Static::Atari::Target::PagingModel::CBSRamPlus;
+			target.paging_model = Target::PagingModel::CBSRamPlus;
 		break;
 		case 16384:
 			DeterminePagingFor16kCartridge(target, segment, disassembly);
 		break;
 		case 32768:
-			target.paging_model = Analyser::Static::Atari::Target::PagingModel::Atari32k;
+			target.paging_model = Target::PagingModel::Atari32k;
 		break;
 		case 65536:
 			DeterminePagingFor64kCartridge(target, segment, disassembly);
@@ -161,8 +162,8 @@ static void DeterminePagingForCartridge(Analyser::Static::Atari::Target &target,
 	// check for a Super Chip. Atari ROM images [almost] always have the same value stored over RAM
 	// regions; when they don't they at least seem to have the first 128 bytes be the same as the
 	// next 128 bytes. So check for that.
-	if(	target.paging_model != Analyser::Static::Atari::Target::PagingModel::CBSRamPlus &&
-		target.paging_model != Analyser::Static::Atari::Target::PagingModel::MNetwork) {
+	if(	target.paging_model != Target::PagingModel::CBSRamPlus &&
+		target.paging_model != Target::PagingModel::MNetwork) {
 		bool has_superchip = true;
 		for(std::size_t address = 0; address < 128; address++) {
 			if(segment.data[address] != segment.data[address+128]) {
@@ -174,19 +175,19 @@ static void DeterminePagingForCartridge(Analyser::Static::Atari::Target &target,
 	}
 
 	// check for a Tigervision or Tigervision-esque scheme
-	if(target.paging_model == Analyser::Static::Atari::Target::PagingModel::None && segment.data.size() > 4096) {
+	if(target.paging_model == Target::PagingModel::None && segment.data.size() > 4096) {
 		bool looks_like_tigervision = disassembly.external_stores.find(0x3f) != disassembly.external_stores.end();
-		if(looks_like_tigervision) target.paging_model = Analyser::Static::Atari::Target::PagingModel::Tigervision;
+		if(looks_like_tigervision) target.paging_model = Target::PagingModel::Tigervision;
 	}
 }
 
-Analyser::Static::TargetList Analyser::Static::Atari::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
+Analyser::Static::TargetList Analyser::Static::Atari2600::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
 	// TODO: sanity checking; is this image really for an Atari 2600?
-	std::unique_ptr<Analyser::Static::Atari::Target> target(new Analyser::Static::Atari::Target);
+	auto target = std::make_unique<Target>();
 	target->machine = Machine::Atari2600;
 	target->confidence = 0.5;
 	target->media.cartridges = media.cartridges;
-	target->paging_model = Analyser::Static::Atari::Target::PagingModel::None;
+	target->paging_model = Target::PagingModel::None;
 	target->uses_superchip = false;
 
 	// try to figure out the paging scheme

Analyser/Static/Atari2600/StaticAnalyser.hpp

@@ -15,7 +15,7 @@
 
 namespace Analyser {
 namespace Static {
-namespace Atari {
+namespace Atari2600 {
 
 TargetList GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms);
 

Analyser/Static/Atari2600/Target.hpp

@@ -6,14 +6,14 @@
 //  Copyright 2018 Thomas Harte. All rights reserved.
 //
 
-#ifndef Analyser_Static_Atari_Target_h
-#define Analyser_Static_Atari_Target_h
+#ifndef Analyser_Static_Atari2600_Target_h
+#define Analyser_Static_Atari2600_Target_h
 
 #include "../StaticAnalyser.hpp"
 
 namespace Analyser {
 namespace Static {
-namespace Atari {
+namespace Atari2600 {
 
 struct Target: public ::Analyser::Static::Target {
 	enum class PagingModel {

Analyser/Static/AtariST/StaticAnalyser.cpp

@@ -0,0 +1,26 @@
+//
+//  StaticAnalyser.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 03/10/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#include "StaticAnalyser.hpp"
+#include "Target.hpp"
+
+Analyser::Static::TargetList Analyser::Static::AtariST::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
+	// This analyser can comprehend disks and mass-storage devices only.
+	if(media.disks.empty()) return {};
+
+	// As there is at least one usable media image, wave it through.
+	Analyser::Static::TargetList targets;
+
+	using Target = Analyser::Static::Target;
+	auto *target = new Target;
+	target->machine = Analyser::Machine::AtariST;
+	target->media = media;
+	targets.push_back(std::unique_ptr<Analyser::Static::Target>(target));
+
+	return targets;
+}

Analyser/Static/AtariST/StaticAnalyser.hpp

@@ -0,0 +1,27 @@
+//
+//  StaticAnalyser.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 03/10/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef Analyser_Static_AtariST_StaticAnalyser_hpp
+#define Analyser_Static_AtariST_StaticAnalyser_hpp
+
+#include "../StaticAnalyser.hpp"
+#include "../../../Storage/TargetPlatforms.hpp"
+#include <string>
+
+namespace Analyser {
+namespace Static {
+namespace AtariST {
+
+TargetList GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms);
+
+}
+}
+}
+
+
+#endif /* Analyser_Static_AtariST_StaticAnalyser_hpp */

Analyser/Static/AtariST/Target.hpp

@@ -0,0 +1,23 @@
+//
+//  Target.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 03/06/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef Analyser_Static_AtariST_Target_h
+#define Analyser_Static_AtariST_Target_h
+
+namespace Analyser {
+namespace Static {
+namespace AtariST {
+
+struct Target: public ::Analyser::Static::Target {
+};
+
+}
+}
+}
+
+#endif /* Analyser_Static_AtariST_Target_h */

Analyser/Static/Coleco/StaticAnalyser.cpp

@@ -17,13 +17,8 @@ static std::vector<std::shared_ptr<Storage::Cartridge::Cartridge>>
 
 		// only one mapped item is allowed
 		if(segments.size() != 1) continue;
-
-		// which must be 8, 12, 16, 24 or 32 kb in size
 		const Storage::Cartridge::Cartridge::Segment &segment = segments.front();
 		const std::size_t data_size = segment.data.size();
-		const std::size_t overflow = data_size&8191;
-		if(overflow > 8 && overflow != 512 && (data_size != 12*1024)) continue;
-		if(data_size < 8192) continue;
 
 		// the two bytes that will be first must be 0xaa and 0x55, either way around
 		auto *start = &segment.data[0];
@@ -34,19 +29,24 @@ static std::vector<std::shared_ptr<Storage::Cartridge::Cartridge>>
 		if(start[0] == start[1]) continue;
 
 		// probability of a random binary blob that isn't a Coleco ROM proceeding to here is 1 - 1/32768.
-		if(!overflow) {
-			coleco_cartridges.push_back(cartridge);
+
+		// Round up to the next multiple of 8kb if this image is less than 32kb. Otherwise round down if
+		// this image is within a short distance of 32kb.
+		std::vector<Storage::Cartridge::Cartridge::Segment> output_segments;
+
+		size_t target_size;
+		if(data_size >= 32*1024 && data_size < 32*1024 + 512) {
+			target_size = 32 * 1024;
 		} else {
-			// Size down to a multiple of 8kb and apply the start address.
-			std::vector<Storage::Cartridge::Cartridge::Segment> output_segments;
-
-			std::vector<uint8_t> truncated_data;
-			std::vector<uint8_t>::difference_type truncated_size = static_cast<std::vector<uint8_t>::difference_type>(segment.data.size()) & ~8191;
-			truncated_data.insert(truncated_data.begin(), segment.data.begin(), segment.data.begin() + truncated_size);
-			output_segments.emplace_back(0x8000, truncated_data);
-
-			coleco_cartridges.emplace_back(new Storage::Cartridge::Cartridge(output_segments));
+			target_size = data_size + ((8192 - (data_size & 8191)) & 8191);
 		}
+
+		std::vector<uint8_t> truncated_data;
+		truncated_data = segment.data;
+		truncated_data.resize(target_size);
+		output_segments.emplace_back(0x8000, truncated_data);
+
+		coleco_cartridges.emplace_back(new Storage::Cartridge::Cartridge(output_segments));
 	}
 
 	return coleco_cartridges;
@@ -54,7 +54,7 @@ static std::vector<std::shared_ptr<Storage::Cartridge::Cartridge>>
 
 Analyser::Static::TargetList Analyser::Static::Coleco::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
 	TargetList targets;
-	std::unique_ptr<Target> target(new Target);
+	auto target = std::make_unique<Target>();
 	target->machine = Machine::ColecoVision;
 	target->confidence = 1.0f - 1.0f / 32768.0f;
 	target->media.cartridges = ColecoCartridgesFrom(media.cartridges);

Analyser/Static/Coleco/StaticAnalyser.hpp

@@ -23,5 +23,4 @@ TargetList GetTargets(const Media &media, const std::string &file_name, TargetPl
 }
 }
 
-
 #endif /* StaticAnalyser_hpp */

Analyser/Static/Commodore/Disk.cpp

@@ -19,12 +19,10 @@ using namespace Analyser::Static::Commodore;
 
 class CommodoreGCRParser: public Storage::Disk::Controller {
 	public:
-		std::shared_ptr<Storage::Disk::Drive> drive;
-
 		CommodoreGCRParser() : Storage::Disk::Controller(4000000), shift_register_(0), track_(1) {
-			drive.reset(new Storage::Disk::Drive(4000000, 300, 2));
-			set_drive(drive);
-			drive->set_motor_on(true);
+			emplace_drive(4000000, 300, 2);
+			set_drive(1);
+			get_drive().set_motor_on(true);
 		}
 
 		struct Sector {
@@ -61,6 +59,10 @@ class CommodoreGCRParser: public Storage::Disk::Controller {
 			return get_sector(sector);
 		}
 
+		void set_disk(const std::shared_ptr<Storage::Disk::Disk> &disk) {
+			get_drive().set_disk(disk);
+		}
+
 	private:
 		unsigned int shift_register_;
 		int index_count_;
@@ -125,7 +127,7 @@ class CommodoreGCRParser: public Storage::Disk::Controller {
 		}
 
 		std::shared_ptr<Sector> get_next_sector() {
-			std::shared_ptr<Sector> sector(new Sector);
+			auto sector = std::make_shared<Sector>();
 			const int max_index_count = index_count_ + 2;
 
 			while(index_count_ < max_index_count) {
@@ -170,7 +172,7 @@ class CommodoreGCRParser: public Storage::Disk::Controller {
 std::vector<File> Analyser::Static::Commodore::GetFiles(const std::shared_ptr<Storage::Disk::Disk> &disk) {
 	std::vector<File> files;
 	CommodoreGCRParser parser;
-	parser.drive->set_disk(disk);
+	parser.set_disk(disk);
 
 	// find any sector whatsoever to establish the current track
 	std::shared_ptr<CommodoreGCRParser::Sector> sector;

Analyser/Static/Commodore/StaticAnalyser.cpp

@@ -13,8 +13,10 @@
 #include "Tape.hpp"
 #include "Target.hpp"
 #include "../../../Storage/Cartridge/Encodings/CommodoreROM.hpp"
+#include "../../../Outputs/Log.hpp"
 
 #include <algorithm>
+#include <cstring>
 #include <sstream>
 
 using namespace Analyser::Static::Commodore;
@@ -43,7 +45,7 @@ static std::vector<std::shared_ptr<Storage::Cartridge::Cartridge>>
 Analyser::Static::TargetList Analyser::Static::Commodore::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
 	TargetList destination;
 
-	std::unique_ptr<Target> target(new Target);
+	auto target = std::make_unique<Target>();
 	target->machine = Machine::Vic20;	// TODO: machine estimation
 	target->confidence = 0.5; // TODO: a proper estimation
 
@@ -77,10 +79,10 @@ Analyser::Static::TargetList Analyser::Static::Commodore::GetTargets(const Media
 	}
 
 	if(!files.empty()) {
-		target->memory_model = Target::MemoryModel::Unexpanded;
+		auto memory_model = Target::MemoryModel::Unexpanded;
 		std::ostringstream string_stream;
 		string_stream << "LOAD\"" << (is_disk ? "*" : "") << "\"," << device << ",";
-  		if(files.front().is_basic()) {
+		if(files.front().is_basic()) {
 			string_stream << "0";
 		} else {
 			string_stream << "1";
@@ -91,18 +93,20 @@ Analyser::Static::TargetList Analyser::Static::Commodore::GetTargets(const Media
 		// make a first guess based on loading address
 		switch(files.front().starting_address) {
 			default:
-				printf("Starting address %04x?\n", files.front().starting_address);
+				LOG("Unrecognised loading address for Commodore program: " << PADHEX(4) <<  files.front().starting_address);
 			case 0x1001:
-				target->memory_model = Target::MemoryModel::Unexpanded;
+				memory_model = Target::MemoryModel::Unexpanded;
 			break;
 			case 0x1201:
-				target->memory_model = Target::MemoryModel::ThirtyTwoKB;
+				memory_model = Target::MemoryModel::ThirtyTwoKB;
 			break;
 			case 0x0401:
-				target->memory_model = Target::MemoryModel::EightKB;
+				memory_model = Target::MemoryModel::EightKB;
 			break;
 		}
 
+		target->set_memory_model(memory_model);
+
 		// General approach: increase memory size conservatively such that the largest file found will fit.
 //		for(File &file : files) {
 //			std::size_t file_size = file.data.size();
@@ -144,13 +148,52 @@ Analyser::Static::TargetList Analyser::Static::Commodore::GetTargets(const Media
 	}
 
 	if(!target->media.empty()) {
-		// Inspect filename for a region hint.
+		// Inspect filename for configuration hints.
 		std::string lowercase_name = file_name;
 		std::transform(lowercase_name.begin(), lowercase_name.end(), lowercase_name.begin(), ::tolower);
+
+		// Hint 1: 'ntsc' anywhere in the name implies America.
 		if(lowercase_name.find("ntsc") != std::string::npos) {
 			target->region = Analyser::Static::Commodore::Target::Region::American;
 		}
 
+		// Potential additional hints: check for TheC64 tags.
+		auto final_underscore = lowercase_name.find_last_of('_');
+		if(final_underscore != std::string::npos) {
+			auto iterator = lowercase_name.begin() + ssize_t(final_underscore) + 1;
+
+			while(iterator != lowercase_name.end()) {
+				// Grab the next tag.
+				char next_tag[3] = {0, 0, 0};
+				next_tag[0] = *iterator++;
+				if(iterator == lowercase_name.end()) break;
+				next_tag[1] = *iterator++;
+
+				// Exit early if attempting to read another tag has run over the file extension.
+				if(next_tag[0] == '.' || next_tag[1] == '.') break;
+
+				// Check whether it's anything.
+				target->enabled_ram.bank0 |= !strcmp(next_tag, "b0");
+				target->enabled_ram.bank1 |= !strcmp(next_tag, "b1");
+				target->enabled_ram.bank2 |= !strcmp(next_tag, "b2");
+				target->enabled_ram.bank3 |= !strcmp(next_tag, "b3");
+				target->enabled_ram.bank5 |= !strcmp(next_tag, "b5");
+				if(!strcmp(next_tag, "tn")) {	// i.e. NTSC.
+					target->region = Analyser::Static::Commodore::Target::Region::American;
+				}
+				if(!strcmp(next_tag, "tp")) {	// i.e. PAL.
+					target->region = Analyser::Static::Commodore::Target::Region::European;
+				}
+
+				// Unhandled:
+				//
+				//	M6: 	this is a C64 file.
+				//	MV: 	this is a Vic-20 file.
+				//	J1/J2:	this C64 file should have the primary joystick in slot 1/2.
+				//	RO:		this disk image should be treated as read-only.
+			}
+		}
+
 		// Attach a 1540 if there are any disks here.
 		target->has_c1540 = !target->media.disks.empty();
 

Analyser/Static/Commodore/Target.hpp

@@ -31,7 +31,26 @@ struct Target: public ::Analyser::Static::Target {
 		Swedish
 	};
 
-	MemoryModel memory_model = MemoryModel::Unexpanded;
+	/// Maps from a named memory model to a bank enabled/disabled set.
+	void set_memory_model(MemoryModel memory_model) {
+		// This is correct for unexpanded and 32kb memory models.
+		enabled_ram.bank0 = enabled_ram.bank1 =
+		enabled_ram.bank2 = enabled_ram.bank3 =
+		enabled_ram.bank5 = memory_model == MemoryModel::ThirtyTwoKB;
+
+		// Bank 0 will need to be enabled if this is an 8kb machine.
+		enabled_ram.bank0 |= memory_model == MemoryModel::EightKB;
+	}
+	struct {
+		bool bank0 = false;
+		bool bank1 = false;
+		bool bank2 = false;
+		bool bank3 = false;
+		bool bank5 = false;
+					// Sic. There is no bank 4; this is because the area that logically would be
+					// bank 4 is occupied by the character ROM, colour RAM, hardware registers, etc.
+	} enabled_ram;
+
 	Region region = Region::European;
 	bool has_c1540 = false;
 	std::string loading_command;

Analyser/Static/Disassembler/Z80.cpp

@@ -63,9 +63,9 @@ class Accessor {
 #define z(v) (v & 7)
 
 Instruction::Condition condition_table[] = {
-	Instruction::Condition::NZ, 	Instruction::Condition::Z,
-	Instruction::Condition::NC, 	Instruction::Condition::C,
-	Instruction::Condition::PO, 	Instruction::Condition::PE,
+	Instruction::Condition::NZ,		Instruction::Condition::Z,
+	Instruction::Condition::NC,		Instruction::Condition::C,
+	Instruction::Condition::PO,		Instruction::Condition::PE,
 	Instruction::Condition::P,		Instruction::Condition::M
 };
 

Analyser/Static/MSX/StaticAnalyser.cpp

@@ -34,7 +34,7 @@ static std::unique_ptr<Analyser::Static::Target> CartridgeTarget(
 		output_segments.emplace_back(start_address, segment.data);
 	}
 
-	std::unique_ptr<Analyser::Static::MSX::Target> target(new Analyser::Static::MSX::Target);
+	auto target = std::make_unique<Analyser::Static::MSX::Target>();
 	target->machine = Analyser::Machine::MSX;
 	target->confidence = confidence;
 
@@ -269,7 +269,7 @@ Analyser::Static::TargetList Analyser::Static::MSX::GetTargets(const Media &medi
 	std::move(cartridge_targets.begin(), cartridge_targets.end(), std::back_inserter(destination));
 
 	// Consider building a target for disks and/or tapes.
-	std::unique_ptr<Target> target(new Target);
+	auto target = std::make_unique<Target>();
 
 	// Check tapes for loadable files.
 	for(auto &tape : media.tapes) {
@@ -285,7 +285,12 @@ Analyser::Static::TargetList Analyser::Static::MSX::GetTargets(const Media &medi
 		}
 	}
 
+	// Region selection: for now, this as simple as:
+	// "If a tape is involved, be European. Otherwise be American (i.e. English, but 60Hz)".
+	target->region = target->media.tapes.empty() ? Target::Region::USA : Target::Region::Europe;
+
 	// Blindly accept disks for now.
+	// TODO: how to spot an MSX disk?
 	target->media.disks = media.disks;
 	target->has_disk_drive = !media.disks.empty();
 

Analyser/Static/MSX/Target.hpp

@@ -19,6 +19,12 @@ namespace MSX {
 struct Target: public ::Analyser::Static::Target {
 	bool has_disk_drive = false;
 	std::string loading_command;
+
+	enum class Region {
+		Japan,
+		USA,
+		Europe
+	} region = Region::USA;
 };
 
 }

Analyser/Static/Macintosh/StaticAnalyser.cpp

@@ -0,0 +1,26 @@
+//
+//  StaticAnalyser.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 02/06/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#include "StaticAnalyser.hpp"
+#include "Target.hpp"
+
+Analyser::Static::TargetList Analyser::Static::Macintosh::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
+	// This analyser can comprehend disks and mass-storage devices only.
+	if(media.disks.empty() && media.mass_storage_devices.empty()) return {};
+
+	// As there is at least one usable media image, wave it through.
+	Analyser::Static::TargetList targets;
+
+	using Target = Analyser::Static::Macintosh::Target;
+	auto *target = new Target;
+	target->machine = Analyser::Machine::Macintosh;
+	target->media = media;
+	targets.push_back(std::unique_ptr<Analyser::Static::Target>(target));
+
+	return targets;
+}

Analyser/Static/Macintosh/StaticAnalyser.hpp

@@ -0,0 +1,27 @@
+//
+//  StaticAnalyser.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 02/06/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef Analyser_Static_Macintosh_StaticAnalyser_hpp
+#define Analyser_Static_Macintosh_StaticAnalyser_hpp
+
+#include "../StaticAnalyser.hpp"
+#include "../../../Storage/TargetPlatforms.hpp"
+#include <string>
+
+namespace Analyser {
+namespace Static {
+namespace Macintosh {
+
+TargetList GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms);
+
+}
+}
+}
+
+
+#endif /* Analyser_Static_Macintosh_StaticAnalyser_hpp */

Analyser/Static/Macintosh/Target.hpp

@@ -0,0 +1,31 @@
+//
+//  Target.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 03/06/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef Analyser_Static_Macintosh_Target_h
+#define Analyser_Static_Macintosh_Target_h
+
+namespace Analyser {
+namespace Static {
+namespace Macintosh {
+
+struct Target: public ::Analyser::Static::Target {
+	enum class Model {
+		Mac128k,
+		Mac512k,
+		Mac512ke,
+		MacPlus
+	};
+
+	Model model = Model::MacPlus;
+};
+
+}
+}
+}
+
+#endif /* Analyser_Static_Macintosh_Target_h */

Analyser/Static/Oric/StaticAnalyser.cpp

@@ -20,7 +20,9 @@
 
 using namespace Analyser::Static::Oric;
 
-static int Score(const Analyser::Static::MOS6502::Disassembly &disassembly, const std::set<uint16_t> &rom_functions, const std::set<uint16_t> &variable_locations) {
+namespace {
+
+int score(const Analyser::Static::MOS6502::Disassembly &disassembly, const std::set<uint16_t> &rom_functions, const std::set<uint16_t> &variable_locations) {
 	int score = 0;
 
 	for(const auto address : disassembly.outward_calls)		score += (rom_functions.find(address) != rom_functions.end()) ? 1 : -1;
@@ -30,7 +32,7 @@ static int Score(const Analyser::Static::MOS6502::Disassembly &disassembly, cons
 	return score;
 }
 
-static int Basic10Score(const Analyser::Static::MOS6502::Disassembly &disassembly) {
+int basic10_score(const Analyser::Static::MOS6502::Disassembly &disassembly) {
 	const std::set<uint16_t> rom_functions = {
 		0x0228,	0x022b,
 		0xc3ca,	0xc3f8,	0xc448,	0xc47c,	0xc4b5,	0xc4e3,	0xc4e0,	0xc524,	0xc56f,	0xc5a2,	0xc5f8,	0xc60a,	0xc6a5,	0xc6de,	0xc719,	0xc738,
@@ -51,10 +53,10 @@ static int Basic10Score(const Analyser::Static::MOS6502::Disassembly &disassembl
 		0x0228, 0x0229, 0x022a, 0x022b, 0x022c, 0x022d, 0x0230
 	};
 
-	return Score(disassembly, rom_functions, variable_locations);
+	return score(disassembly, rom_functions, variable_locations);
 }
 
-static int Basic11Score(const Analyser::Static::MOS6502::Disassembly &disassembly) {
+int basic11_score(const Analyser::Static::MOS6502::Disassembly &disassembly) {
 	const std::set<uint16_t> rom_functions = {
 		0x0238,	0x023b,	0x023e,	0x0241,	0x0244,	0x0247,
 		0xc3c6,	0xc3f4,	0xc444,	0xc47c,	0xc4a8,	0xc4d3,	0xc4e0,	0xc524,	0xc55f,	0xc592,	0xc5e8,	0xc5fa,	0xc692,	0xc6b3,	0xc6ee,	0xc70d,
@@ -76,10 +78,10 @@ static int Basic11Score(const Analyser::Static::MOS6502::Disassembly &disassembl
 		0x0244, 0x0245, 0x0246, 0x0247, 0x0248, 0x0249, 0x024a, 0x024b, 0x024c
 	};
 
-	return Score(disassembly, rom_functions, variable_locations);
+	return score(disassembly, rom_functions, variable_locations);
 }
 
-static bool IsMicrodisc(Storage::Encodings::MFM::Parser &parser) {
+bool is_microdisc(Storage::Encodings::MFM::Parser &parser) {
 	/*
 		The Microdisc boot sector is sector 2 of track 0 and contains a 23-byte signature.
 	*/
@@ -100,8 +102,51 @@ static bool IsMicrodisc(Storage::Encodings::MFM::Parser &parser) {
 	return !std::memcmp(signature, first_sample.data(), sizeof(signature));
 }
 
+bool is_400_loader(Storage::Encodings::MFM::Parser &parser, uint16_t range_start, uint16_t range_end) {
+	/*
+		Both the Jasmin and BD-DOS boot sectors are sector 1 of track 0 and are loaded at $400;
+		use disassembly to test for likely matches.
+	*/
+
+	Storage::Encodings::MFM::Sector *sector = parser.get_sector(0, 0, 1);
+	if(!sector) return false;
+	if(sector->samples.empty()) return false;
+
+	// Take a copy of the first sampling, and keep only the final 256 bytes (assuming at least that many were found).
+	std::vector<uint8_t> first_sample = sector->samples[0];
+	if(first_sample.size() < 256) return false;
+	if(first_sample.size() > 256) {
+		first_sample.erase(first_sample.end() - 256, first_sample.end());
+	}
+
+	// Grab a disassembly.
+	const auto disassembly =
+		Analyser::Static::MOS6502::Disassemble(first_sample, Analyser::Static::Disassembler::OffsetMapper(0x400), {0x400});
+
+	// Check for references to the Jasmin registers.
+	int register_hits = 0;
+	for(auto list : {disassembly.external_stores, disassembly.external_loads, disassembly.external_modifies}) {
+		for(auto address : list) {
+			register_hits += (address >= range_start && address <= range_end);
+		}
+	}
+
+	// Arbitrary, sure, but as long as at least two accesses to the requested register range are found, accept this.
+	return register_hits >= 2;
+}
+
+bool is_jasmin(Storage::Encodings::MFM::Parser &parser) {
+	return is_400_loader(parser, 0x3f4, 0x3ff);
+}
+
+bool is_bd500(Storage::Encodings::MFM::Parser &parser) {
+	return is_400_loader(parser, 0x310, 0x323);
+}
+
+}
+
 Analyser::Static::TargetList Analyser::Static::Oric::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
-	std::unique_ptr<Target> target(new Target);
+	auto target = std::make_unique<Target>();
 	target->machine = Machine::Oric;
 	target->confidence = 0.5;
 
@@ -111,16 +156,14 @@ Analyser::Static::TargetList Analyser::Static::Oric::GetTargets(const Media &med
 	for(auto &tape : media.tapes) {
 		std::vector<File> tape_files = GetFiles(tape);
 		tape->reset();
-		if(tape_files.size()) {
+		if(!tape_files.empty()) {
 			for(const auto &file : tape_files) {
 				if(file.data_type == File::MachineCode) {
 					std::vector<uint16_t> entry_points = {file.starting_address};
-					Analyser::Static::MOS6502::Disassembly disassembly =
+					const Analyser::Static::MOS6502::Disassembly disassembly =
 						Analyser::Static::MOS6502::Disassemble(file.data, Analyser::Static::Disassembler::OffsetMapper(file.starting_address), entry_points);
 
-					int basic10_score = Basic10Score(disassembly);
-					int basic11_score = Basic11Score(disassembly);
-					if(basic10_score > basic11_score) basic10_votes++; else basic11_votes++;
+					if(basic10_score(disassembly) > basic11_score(disassembly)) ++basic10_votes; else ++basic11_votes;
 				}
 			}
 
@@ -130,12 +173,22 @@ Analyser::Static::TargetList Analyser::Static::Oric::GetTargets(const Media &med
 	}
 
 	if(!media.disks.empty()) {
-		// Only the Microdisc is emulated right now, so accept only disks that it can boot from.
+		// 8-DOS is recognised by a dedicated Disk II analyser, so check only for Microdisc,
+		// Jasmin and BD-DOS formats here.
 		for(auto &disk: media.disks) {
 			Storage::Encodings::MFM::Parser parser(true, disk);
-			if(IsMicrodisc(parser)) {
+
+			if(is_microdisc(parser)) {
 				target->disk_interface = Target::DiskInterface::Microdisc;
 				target->media.disks.push_back(disk);
+			} else if(is_jasmin(parser)) {
+				target->disk_interface = Target::DiskInterface::Jasmin;
+				target->should_start_jasmin = true;
+				target->media.disks.push_back(disk);
+			} else if(is_bd500(parser)) {
+				target->disk_interface = Target::DiskInterface::BD500;
+				target->media.disks.push_back(disk);
+				target->rom = Target::ROM::BASIC10;
 			}
 		}
 	}

Analyser/Static/Oric/Target.hpp

@@ -26,12 +26,15 @@ struct Target: public ::Analyser::Static::Target {
 	enum class DiskInterface {
 		Microdisc,
 		Pravetz,
+		Jasmin,
+		BD500,
 		None
 	};
 
 	ROM rom = ROM::BASIC11;
 	DiskInterface disk_interface = DiskInterface::None;
 	std::string loading_command;
+	bool should_start_jasmin = false;
 };
 
 }

Analyser/Static/Sega/StaticAnalyser.cpp

@@ -0,0 +1,82 @@
+//
+//  StaticAnalyser.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 20/09/2018.
+//  Copyright © 2018 Thomas Harte. All rights reserved.
+//
+
+#include "StaticAnalyser.hpp"
+
+#include "Target.hpp"
+
+#include <algorithm>
+#include <cstring>
+
+Analyser::Static::TargetList Analyser::Static::Sega::GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms) {
+	if(media.cartridges.empty())
+		return {};
+
+	TargetList targets;
+	auto target = std::make_unique<Target>();
+
+	target->machine = Machine::MasterSystem;
+
+	// Files named .sg are treated as for the SG1000; otherwise assume a Master System.
+	if(file_name.size() >= 2 && *(file_name.end() - 2) == 's' && *(file_name.end() - 1) == 'g') {
+		target->model = Target::Model::SG1000;
+	} else {
+		target->model = Target::Model::MasterSystem;
+	}
+
+	// If this is a Master System title, look for a ROM header.
+	if(target->model == Target::Model::MasterSystem) {
+		const auto &data = media.cartridges.front()->get_segments()[0].data;
+
+		// First try to locate a header.
+		size_t header_offset = 0;
+		size_t potential_offsets[] = {0x1ff0, 0x3ff0, 0x7ff0};
+		for(auto potential_offset: potential_offsets) {
+			if(!memcmp(&data[potential_offset], "TMR SEGA", 8)) {
+				header_offset = potential_offset;
+				break;
+			}
+		}
+
+		// If a header was found, use it to crib region.
+		if(header_offset) {
+			// Treat export titles as European by default; decline to
+			// do so only if (US) or (NTSC) is in the file name.
+			const uint8_t region = data[header_offset + 0x0f] >> 4;
+			switch(region) {
+				default: break;
+				case 4: {
+					std::string lowercase_name = file_name;
+					std::transform(lowercase_name.begin(), lowercase_name.end(), lowercase_name.begin(), ::tolower);
+					if(lowercase_name.find("(jp)") == std::string::npos) {
+						target->region =
+							(lowercase_name.find("(us)") == std::string::npos &&
+							lowercase_name.find("(ntsc)") == std::string::npos) ? Target::Region::Europe : Target::Region::USA;
+					}
+				} break;
+			}
+
+			// Also check for a Codemasters header.
+			// If one is found, set the paging scheme appropriately.
+			const uint16_t inverse_checksum = uint16_t(0x10000 - (data[0x7fe6] | (data[0x7fe7] << 8)));
+			if(
+				data[0x7fe3] >= 0x87 && data[0x7fe3] < 0x96 &&									// i.e. game is dated between 1987 and 1996
+				(inverse_checksum&0xff) == data[0x7fe8] &&
+				(inverse_checksum >> 8) == data[0x7fe9] &&										// i.e. the standard checksum appears to be present
+				!data[0x7fea] && !data[0x7feb] && !data[0x7fec] && !data[0x7fed] && !data[0x7fee] && !data[0x7fef]
+			) {
+				target->paging_scheme = Target::PagingScheme::Codemasters;
+				target->model = Target::Model::MasterSystem2;
+			}
+		}
+	}
+
+	target->media.cartridges = media.cartridges;
+	targets.push_back(std::move(target));
+	return targets;
+}

Analyser/Static/Sega/StaticAnalyser.hpp

@@ -0,0 +1,26 @@
+//
+//  StaticAnalyser.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 20/09/2018.
+//  Copyright © 2018 Thomas Harte. All rights reserved.
+//
+
+#ifndef StaticAnalyser_Sega_StaticAnalyser_hpp
+#define StaticAnalyser_Sega_StaticAnalyser_hpp
+
+#include "../StaticAnalyser.hpp"
+#include "../../../Storage/TargetPlatforms.hpp"
+#include <string>
+
+namespace Analyser {
+namespace Static {
+namespace Sega {
+
+TargetList GetTargets(const Media &media, const std::string &file_name, TargetPlatform::IntType potential_platforms);
+
+}
+}
+}
+
+#endif /* StaticAnalyser_hpp */

Analyser/Static/Sega/Target.hpp

@@ -0,0 +1,46 @@
+//
+//  Target.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 23/09/2018.
+//  Copyright © 2018 Thomas Harte. All rights reserved.
+//
+
+#ifndef Analyser_Static_Sega_Target_h
+#define Analyser_Static_Sega_Target_h
+
+namespace Analyser {
+namespace Static {
+namespace Sega {
+
+struct Target: public ::Analyser::Static::Target {
+	enum class Model {
+		SG1000,
+		MasterSystem,
+		MasterSystem2,
+	};
+
+	enum class Region {
+		Japan,
+		USA,
+		Europe,
+		Brazil
+	};
+
+	enum class PagingScheme {
+		Sega,
+		Codemasters
+	};
+
+	Model model = Model::MasterSystem;
+	Region region = Region::Japan;
+	PagingScheme paging_scheme = PagingScheme::Sega;
+};
+
+#define is_master_system(v) v >= Analyser::Static::Sega::Target::Model::MasterSystem
+
+}
+}
+}
+
+#endif /* Analyser_Static_Sega_Target_h */

Analyser/Static/StaticAnalyser.cpp

@@ -17,12 +17,15 @@
 #include "Acorn/StaticAnalyser.hpp"
 #include "AmstradCPC/StaticAnalyser.hpp"
 #include "AppleII/StaticAnalyser.hpp"
-#include "Atari/StaticAnalyser.hpp"
+#include "Atari2600/StaticAnalyser.hpp"
+#include "AtariST/StaticAnalyser.hpp"
 #include "Coleco/StaticAnalyser.hpp"
 #include "Commodore/StaticAnalyser.hpp"
 #include "DiskII/StaticAnalyser.hpp"
+#include "Macintosh/StaticAnalyser.hpp"
 #include "MSX/StaticAnalyser.hpp"
 #include "Oric/StaticAnalyser.hpp"
+#include "Sega/StaticAnalyser.hpp"
 #include "ZX8081/StaticAnalyser.hpp"
 
 // Cartridges
@@ -34,15 +37,22 @@
 #include "../../Storage/Disk/DiskImage/Formats/AppleDSK.hpp"
 #include "../../Storage/Disk/DiskImage/Formats/CPCDSK.hpp"
 #include "../../Storage/Disk/DiskImage/Formats/D64.hpp"
+#include "../../Storage/Disk/DiskImage/Formats/MacintoshIMG.hpp"
 #include "../../Storage/Disk/DiskImage/Formats/G64.hpp"
 #include "../../Storage/Disk/DiskImage/Formats/DMK.hpp"
 #include "../../Storage/Disk/DiskImage/Formats/HFE.hpp"
+#include "../../Storage/Disk/DiskImage/Formats/MSA.hpp"
 #include "../../Storage/Disk/DiskImage/Formats/MSXDSK.hpp"
 #include "../../Storage/Disk/DiskImage/Formats/NIB.hpp"
 #include "../../Storage/Disk/DiskImage/Formats/OricMFMDSK.hpp"
 #include "../../Storage/Disk/DiskImage/Formats/SSD.hpp"
+#include "../../Storage/Disk/DiskImage/Formats/ST.hpp"
+#include "../../Storage/Disk/DiskImage/Formats/STX.hpp"
 #include "../../Storage/Disk/DiskImage/Formats/WOZ.hpp"
 
+// Mass Storage Devices (i.e. usually, hard disks)
+#include "../../Storage/MassStorage/Formats/HFV.hpp"
+
 // Tapes
 #include "../../Storage/Tape/Formats/CAS.hpp"
 #include "../../Storage/Tape/Formats/CommodoreTAP.hpp"
@@ -84,34 +94,39 @@ static Media GetMediaAndPlatforms(const std::string &file_name, TargetPlatform::
 		TryInsert(list, class, platforms)	\
 	}
 
-	Format("80", result.tapes, Tape::ZX80O81P, TargetPlatform::ZX8081)										// 80
-	Format("81", result.tapes, Tape::ZX80O81P, TargetPlatform::ZX8081)										// 81
-	Format("a26", result.cartridges, Cartridge::BinaryDump, TargetPlatform::Atari2600)						// A26
-	Format("adf", result.disks, Disk::DiskImageHolder<Storage::Disk::AcornADF>, TargetPlatform::Acorn)		// ADF
-	Format("bin", result.cartridges, Cartridge::BinaryDump, TargetPlatform::AllCartridge)					// BIN
-	Format("cas", result.tapes, Tape::CAS, TargetPlatform::MSX)												// CAS
-	Format("cdt", result.tapes, Tape::TZX, TargetPlatform::AmstradCPC)										// CDT
-	Format("col", result.cartridges, Cartridge::BinaryDump, TargetPlatform::ColecoVision)					// COL
-	Format("csw", result.tapes, Tape::CSW, TargetPlatform::AllTape)											// CSW
-	Format("d64", result.disks, Disk::DiskImageHolder<Storage::Disk::D64>, TargetPlatform::Commodore)		// D64
-	Format("dmk", result.disks, Disk::DiskImageHolder<Storage::Disk::DMK>, TargetPlatform::MSX)				// DMK
-	Format("do", result.disks, Disk::DiskImageHolder<Storage::Disk::AppleDSK>, TargetPlatform::DiskII)		// DO
-	Format("dsd", result.disks, Disk::DiskImageHolder<Storage::Disk::SSD>, TargetPlatform::Acorn)			// DSD
-	Format("dsk", result.disks, Disk::DiskImageHolder<Storage::Disk::CPCDSK>, TargetPlatform::AmstradCPC)	// DSK (Amstrad CPC)
-	Format("dsk", result.disks, Disk::DiskImageHolder<Storage::Disk::AppleDSK>, TargetPlatform::DiskII)		// DSK (Apple)
-	Format("dsk", result.disks, Disk::DiskImageHolder<Storage::Disk::MSXDSK>, TargetPlatform::MSX)			// DSK (MSX)
-	Format("dsk", result.disks, Disk::DiskImageHolder<Storage::Disk::OricMFMDSK>, TargetPlatform::Oric)		// DSK (Oric)
-	Format("g64", result.disks, Disk::DiskImageHolder<Storage::Disk::G64>, TargetPlatform::Commodore)		// G64
+	Format("80", result.tapes, Tape::ZX80O81P, TargetPlatform::ZX8081)											// 80
+	Format("81", result.tapes, Tape::ZX80O81P, TargetPlatform::ZX8081)											// 81
+	Format("a26", result.cartridges, Cartridge::BinaryDump, TargetPlatform::Atari2600)							// A26
+	Format("adf", result.disks, Disk::DiskImageHolder<Storage::Disk::AcornADF>, TargetPlatform::Acorn)			// ADF
+	Format("bin", result.cartridges, Cartridge::BinaryDump, TargetPlatform::AllCartridge)						// BIN (cartridge dump)
+	Format("cas", result.tapes, Tape::CAS, TargetPlatform::MSX)													// CAS
+	Format("cdt", result.tapes, Tape::TZX, TargetPlatform::AmstradCPC)											// CDT
+	Format("col", result.cartridges, Cartridge::BinaryDump, TargetPlatform::ColecoVision)						// COL
+	Format("csw", result.tapes, Tape::CSW, TargetPlatform::AllTape)												// CSW
+	Format("d64", result.disks, Disk::DiskImageHolder<Storage::Disk::D64>, TargetPlatform::Commodore)			// D64
+	Format("dmk", result.disks, Disk::DiskImageHolder<Storage::Disk::DMK>, TargetPlatform::MSX)					// DMK
+	Format("do", result.disks, Disk::DiskImageHolder<Storage::Disk::AppleDSK>, TargetPlatform::DiskII)			// DO
+	Format("dsd", result.disks, Disk::DiskImageHolder<Storage::Disk::SSD>, TargetPlatform::Acorn)				// DSD
+	Format("dsk", result.disks, Disk::DiskImageHolder<Storage::Disk::CPCDSK>, TargetPlatform::AmstradCPC)		// DSK (Amstrad CPC)
+	Format("dsk", result.disks, Disk::DiskImageHolder<Storage::Disk::AppleDSK>, TargetPlatform::DiskII)			// DSK (Apple II)
+	Format("dsk", result.disks, Disk::DiskImageHolder<Storage::Disk::MacintoshIMG>, TargetPlatform::Macintosh)	// DSK (Macintosh, floppy disk)
+	Format("dsk", result.mass_storage_devices, MassStorage::HFV, TargetPlatform::Macintosh)						// DSK (Macintosh, hard disk)
+	Format("dsk", result.disks, Disk::DiskImageHolder<Storage::Disk::MSXDSK>, TargetPlatform::MSX)				// DSK (MSX)
+	Format("dsk", result.disks, Disk::DiskImageHolder<Storage::Disk::OricMFMDSK>, TargetPlatform::Oric)			// DSK (Oric)
+	Format("g64", result.disks, Disk::DiskImageHolder<Storage::Disk::G64>, TargetPlatform::Commodore)			// G64
 	Format(	"hfe",
 			result.disks,
 			Disk::DiskImageHolder<Storage::Disk::HFE>,
 			TargetPlatform::Acorn | TargetPlatform::AmstradCPC | TargetPlatform::Commodore | TargetPlatform::Oric)
 			// HFE (TODO: switch to AllDisk once the MSX stops being so greedy)
-	Format("nib", result.disks, Disk::DiskImageHolder<Storage::Disk::NIB>, TargetPlatform::DiskII)			// NIB
-	Format("o", result.tapes, Tape::ZX80O81P, TargetPlatform::ZX8081)										// O
-	Format("p", result.tapes, Tape::ZX80O81P, TargetPlatform::ZX8081)										// P
-	Format("po", result.disks, Disk::DiskImageHolder<Storage::Disk::AppleDSK>, TargetPlatform::DiskII)		// PO
-	Format("p81", result.tapes, Tape::ZX80O81P, TargetPlatform::ZX8081)										// P81
+	Format("img", result.disks, Disk::DiskImageHolder<Storage::Disk::MacintoshIMG>, TargetPlatform::Macintosh)		// IMG (DiskCopy 4.2)
+	Format("image", result.disks, Disk::DiskImageHolder<Storage::Disk::MacintoshIMG>, TargetPlatform::Macintosh)	// IMG (DiskCopy 4.2)
+	Format("msa", result.disks, Disk::DiskImageHolder<Storage::Disk::MSA>, TargetPlatform::AtariST)				// MSA
+	Format("nib", result.disks, Disk::DiskImageHolder<Storage::Disk::NIB>, TargetPlatform::DiskII)				// NIB
+	Format("o", result.tapes, Tape::ZX80O81P, TargetPlatform::ZX8081)											// O
+	Format("p", result.tapes, Tape::ZX80O81P, TargetPlatform::ZX8081)											// P
+	Format("po", result.disks, Disk::DiskImageHolder<Storage::Disk::AppleDSK>, TargetPlatform::DiskII)			// PO
+	Format("p81", result.tapes, Tape::ZX80O81P, TargetPlatform::ZX8081)											// P81
 
 	// PRG
 	if(extension == "prg") {
@@ -128,14 +143,18 @@ static Media GetMediaAndPlatforms(const std::string &file_name, TargetPlatform::
 	Format(	"rom",
 			result.cartridges,
 			Cartridge::BinaryDump,
-			TargetPlatform::AcornElectron | TargetPlatform::ColecoVision | TargetPlatform::MSX)				// ROM
-	Format("ssd", result.disks, Disk::DiskImageHolder<Storage::Disk::SSD>, TargetPlatform::Acorn)			// SSD
-	Format("tap", result.tapes, Tape::CommodoreTAP, TargetPlatform::Commodore)								// TAP (Commodore)
-	Format("tap", result.tapes, Tape::OricTAP, TargetPlatform::Oric)										// TAP (Oric)
-	Format("tsx", result.tapes, Tape::TZX, TargetPlatform::MSX)												// TSX
-	Format("tzx", result.tapes, Tape::TZX, TargetPlatform::ZX8081)											// TZX
-	Format("uef", result.tapes, Tape::UEF, TargetPlatform::Acorn)											// UEF (tape)
-	Format("woz", result.disks, Disk::DiskImageHolder<Storage::Disk::WOZ>, TargetPlatform::DiskII)			// WOZ
+			TargetPlatform::AcornElectron | TargetPlatform::ColecoVision | TargetPlatform::MSX)					// ROM
+	Format("sg", result.cartridges, Cartridge::BinaryDump, TargetPlatform::Sega)								// SG
+	Format("sms", result.cartridges, Cartridge::BinaryDump, TargetPlatform::Sega)								// SMS
+	Format("ssd", result.disks, Disk::DiskImageHolder<Storage::Disk::SSD>, TargetPlatform::Acorn)				// SSD
+	Format("st", result.disks, Disk::DiskImageHolder<Storage::Disk::ST>, TargetPlatform::AtariST)				// ST
+	Format("stx", result.disks, Disk::DiskImageHolder<Storage::Disk::STX>, TargetPlatform::AtariST)				// STX
+	Format("tap", result.tapes, Tape::CommodoreTAP, TargetPlatform::Commodore)									// TAP (Commodore)
+	Format("tap", result.tapes, Tape::OricTAP, TargetPlatform::Oric)											// TAP (Oric)
+	Format("tsx", result.tapes, Tape::TZX, TargetPlatform::MSX)													// TSX
+	Format("tzx", result.tapes, Tape::TZX, TargetPlatform::ZX8081)												// TZX
+	Format("uef", result.tapes, Tape::UEF, TargetPlatform::Acorn)												// UEF (tape)
+	Format("woz", result.disks, Disk::DiskImageHolder<Storage::Disk::WOZ>, TargetPlatform::DiskII)				// WOZ
 
 #undef Format
 #undef Insert
@@ -152,7 +171,7 @@ Media Analyser::Static::GetMedia(const std::string &file_name) {
 TargetList Analyser::Static::GetTargets(const std::string &file_name) {
 	TargetList targets;
 
-	// Collect all disks, tapes and ROMs as can be extrapolated from this file, forming the
+	// Collect all disks, tapes ROMs, etc as can be extrapolated from this file, forming the
 	// union of all platforms this file might be a target for.
 	TargetPlatform::IntType potential_platforms = 0;
 	Media media = GetMediaAndPlatforms(file_name, potential_platforms);
@@ -166,12 +185,15 @@ TargetList Analyser::Static::GetTargets(const std::string &file_name) {
 	if(potential_platforms & TargetPlatform::Acorn)			Append(Acorn);
 	if(potential_platforms & TargetPlatform::AmstradCPC)	Append(AmstradCPC);
 	if(potential_platforms & TargetPlatform::AppleII)		Append(AppleII);
-	if(potential_platforms & TargetPlatform::Atari2600)		Append(Atari);
+	if(potential_platforms & TargetPlatform::Atari2600)		Append(Atari2600);
+	if(potential_platforms & TargetPlatform::AtariST)		Append(AtariST);
 	if(potential_platforms & TargetPlatform::ColecoVision)	Append(Coleco);
 	if(potential_platforms & TargetPlatform::Commodore)		Append(Commodore);
 	if(potential_platforms & TargetPlatform::DiskII)		Append(DiskII);
+	if(potential_platforms & TargetPlatform::Macintosh)		Append(Macintosh);
 	if(potential_platforms & TargetPlatform::MSX)			Append(MSX);
 	if(potential_platforms & TargetPlatform::Oric)			Append(Oric);
+	if(potential_platforms & TargetPlatform::Sega)			Append(Sega);
 	if(potential_platforms & TargetPlatform::ZX8081)		Append(ZX8081);
 	#undef Append
 

Analyser/Static/StaticAnalyser.hpp

@@ -11,9 +11,10 @@
 
 #include "../Machines.hpp"
 
-#include "../../Storage/Tape/Tape.hpp"
-#include "../../Storage/Disk/Disk.hpp"
 #include "../../Storage/Cartridge/Cartridge.hpp"
+#include "../../Storage/Disk/Disk.hpp"
+#include "../../Storage/MassStorage/MassStorageDevice.hpp"
+#include "../../Storage/Tape/Tape.hpp"
 
 #include <memory>
 #include <string>
@@ -29,9 +30,10 @@ struct Media {
 	std::vector<std::shared_ptr<Storage::Disk::Disk>> disks;
 	std::vector<std::shared_ptr<Storage::Tape::Tape>> tapes;
 	std::vector<std::shared_ptr<Storage::Cartridge::Cartridge>> cartridges;
+	std::vector<std::shared_ptr<Storage::MassStorage::MassStorageDevice>> mass_storage_devices;
 
 	bool empty() const {
-		return disks.empty() && tapes.empty() && cartridges.empty();
+		return disks.empty() && tapes.empty() && cartridges.empty() && mass_storage_devices.empty();
 	}
 };
 

ClockReceiver/ClockReceiver.hpp

@@ -9,6 +9,9 @@
 #ifndef ClockReceiver_hpp
 #define ClockReceiver_hpp
 
+#include "ForceInline.hpp"
+#include <cstdint>
+
 /*
 	Informal pattern for all classes that run from a clock cycle:
 
@@ -52,149 +55,193 @@
 */
 template <class T> class WrappedInt {
 	public:
-		inline WrappedInt(int l) : length_(l) {}
-		inline WrappedInt() : length_(0) {}
+		using IntType = int64_t;
 
-		inline T &operator =(const T &rhs) {
+		forceinline constexpr WrappedInt(IntType l) noexcept : length_(l) {}
+		forceinline constexpr WrappedInt() noexcept : length_(0) {}
+
+		forceinline T &operator =(const T &rhs) {
 			length_ = rhs.length_;
 			return *this;
 		}
 
-		inline T &operator +=(const T &rhs) {
+		forceinline T &operator +=(const T &rhs) {
 			length_ += rhs.length_;
 			return *static_cast<T *>(this);
 		}
 
-		inline T &operator -=(const T &rhs) {
+		forceinline T &operator -=(const T &rhs) {
 			length_ -= rhs.length_;
 			return *static_cast<T *>(this);
 		}
 
-		inline T &operator ++() {
+		forceinline T &operator ++() {
 			++ length_;
 			return *static_cast<T *>(this);
 		}
 
-		inline T &operator ++(int) {
+		forceinline T &operator ++(int) {
 			length_ ++;
 			return *static_cast<T *>(this);
 		}
 
-		inline T &operator --() {
+		forceinline T &operator --() {
 			-- length_;
 			return *static_cast<T *>(this);
 		}
 
-		inline T &operator --(int) {
+		forceinline T &operator --(int) {
 			length_ --;
 			return *static_cast<T *>(this);
 		}
 
-		inline T &operator %=(const T &rhs) {
+		forceinline T &operator *=(const T &rhs) {
+			length_ *= rhs.length_;
+			return *static_cast<T *>(this);
+		}
+
+		forceinline T &operator /=(const T &rhs) {
+			length_ /= rhs.length_;
+			return *static_cast<T *>(this);
+		}
+
+		forceinline T &operator %=(const T &rhs) {
 			length_ %= rhs.length_;
 			return *static_cast<T *>(this);
 		}
 
-		inline T &operator &=(const T &rhs) {
+		forceinline T &operator &=(const T &rhs) {
 			length_ &= rhs.length_;
 			return *static_cast<T *>(this);
 		}
 
-		inline T operator +(const T &rhs) const			{	return T(length_ + rhs.length_);	}
-		inline T operator -(const T &rhs) const			{	return T(length_ - rhs.length_);	}
+		forceinline constexpr T operator +(const T &rhs) const			{	return T(length_ + rhs.length_);	}
+		forceinline constexpr T operator -(const T &rhs) const			{	return T(length_ - rhs.length_);	}
 
-		inline T operator %(const T &rhs) const			{	return T(length_ % rhs.length_);	}
-		inline T operator &(const T &rhs) const			{	return T(length_ & rhs.length_);	}
+		forceinline constexpr T operator *(const T &rhs) const			{	return T(length_ * rhs.length_);	}
+		forceinline constexpr T operator /(const T &rhs) const			{	return T(length_ / rhs.length_);	}
 
-		inline T operator -() const						{	return T(- length_);				}
+		forceinline constexpr T operator %(const T &rhs) const			{	return T(length_ % rhs.length_);	}
+		forceinline constexpr T operator &(const T &rhs) const			{	return T(length_ & rhs.length_);	}
 
-		inline bool operator <(const T &rhs) const		{	return length_ < rhs.length_;		}
-		inline bool operator >(const T &rhs) const		{	return length_ > rhs.length_;		}
-		inline bool operator <=(const T &rhs) const		{	return length_ <= rhs.length_;		}
-		inline bool operator >=(const T &rhs) const		{	return length_ >= rhs.length_;		}
-		inline bool operator ==(const T &rhs) const		{	return length_ == rhs.length_;		}
-		inline bool operator !=(const T &rhs) const		{	return length_ != rhs.length_;		}
+		forceinline constexpr T operator -() const						{	return T(- length_);				}
 
-		inline bool operator !() const					{	return !length_;					}
+		forceinline constexpr bool operator <(const T &rhs) const		{	return length_ < rhs.length_;		}
+		forceinline constexpr bool operator >(const T &rhs) const		{	return length_ > rhs.length_;		}
+		forceinline constexpr bool operator <=(const T &rhs) const		{	return length_ <= rhs.length_;		}
+		forceinline constexpr bool operator >=(const T &rhs) const		{	return length_ >= rhs.length_;		}
+		forceinline constexpr bool operator ==(const T &rhs) const		{	return length_ == rhs.length_;		}
+		forceinline constexpr bool operator !=(const T &rhs) const		{	return length_ != rhs.length_;		}
+
+		forceinline constexpr bool operator !() const					{	return !length_;					}
 		// bool operator () is not supported because it offers an implicit cast to int, which is prone silently to permit misuse
 
-		inline int as_int() const { return length_; }
+		/// @returns The underlying int, cast to an integral type of your choosing.
+		template<typename Type = IntType> forceinline constexpr Type as() const { return Type(length_); }
+
+		/// @returns The underlying int, in its native form.
+		forceinline constexpr IntType as_integral() const { return length_; }
 
 		/*!
 			Severs from @c this the effect of dividing by @c divisor; @c this will end up with
 			the value of @c this modulo @c divisor and @c divided by @c divisor is returned.
 		*/
-		inline T divide(const T &divisor) {
-			T result(length_ / divisor.length_);
-			length_ %= divisor.length_;
-			return result;
+		template <typename Result = T> forceinline Result divide(const T &divisor) {
+			Result r;
+			static_cast<T *>(this)->fill(r, divisor);
+			return r;
 		}
 
 		/*!
 			Flushes the value in @c this. The current value is returned, and the internal value
 			is reset to zero.
 		*/
-		inline T flush() {
-			T result(length_);
-			length_ = 0;
-			return result;
+		template <typename Result> Result flush() {
+			// Jiggery pokery here; switching to function overloading avoids
+			// the namespace-level requirement for template specialisation.
+			Result r;
+			static_cast<T *>(this)->fill(r);
+			return r;
 		}
 
 		// operator int() is deliberately not provided, to avoid accidental subtitution of
 		// classes that use this template.
 
 	protected:
-		int length_;
+		IntType length_;
 };
 
 /// Describes an integer number of whole cycles: pairs of clock signal transitions.
 class Cycles: public WrappedInt<Cycles> {
 	public:
-		inline Cycles(int l) : WrappedInt<Cycles>(l) {}
-		inline Cycles() : WrappedInt<Cycles>() {}
-		inline Cycles(const Cycles &cycles) : WrappedInt<Cycles>(cycles.length_) {}
+		forceinline constexpr Cycles(IntType l) noexcept : WrappedInt<Cycles>(l) {}
+		forceinline constexpr Cycles() noexcept : WrappedInt<Cycles>() {}
+		forceinline constexpr Cycles(const Cycles &cycles) noexcept : WrappedInt<Cycles>(cycles.length_) {}
+
+	private:
+		friend WrappedInt;
+		void fill(Cycles &result) {
+			result.length_ = length_;
+			length_ = 0;
+		}
+
+		void fill(Cycles &result, const Cycles &divisor) {
+			result.length_ = length_ / divisor.length_;
+			length_ %= divisor.length_;
+		}
 };
 
 /// Describes an integer number of half cycles: single clock signal transitions.
 class HalfCycles: public WrappedInt<HalfCycles> {
 	public:
-		inline HalfCycles(int l) : WrappedInt<HalfCycles>(l) {}
-		inline HalfCycles() : WrappedInt<HalfCycles>() {}
+		forceinline constexpr HalfCycles(IntType l) noexcept : WrappedInt<HalfCycles>(l) {}
+		forceinline constexpr HalfCycles() noexcept : WrappedInt<HalfCycles>() {}
 
-		inline HalfCycles(const Cycles cycles) : WrappedInt<HalfCycles>(cycles.as_int() * 2) {}
-		inline HalfCycles(const HalfCycles &half_cycles) : WrappedInt<HalfCycles>(half_cycles.length_) {}
+		forceinline constexpr HalfCycles(const Cycles &cycles) noexcept : WrappedInt<HalfCycles>(cycles.as_integral() * 2) {}
+		forceinline constexpr HalfCycles(const HalfCycles &half_cycles) noexcept : WrappedInt<HalfCycles>(half_cycles.length_) {}
 
 		/// @returns The number of whole cycles completely covered by this span of half cycles.
-		inline Cycles cycles() {
+		forceinline constexpr Cycles cycles() const {
 			return Cycles(length_ >> 1);
 		}
 
-		/// Flushes the whole cycles in @c this, subtracting that many from the total stored here.
-		inline Cycles flush_cycles() {
-			Cycles result(length_ >> 1);
-			length_ &= 1;
-			return result;
-		}
-
-		/// Flushes the half cycles in @c this, returning the number stored and setting this total to zero.
-		inline HalfCycles flush() {
-			HalfCycles result(length_);
-			length_ = 0;
-			return result;
-		}
-
 		/*!
 			Severs from @c this the effect of dividing by @c divisor; @c this will end up with
 			the value of @c this modulo @c divisor and @c divided by @c divisor is returned.
 		*/
-		inline Cycles divide_cycles(const Cycles &divisor) {
-			HalfCycles half_divisor = HalfCycles(divisor);
-			Cycles result(length_ / half_divisor.length_);
+		forceinline Cycles divide_cycles(const Cycles &divisor) {
+			const HalfCycles half_divisor = HalfCycles(divisor);
+			const Cycles result(length_ / half_divisor.length_);
 			length_ %= half_divisor.length_;
 			return result;
 		}
+
+	private:
+		friend WrappedInt;
+		void fill(Cycles &result) {
+			result = Cycles(length_ >> 1);
+			length_ &= 1;
+		}
+
+		void fill(HalfCycles &result) {
+			result.length_ = length_;
+			length_ = 0;
+		}
+
+		void fill(Cycles &result, const HalfCycles &divisor) {
+			result = Cycles(length_ / (divisor.length_ << 1));
+			length_ %= (divisor.length_ << 1);
+		}
+
+		void fill(HalfCycles &result, const HalfCycles &divisor) {
+			result.length_ = length_ / divisor.length_;
+			length_ %= divisor.length_;
+		}
 };
 
+// Create a specialisation of WrappedInt::flush for converting HalfCycles to Cycles
+// without losing the fractional part.
+
 /*!
 	If a component implements only run_for(Cycles), an owner can wrap it in HalfClockReceiver
 	automatically to gain run_for(HalfCycles).
@@ -203,10 +250,9 @@ template <class T> class HalfClockReceiver: public T {
 	public:
 		using T::T;
 
-		using T::run_for;
-		inline void run_for(const HalfCycles half_cycles) {
+		forceinline void run_for(const HalfCycles half_cycles) {
 			half_cycles_ += half_cycles;
-			T::run_for(half_cycles_.flush_cycles());
+			T::run_for(half_cycles_.flush<Cycles>());
 		}
 
 	private:

ClockReceiver/ClockingHintSource.hpp

@@ -0,0 +1,88 @@
+//
+//  ClockingHintSource.h
+//  Clock Signal
+//
+//  Created by Thomas Harte on 20/08/2017.
+//  Copyright 2017 Thomas Harte. All rights reserved.
+//
+
+#ifndef ClockingHintSource_hpp
+#define ClockingHintSource_hpp
+
+namespace ClockingHint {
+
+enum class Preference {
+	/// The component doesn't currently require a clock signal.
+	None,
+	/// The component can be clocked only immediate prior to (explicit) accesses.
+	JustInTime,
+	/// The component require real-time clocking.
+	RealTime
+};
+
+class Source;
+
+struct Observer {
+	/// Called to inform an observer that the component @c component has changed its clocking requirements.
+	virtual void set_component_prefers_clocking(Source *component, Preference clocking) = 0;
+};
+
+/*!
+	An clocking hint source is any component that can provide hints as to the type of
+	clocking required for accurate emulation. A disk controller is an archetypal example.
+
+	Types of clocking are:
+
+		- none:
+			a component that acts and reacts to direct contact but does not have a state that autonomously evolves.
+			E.g. a ROM, RAM, or some kinds of disk controller when not in the process of performing a command.
+
+		- just-in-time:
+			a component that has an evolving state but can receive clock updates only immediately before a
+			direct contact. This is possibly the most common kind of component.
+
+		- real-time:
+			a component that needs to be clocked in 'real time' (i.e. in terms of the emulated machine). For example
+			so that it can announce an interrupt at the proper moment, because it is monitoring some aspect of
+			the machine rather than waiting to be called upon, or because there's some other non-obvious relationship
+			at play.
+
+	A clocking hint source can signal changes in preferred clocking to an observer.
+
+	This is intended to allow for performance improvements to machines with components that can be messaged selectively.
+	The observer callout is virtual so the intended use case is that a machine holds a component that might go through
+	periods of different clocking requirements.
+
+	Transitions should be sufficiently infrequent that a virtual call to announce them costs little enough that
+	the saved or deferred ::run_fors add up to a substantial amount.
+
+	The hint provided is just that: a hint. Owners may perform ::run_for at a greater frequency.
+*/
+class Source {
+	public:
+		/// Registers @c observer as the new clocking observer.
+		void set_clocking_hint_observer(Observer *observer) {
+			observer_ = observer;
+			update_clocking_observer();
+		}
+
+		/// @returns the current preferred clocking strategy.
+		virtual Preference preferred_clocking() = 0;
+
+	private:
+		Observer *observer_ = nullptr;
+
+	protected:
+		/*!
+			Provided for subclasses; call this whenever the clocking preference might have changed.
+			This will notify the observer if there is one.
+		*/
+		void update_clocking_observer() {
+			if(!observer_) return;
+			observer_->set_component_prefers_clocking(this, preferred_clocking());
+		}
+};
+
+}
+
+#endif /* ClockingHintSource_h */

ClockReceiver/DeferredQueue.hpp

@@ -0,0 +1,124 @@
+//
+//  DeferredQueue.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 23/08/2018.
+//  Copyright © 2018 Thomas Harte. All rights reserved.
+//
+
+#ifndef DeferredQueue_h
+#define DeferredQueue_h
+
+#include <functional>
+#include <vector>
+
+/*!
+	Provides the logic to insert into and traverse a list of future scheduled items.
+*/
+template <typename TimeUnit> class DeferredQueue {
+	public:
+		/*!
+			Schedules @c action to occur in @c delay units of time.
+		*/
+		void defer(TimeUnit delay, const std::function<void(void)> &action) {
+			// Apply immediately if there's no delay (or a negative delay).
+			if(delay <= TimeUnit(0)) {
+				action();
+				return;
+			}
+
+			if(!pending_actions_.empty()) {
+				// Otherwise enqueue, having subtracted the delay for any preceding events,
+				// and subtracting from the subsequent, if any.
+				auto insertion_point = pending_actions_.begin();
+				while(insertion_point != pending_actions_.end() && insertion_point->delay < delay) {
+					delay -= insertion_point->delay;
+					++insertion_point;
+				}
+				if(insertion_point != pending_actions_.end()) {
+					insertion_point->delay -= delay;
+				}
+
+				pending_actions_.emplace(insertion_point, delay, action);
+			} else {
+				pending_actions_.emplace_back(delay, action);
+			}
+		}
+
+		/*!
+			@returns The amount of time until the next enqueued action will occur,
+				or TimeUnit(-1) if the queue is empty.
+		*/
+		TimeUnit time_until_next_action() {
+			if(pending_actions_.empty()) return TimeUnit(-1);
+			return pending_actions_.front().delay;
+		}
+
+		/*!
+			Advances the queue the specified amount of time, performing any actions it reaches.
+		*/
+		void advance(TimeUnit time) {
+			auto erase_iterator = pending_actions_.begin();
+			while(erase_iterator != pending_actions_.end()) {
+				erase_iterator->delay -= time;
+				if(erase_iterator->delay <= TimeUnit(0)) {
+					time = -erase_iterator->delay;
+					erase_iterator->action();
+					++erase_iterator;
+				} else {
+					break;
+				}
+			}
+			if(erase_iterator != pending_actions_.begin()) {
+				pending_actions_.erase(pending_actions_.begin(), erase_iterator);
+			}
+		}
+
+	private:
+		// The list of deferred actions.
+		struct DeferredAction {
+			TimeUnit delay;
+			std::function<void(void)> action;
+
+			DeferredAction(TimeUnit delay, const std::function<void(void)> &action) : delay(delay), action(std::move(action)) {}
+		};
+		std::vector<DeferredAction> pending_actions_;
+};
+
+/*!
+	A DeferredQueue maintains a list of ordered actions and the times at which
+	they should happen, and divides a total execution period up into the portions
+	that occur between those actions, triggering each action when it is reached.
+
+	This list is efficient only for short queues.
+*/
+template <typename TimeUnit> class DeferredQueuePerformer: public DeferredQueue<TimeUnit> {
+	public:
+		/// Constructs a DeferredQueue that will call target(period) in between deferred actions.
+		DeferredQueuePerformer(std::function<void(TimeUnit)> &&target) : target_(std::move(target)) {}
+
+		/*!
+			Runs for @c length units of time.
+
+			The constructor-supplied target will be called with one or more periods that add up to @c length;
+			any scheduled actions will be called between periods.
+		*/
+		void run_for(TimeUnit length) {
+			auto time_to_next = DeferredQueue<TimeUnit>::time_until_next_action();
+			while(time_to_next != TimeUnit(-1) && time_to_next <= length) {
+				target_(time_to_next);
+				length -= time_to_next;
+				DeferredQueue<TimeUnit>::advance(time_to_next);
+			}
+
+			DeferredQueue<TimeUnit>::advance(length);
+			target_(length);
+
+			// TODO: optimise this to avoid the multiple std::vector deletes. Find a neat way to expose that solution, maybe?
+		}
+
+	private:
+		std::function<void(TimeUnit)> target_;
+};
+
+#endif /* DeferredQueue_h */

ClockReceiver/ForceInline.hpp

@@ -9,9 +9,9 @@
 #ifndef ForceInline_hpp
 #define ForceInline_hpp
 
-#ifdef DEBUG
+#ifndef NDEBUG
 
-#define forceinline
+#define forceinline inline
 
 #else
 

ClockReceiver/JustInTime.hpp

@@ -0,0 +1,173 @@
+//
+//  JustInTime.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 28/07/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef JustInTime_h
+#define JustInTime_h
+
+#include "../Concurrency/AsyncTaskQueue.hpp"
+#include "ForceInline.hpp"
+
+/*!
+	A JustInTimeActor holds (i) an embedded object with a run_for method; and (ii) an amount
+	of time since run_for was last called.
+
+	Time can be added using the += operator. The -> operator can be used to access the
+	embedded object. All time accumulated will be pushed to object before the pointer is returned.
+
+	Machines that accumulate HalfCycle time but supply to a Cycle-counted device may supply a
+	separate @c TargetTimeScale at template declaration.
+*/
+template <class T, int multiplier = 1, int divider = 1, class LocalTimeScale = HalfCycles, class TargetTimeScale = LocalTimeScale> class JustInTimeActor {
+	public:
+		/// Constructs a new JustInTimeActor using the same construction arguments as the included object.
+		template<typename... Args> JustInTimeActor(Args&&... args) : object_(std::forward<Args>(args)...) {}
+
+		/// Adds time to the actor.
+		forceinline void operator += (const LocalTimeScale &rhs) {
+			if constexpr (multiplier != 1) {
+				time_since_update_ += rhs * multiplier;
+			} else {
+				time_since_update_ += rhs;
+			}
+			is_flushed_ = false;
+		}
+
+		/// Flushes all accumulated time and returns a pointer to the included object.
+		forceinline T *operator->() {
+			flush();
+			return &object_;
+		}
+
+		/// Acts exactly as per the standard ->, but preserves constness.
+		forceinline const T *operator->() const {
+			auto non_const_this = const_cast<JustInTimeActor<T, multiplier, divider, LocalTimeScale, TargetTimeScale> *>(this);
+			non_const_this->flush();
+			return &object_;
+		}
+
+		/// Returns a pointer to the included object without flushing time.
+		forceinline T *last_valid() {
+			return &object_;
+		}
+
+		/// Flushes all accumulated time.
+		forceinline void flush() {
+			if(!is_flushed_) {
+				is_flushed_ = true;
+				if constexpr (divider == 1) {
+					const auto duration = time_since_update_.template flush<TargetTimeScale>();
+					object_.run_for(duration);
+				} else {
+					const auto duration = time_since_update_.template divide<TargetTimeScale>(LocalTimeScale(divider));
+					if(duration > TargetTimeScale(0))
+						object_.run_for(duration);
+				}
+			}
+		}
+
+	private:
+		T object_;
+		LocalTimeScale time_since_update_;
+		bool is_flushed_ = true;
+};
+
+/*!
+	A RealTimeActor presents the same interface as a JustInTimeActor but doesn't defer work.
+	Time added will be performed immediately.
+
+	Its primary purpose is to allow consumers to remain flexible in their scheduling.
+*/
+template <class T, int multiplier = 1, int divider = 1, class LocalTimeScale = HalfCycles, class TargetTimeScale = LocalTimeScale> class RealTimeActor {
+	public:
+		template<typename... Args> RealTimeActor(Args&&... args) : object_(std::forward<Args>(args)...) {}
+
+		forceinline void operator += (const LocalTimeScale &rhs) {
+			if constexpr (multiplier == 1 && divider == 1) {
+				object_.run_for(TargetTimeScale(rhs));
+				return;
+			}
+
+			if constexpr (multiplier == 1) {
+				accumulated_time_ += rhs;
+			} else {
+				accumulated_time_ += rhs * multiplier;
+			}
+
+			if constexpr (divider == 1) {
+				const auto duration = accumulated_time_.template flush<TargetTimeScale>();
+				object_.run_for(duration);
+			} else {
+				const auto duration = accumulated_time_.template divide<TargetTimeScale>(LocalTimeScale(divider));
+				if(duration > TargetTimeScale(0))
+					object_.run_for(duration);
+			}
+		}
+
+		forceinline T *operator->()				{	return &object_;	}
+		forceinline const T *operator->() const	{	return &object_;	}
+		forceinline T *last_valid() 			{	return &object_;	}
+		forceinline void flush()				{}
+
+	private:
+		T object_;
+		LocalTimeScale accumulated_time_;
+};
+
+/*!
+	A AsyncJustInTimeActor acts like a JustInTimeActor but additionally contains an AsyncTaskQueue.
+	Any time the amount of accumulated time crosses a threshold provided at construction time,
+	the object will be updated on the AsyncTaskQueue.
+*/
+template <class T, class LocalTimeScale = HalfCycles, class TargetTimeScale = LocalTimeScale> class AsyncJustInTimeActor {
+	public:
+		/// Constructs a new AsyncJustInTimeActor using the same construction arguments as the included object.
+		template<typename... Args> AsyncJustInTimeActor(TargetTimeScale threshold, Args&&... args) :
+			object_(std::forward<Args>(args)...),
+		 	threshold_(threshold) {}
+
+		/// Adds time to the actor.
+		inline void operator += (const LocalTimeScale &rhs) {
+			time_since_update_ += rhs;
+			if(time_since_update_ >= threshold_) {
+				time_since_update_ -= threshold_;
+				task_queue_.enqueue([this] () {
+					object_.run_for(threshold_);
+				});
+			}
+			is_flushed_ = false;
+		}
+
+		/// Flushes all accumulated time and returns a pointer to the included object.
+		inline T *operator->() {
+			flush();
+			return &object_;
+		}
+
+		/// Returns a pointer to the included object without flushing time.
+		inline T *last_valid() {
+			return &object_;
+		}
+
+		/// Flushes all accumulated time.
+		inline void flush() {
+			if(!is_flushed_) {
+				task_queue_.flush();
+				object_.run_for(time_since_update_.template flush<TargetTimeScale>());
+				is_flushed_ = true;
+			}
+		}
+
+	private:
+		T object_;
+		LocalTimeScale time_since_update_;
+		TargetTimeScale threshold_;
+		bool is_flushed_ = true;
+		Concurrency::AsyncTaskQueue task_queue_;
+};
+
+#endif /* JustInTime_h */

ClockReceiver/ScanSynchroniser.hpp

@@ -0,0 +1,88 @@
+//
+//  ScanSynchroniser.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 09/02/2020.
+//  Copyright © 2020 Thomas Harte. All rights reserved.
+//
+
+#ifndef ScanSynchroniser_h
+#define ScanSynchroniser_h
+
+#include "../Outputs/ScanTarget.hpp"
+
+#include <cmath>
+
+namespace Time {
+
+/*!
+	Where an emulated machine is sufficiently close to a host machine's frame rate that a small nudge in
+	its speed multiplier will bring it into frame synchronisation, the ScanSynchroniser provides a sequence of
+	speed multipliers designed both to adjust the machine to the proper speed and, in a reasonable amount
+	of time, to bring it into phase.
+*/
+class ScanSynchroniser {
+	public:
+		/*!
+			@returns @c true if the emulated machine can be synchronised with the host frame output based on its
+				current @c [scan]status and the host machine's @c frame_duration; @c false otherwise.
+		*/
+		bool can_synchronise(const Outputs::Display::ScanStatus &scan_status, double frame_duration) {
+			ratio_ = 1.0;
+			if(scan_status.field_duration_gradient < 0.00001) {
+				// Check out the machine's current frame time.
+				// If it's within 3% of a non-zero integer multiple of the
+				// display rate, mark this time window to be split over the sync.
+				ratio_ = (frame_duration * base_multiplier_) / scan_status.field_duration;
+				const double integer_ratio = round(ratio_);
+				if(integer_ratio > 0.0) {
+					ratio_ /= integer_ratio;
+					return ratio_ <= maximum_rate_adjustment && ratio_ >= 1.0 / maximum_rate_adjustment;
+				}
+			}
+			return false;
+		}
+
+		/*!
+			@returns The appropriate speed multiplier for the next frame based on the inputs previously supplied to @c can_synchronise.
+				Results are undefined if @c can_synchroise returned @c false.
+		*/
+		double next_speed_multiplier(const Outputs::Display::ScanStatus &scan_status) {
+			// The host versus emulated ratio is calculated based on the current perceived frame duration of the machine.
+			// Either that number is exactly correct or it's already the result of some sort of low-pass filter. So there's
+			// no benefit to second guessing it here — just take it to be correct.
+			//
+			// ... with one slight caveat, which is that it is desireable to adjust phase here, to align vertical sync points.
+			// So the set speed multiplier may be adjusted slightly to aim for that.
+			double speed_multiplier = 1.0 / (ratio_ / base_multiplier_);
+			if(scan_status.current_position > 0.0) {
+				if(scan_status.current_position < 0.5) speed_multiplier /= phase_adjustment_ratio;
+				else speed_multiplier *= phase_adjustment_ratio;
+			}
+			speed_multiplier_ = (speed_multiplier_ * 0.95) + (speed_multiplier * 0.05);
+			return speed_multiplier_ * base_multiplier_;
+		}
+
+		void set_base_speed_multiplier(double multiplier) {
+			base_multiplier_ = multiplier;
+		}
+
+		double get_base_speed_multiplier() {
+			return base_multiplier_;
+		}
+
+	private:
+		static constexpr double maximum_rate_adjustment = 1.03;
+		static constexpr double phase_adjustment_ratio = 1.005;
+
+		// Managed local state.
+		double speed_multiplier_ = 1.0;
+		double base_multiplier_ = 1.0;
+
+		// Temporary storage to bridge the can_synchronise -> next_speed_multiplier gap.
+		double ratio_ = 1.0;
+};
+
+}
+
+#endif /* ScanSynchroniser_h */

ClockReceiver/Sleeper.hpp

@@ -1,60 +0,0 @@
-//
-//  Sleeper.h
-//  Clock Signal
-//
-//  Created by Thomas Harte on 20/08/2017.
-//  Copyright 2017 Thomas Harte. All rights reserved.
-//
-
-#ifndef Sleeper_hpp
-#define Sleeper_hpp
-
-/*!
-	A sleeper is any component that sometimes requires a clock but at other times is 'asleep', i.e. is not doing
-	any clock-derived work, so needn't receive a clock. A disk controller is an archetypal example.
-
-	A sleeper will signal sleeps and wakes to an observer.
-
-	This is intended to allow for performance improvements to machines with components that can sleep. The observer
-	callout is virtual so the intended use case is that a machine holds a component that might sleep. Its transitions
-	into and out of sleep are sufficiently infrequent that a virtual call to announce them costs sufficiently little that
-	the saved ::run_fors add up to a substantial amount.
-
-	By convention, sleeper components must be willing to accept ::run_for even after announcing sleep. It's a hint,
-	not a command.
-*/
-class Sleeper {
-	public:
-		Sleeper() : sleep_observer_(nullptr) {}
-
-		class SleepObserver {
-			public:
-				/// Called to inform an observer that the component @c component has either gone to sleep or become awake.
-				virtual void set_component_is_sleeping(Sleeper *component, bool is_sleeping) = 0;
-		};
-
-		/// Registers @c observer as the new sleep observer;
-		void set_sleep_observer(SleepObserver *observer) {
-			sleep_observer_ = observer;
-		}
-
-		/// @returns @c true if the component is currently sleeping; @c false otherwise.
-		virtual bool is_sleeping() = 0;
-
-	protected:
-		/// Provided for subclasses; send sleep announcements to the sleep_observer_.
-		SleepObserver *sleep_observer_;
-
-		/*!
-			Provided for subclasses; call this whenever is_sleeping might have changed, and the observer will be notified,
-			if one exists.
-
-			@c is_sleeping will be called only if there is an observer.
-		*/
-		void update_sleep_observer() {
-			if(!sleep_observer_) return;
-			sleep_observer_->set_component_is_sleeping(this, is_sleeping());
-		}
-};
-
-#endif /* Sleeper_h */

ClockReceiver/TimeTypes.hpp

@@ -9,9 +9,16 @@
 #ifndef TimeTypes_h
 #define TimeTypes_h
 
+#include <chrono>
+
 namespace Time {
 
 typedef double Seconds;
+typedef int64_t Nanos;
+
+inline Nanos nanos_now() {
+	return std::chrono::duration_cast<std::chrono::nanoseconds>(std::chrono::high_resolution_clock::now().time_since_epoch()).count();
+}
 
 }
 

Components/1770/1770.cpp

@@ -7,35 +7,39 @@
 //
 
 #include "1770.hpp"
+
 #include "../../Storage/Disk/Encodings/MFM/Constants.hpp"
 
+#define LOG_PREFIX "[WD FDC] "
+#include "../../Outputs/Log.hpp"
+
 using namespace WD;
 
 WD1770::WD1770(Personality p) :
 		Storage::Disk::MFMController(8000000),
 		personality_(p),
-		interesting_event_mask_(static_cast<int>(Event1770::Command)) {
+		interesting_event_mask_(int(Event1770::Command)) {
 	set_is_double_density(false);
-	posit_event(static_cast<int>(Event1770::Command));
+	posit_event(int(Event1770::Command));
 }
 
-void WD1770::set_register(int address, uint8_t value) {
+void WD1770::write(int address, uint8_t value) {
 	switch(address&3) {
 		case 0: {
 			if((value&0xf0) == 0xd0) {
 				if(value == 0xd0) {
 					// Force interrupt **immediately**.
-					printf("Force interrupt immediately\n");
-					posit_event(static_cast<int>(Event1770::ForceInterrupt));
+					LOG("Force interrupt immediately");
+					posit_event(int(Event1770::ForceInterrupt));
 				} else {
-					printf("!!!TODO: force interrupt!!!\n");
+					ERROR("!!!TODO: force interrupt!!!");
 					update_status([] (Status &status) {
 						status.type = Status::One;
 					});
 				}
 			} else {
 				command_ = value;
-				posit_event(static_cast<int>(Event1770::Command));
+				posit_event(int(Event1770::Command));
 			}
 		}
 		break;
@@ -50,27 +54,35 @@ void WD1770::set_register(int address, uint8_t value) {
 	}
 }
 
-uint8_t WD1770::get_register(int address) {
+uint8_t WD1770::read(int address) {
 	switch(address&3) {
 		default: {
 			update_status([] (Status &status) {
 				status.interrupt_request = false;
 			});
 			uint8_t status =
-					(status_.write_protect ? Flag::WriteProtect : 0) |
-					(status_.crc_error ? Flag::CRCError : 0) |
-					(status_.busy ? Flag::Busy : 0);
+				(status_.crc_error ? Flag::CRCError : 0) |
+				(status_.busy ? Flag::Busy : 0);
+
+			// Per Jean Louis-Guérin's documentation:
+			//
+			//	* 	the write-protect bit is locked into place by a type 2 or type 3 command, but is
+			//		read live after a type 1.
+			//	*	the track 0 bit is captured during a type 1 instruction and lost upon any other type,
+			//		it is not live sampled.
 			switch(status_.type) {
 				case Status::One:
 					status |=
-						(get_drive().get_is_track_zero() ? Flag::TrackZero : 0) |
-						(status_.seek_error ? Flag::SeekError : 0);
-						// TODO: index hole
+						(status_.track_zero ? Flag::TrackZero : 0) |
+						(status_.seek_error ? Flag::SeekError : 0) |
+						(get_drive().get_is_read_only() ? Flag::WriteProtect : 0) |
+						(get_drive().get_index_pulse() ? Flag::Index : 0);
 				break;
 
 				case Status::Two:
 				case Status::Three:
 					status |=
+						(status_.write_protect ? Flag::WriteProtect : 0) |
 						(status_.record_type ? Flag::RecordType : 0) |
 						(status_.lost_data ? Flag::LostData : 0) |
 						(status_.data_request ? Flag::DataRequest : 0) |
@@ -87,10 +99,15 @@ uint8_t WD1770::get_register(int address) {
 				if(status_.type == Status::One)
 					status |= (status_.spin_up ? Flag::SpinUp : 0);
 			}
+//			LOG("Returned status " << PADHEX(2) << int(status) << " of type " << 1+int(status_.type));
 			return status;
 		}
-		case 1:		return track_;
-		case 2:		return sector_;
+		case 1:
+			LOG("Returned track " << int(track_));
+			return track_;
+		case 2:
+			LOG("Returned sector " << int(sector_));
+			return sector_;
 		case 3:
 			update_status([] (Status &status) {
 				status.data_request = false;
@@ -103,28 +120,30 @@ void WD1770::run_for(const Cycles cycles) {
 	Storage::Disk::Controller::run_for(cycles);
 
 	if(delay_time_) {
-		unsigned int number_of_cycles = static_cast<unsigned int>(cycles.as_int());
+		const auto number_of_cycles = cycles.as_integral();
 		if(delay_time_ <= number_of_cycles) {
 			delay_time_ = 0;
-			posit_event(static_cast<int>(Event1770::Timer));
+			posit_event(int(Event1770::Timer));
 		} else {
 			delay_time_ -= number_of_cycles;
 		}
 	}
 }
 
-#define WAIT_FOR_EVENT(mask)	resume_point_ = __LINE__; interesting_event_mask_ = static_cast<int>(mask); return; case __LINE__:
+#define WAIT_FOR_EVENT(mask)	resume_point_ = __LINE__; interesting_event_mask_ = int(mask); return; case __LINE__:
 #define WAIT_FOR_TIME(ms)		resume_point_ = __LINE__; delay_time_ = ms * 8000; WAIT_FOR_EVENT(Event1770::Timer);
-#define WAIT_FOR_BYTES(count)	resume_point_ = __LINE__; distance_into_section_ = 0; WAIT_FOR_EVENT(Event::Token); if(get_latest_token().type == Token::Byte) distance_into_section_++; if(distance_into_section_ < count) { interesting_event_mask_ = static_cast<int>(Event::Token); return; }
+#define WAIT_FOR_BYTES(count)	resume_point_ = __LINE__; distance_into_section_ = 0; WAIT_FOR_EVENT(Event::Token); if(get_latest_token().type == Token::Byte) distance_into_section_++; if(distance_into_section_ < count) { interesting_event_mask_ = int(Event::Token); return; }
 #define BEGIN_SECTION()	switch(resume_point_) { default:
 #define END_SECTION()	(void)0; }
 
 #define READ_ID()	\
-		if(new_event_type == static_cast<int>(Event::Token)) {	\
-			if(!distance_into_section_ && get_latest_token().type == Token::ID) {set_data_mode(DataMode::Reading); distance_into_section_++; }	\
-			else if(distance_into_section_ && distance_into_section_ < 7 && get_latest_token().type == Token::Byte) {	\
+		if(new_event_type == int(Event::Token)) {	\
+			if(!distance_into_section_ && get_latest_token().type == Token::ID) {\
+				set_data_mode(DataMode::Reading);	\
+				++distance_into_section_;	\
+			} else if(distance_into_section_ && distance_into_section_ < 7 && get_latest_token().type == Token::Byte) {	\
 				header_[distance_into_section_ - 1] = get_latest_token().byte_value;	\
-				distance_into_section_++;	\
+				++distance_into_section_;	\
 			}	\
 		}
 
@@ -139,28 +158,28 @@ void WD1770::run_for(const Cycles cycles) {
 		WAIT_FOR_EVENT(Event1770::IndexHoleTarget);	\
 		status_.spin_up = true;
 
-//     +--------+----------+-------------------------+
-//     !	    !	       !          BITS           !
-//     ! TYPE   ! COMMAND  !  7  6	5  4  3  2  1  0 !
-//     +--------+----------+-------------------------+
-//     !	 1  ! Restore  !  0  0	0  0  h  v r1 r0 !
-//     !	 1  ! Seek     !  0  0	0  1  h  v r1 r0 !
-//     !	 1  ! Step     !  0  0	1  u  h  v r1 r0 !
-//     !	 1  ! Step-in  !  0  1	0  u  h  v r1 r0 !
-//     !	 1  ! Step-out !  0  1	1  u  h  v r1 r0 !
-//     !	 2  ! Rd sectr !  1  0	0  m  h  E  0  0 !
-//     !	 2  ! Wt sectr !  1  0	1  m  h  E  P a0 !
-//     !	 3  ! Rd addr  !  1  1	0  0  h  E  0  0 !
-//     !	 3  ! Rd track !  1  1	1  0  h  E  0  0 !
-//     !	 3  ! Wt track !  1  1	1  1  h  E  P  0 !
-//     !	 4  ! Forc int !  1  1	0  1 i3 i2 i1 i0 !
-//     +--------+----------+-------------------------+
+// +--------+----------+-------------------------+
+// !	    !	       !          BITS           !
+// ! TYPE   ! COMMAND  !  7  6	5  4  3  2  1  0 !
+// +--------+----------+-------------------------+
+// !	 1  ! Restore  !  0  0	0  0  h  v r1 r0 !
+// !	 1  ! Seek     !  0  0	0  1  h  v r1 r0 !
+// !	 1  ! Step     !  0  0	1  u  h  v r1 r0 !
+// !	 1  ! Step-in  !  0  1	0  u  h  v r1 r0 !
+// !	 1  ! Step-out !  0  1	1  u  h  v r1 r0 !
+// !	 2  ! Rd sectr !  1  0	0  m  h  E  0  0 !
+// !	 2  ! Wt sectr !  1  0	1  m  h  E  P a0 !
+// !	 3  ! Rd addr  !  1  1	0  0  h  E  0  0 !
+// !	 3  ! Rd track !  1  1	1  0  h  E  0  0 !
+// !	 3  ! Wt track !  1  1	1  1  h  E  P  0 !
+// !	 4  ! Forc int !  1  1	0  1 i3 i2 i1 i0 !
+// +--------+----------+-------------------------+
 
 void WD1770::posit_event(int new_event_type) {
-	if(new_event_type == static_cast<int>(Event::IndexHole)) {
+	if(new_event_type == int(Event::IndexHole)) {
 		index_hole_count_++;
 		if(index_hole_count_target_ == index_hole_count_) {
-			posit_event(static_cast<int>(Event1770::IndexHoleTarget));
+			posit_event(int(Event1770::IndexHoleTarget));
 			index_hole_count_target_ = -1;
 		}
 
@@ -175,25 +194,25 @@ void WD1770::posit_event(int new_event_type) {
 		}
 	}
 
-	if(new_event_type == static_cast<int>(Event1770::ForceInterrupt)) {
+	if(new_event_type == int(Event1770::ForceInterrupt)) {
 		interesting_event_mask_ = 0;
 		resume_point_ = 0;
 		update_status([] (Status &status) {
 			status.type = Status::One;
 			status.data_request = false;
+			status.spin_up = false;
 		});
 	} else {
-		if(!(interesting_event_mask_ & static_cast<int>(new_event_type))) return;
+		if(!(interesting_event_mask_ & int(new_event_type))) return;
 		interesting_event_mask_ &= ~new_event_type;
 	}
 
-	Status new_status;
 	BEGIN_SECTION()
 
 	// Wait for a new command, branch to the appropriate handler.
 	case 0:
 	wait_for_command:
-		printf("Idle...\n");
+		LOG("Idle...");
 		set_data_mode(DataMode::Scanning);
 		index_hole_count_ = 0;
 
@@ -207,9 +226,10 @@ void WD1770::posit_event(int new_event_type) {
 		update_status([] (Status &status) {
 			status.busy = true;
 			status.interrupt_request = false;
+			status.track_zero = false;	// Always reset by a non-type 1; so reset regardless and set properly later.
 		});
 
-		printf("Starting %02x\n", command_);
+		LOG("Starting " << PADHEX(2) << int(command_));
 
 		if(!(command_ & 0x80)) goto begin_type_1;
 		if(!(command_ & 0x40)) goto begin_type_2;
@@ -219,16 +239,16 @@ void WD1770::posit_event(int new_event_type) {
 	/*
 		Type 1 entry point.
 	*/
-//     +--------+----------+-------------------------+
-//     !	    !	       !          BITS           !
-//     ! TYPE   ! COMMAND  !  7  6	5  4  3  2  1  0 !
-//     +--------+----------+-------------------------+
-//     !	 1  ! Restore  !  0  0	0  0  h  v r1 r0 !
-//     !	 1  ! Seek     !  0  0	0  1  h  v r1 r0 !
-//     !	 1  ! Step     !  0  0	1  u  h  v r1 r0 !
-//     !	 1  ! Step-in  !  0  1	0  u  h  v r1 r0 !
-//     !	 1  ! Step-out !  0  1	1  u  h  v r1 r0 !
-//     +--------+----------+-------------------------+
+	// +--------+----------+-------------------------+
+	// !	    !	       !          BITS           !
+	// ! TYPE   ! COMMAND  !  7  6	5  4  3  2  1  0 !
+	// +--------+----------+-------------------------+
+	// !	 1  ! Restore  !  0  0	0  0  h  v r1 r0 !
+	// !	 1  ! Seek     !  0  0	0  1  h  v r1 r0 !
+	// !	 1  ! Step     !  0  0	1  u  h  v r1 r0 !
+	// !	 1  ! Step-in  !  0  1	0  u  h  v r1 r0 !
+	// !	 1  ! Step-out !  0  1	1  u  h  v r1 r0 !
+	// +--------+----------+-------------------------+
 
 	begin_type_1:
 		// Set initial flags, skip spin-up if possible.
@@ -239,6 +259,7 @@ void WD1770::posit_event(int new_event_type) {
 			status.data_request = false;
 		});
 
+		LOG("Step/Seek/Restore with track " << int(track_) << " data " << int(data_));
 		if(!has_motor_on_line() && !has_head_load_line()) goto test_type1_type;
 
 		if(has_motor_on_line()) goto begin_type1_spin_up;
@@ -271,19 +292,19 @@ void WD1770::posit_event(int new_event_type) {
 		}
 
 	perform_seek_or_restore_command:
-		if(track_ == data_) goto verify;
+		if(track_ == data_) goto verify_seek;
 		step_direction_ = (data_ > track_);
 
 	adjust_track:
-		if(step_direction_) track_++; else track_--;
+		if(step_direction_) ++track_; else --track_;
 
 	perform_step:
 		if(!step_direction_ && get_drive().get_is_track_zero()) {
 			track_ = 0;
-			goto verify;
+			goto verify_seek;
 		}
 		get_drive().step(Storage::Disk::HeadPosition(step_direction_ ? 1 : -1));
-		unsigned int time_to_wait;
+		Cycles::IntType time_to_wait;
 		switch(command_ & 3) {
 			default:
 			case 0: time_to_wait = 6;	break;
@@ -292,14 +313,17 @@ void WD1770::posit_event(int new_event_type) {
 			case 3: time_to_wait = (personality_ == P1772) ? 3 : 30;	break;
 		}
 		WAIT_FOR_TIME(time_to_wait);
-		if(command_ >> 5) goto verify;
+		if(command_ >> 5) goto verify_seek;
 		goto perform_seek_or_restore_command;
 
 	perform_step_command:
 		if(command_ & 0x10) goto adjust_track;
 		goto perform_step;
 
-	verify:
+	verify_seek:
+		update_status([this] (Status &status) {
+			status.track_zero = get_drive().get_is_track_zero();
+		});
 		if(!(command_ & 0x04)) {
 			goto wait_for_command;
 		}
@@ -308,17 +332,20 @@ void WD1770::posit_event(int new_event_type) {
 		distance_into_section_ = 0;
 
 	verify_read_data:
-		WAIT_FOR_EVENT(static_cast<int>(Event::IndexHole) | static_cast<int>(Event::Token));
+		WAIT_FOR_EVENT(int(Event::IndexHole) | int(Event::Token));
 		READ_ID();
 
 		if(index_hole_count_ == 6) {
+			LOG("Nothing found to verify");
 			update_status([] (Status &status) {
 				status.seek_error = true;
 			});
 			goto wait_for_command;
 		}
 		if(distance_into_section_ == 7) {
+			distance_into_section_ = 0;
 			set_data_mode(DataMode::Scanning);
+
 			if(get_crc_generator().get_value()) {
 				update_status([] (Status &status) {
 					status.crc_error = true;
@@ -327,14 +354,12 @@ void WD1770::posit_event(int new_event_type) {
 			}
 
 			if(header_[0] == track_) {
-				printf("Reached track %d\n", track_);
+				LOG("Reached track " << std::dec << int(track_));
 				update_status([] (Status &status) {
 					status.crc_error = false;
 				});
 				goto wait_for_command;
 			}
-
-			distance_into_section_ = 0;
 		}
 		goto verify_read_data;
 
@@ -342,13 +367,13 @@ void WD1770::posit_event(int new_event_type) {
 	/*
 		Type 2 entry point.
 	*/
-//     +--------+----------+-------------------------+
-//     !	    !	       !          BITS           !
-//     ! TYPE   ! COMMAND  !  7  6	5  4  3  2  1  0 !
-//     +--------+----------+-------------------------+
-//     !	 2  ! Rd sectr !  1  0	0  m  h  E  0  0 !
-//     !	 2  ! Wt sectr !  1  0	1  m  h  E  P a0 !
-//     +--------+----------+-------------------------+
+	// +--------+----------+-------------------------+
+	// !	    !	       !          BITS           !
+	// ! TYPE   ! COMMAND  !  7  6	5  4  3  2  1  0 !
+	// +--------+----------+-------------------------+
+	// !	 2  ! Rd sectr !  1  0	0  m  h  E  0  0 !
+	// !	 2  ! Wt sectr !  1  0	1  m  h  E  P a0 !
+	// +--------+----------+-------------------------+
 
 	begin_type_2:
 		update_status([] (Status &status) {
@@ -391,25 +416,30 @@ void WD1770::posit_event(int new_event_type) {
 			goto wait_for_command;
 		}
 
+		distance_into_section_ = 0;
+		set_data_mode(DataMode::Scanning);
+
 	type2_get_header:
-		WAIT_FOR_EVENT(static_cast<int>(Event::IndexHole) | static_cast<int>(Event::Token));
+		WAIT_FOR_EVENT(int(Event::IndexHole) | int(Event::Token));
 		READ_ID();
 
 		if(index_hole_count_ == 5) {
-			printf("Failed to find sector %d\n", sector_);
+			LOG("Failed to find sector " << std::dec << int(sector_));
 			update_status([] (Status &status) {
 				status.record_not_found = true;
 			});
 			goto wait_for_command;
 		}
 		if(distance_into_section_ == 7) {
-			printf("Considering %d/%d\n", header_[0], header_[2]);
+			distance_into_section_ = 0;
 			set_data_mode(DataMode::Scanning);
+
+			LOG("Considering " << std::dec << int(header_[0]) << "/" << int(header_[2]));
 			if(		header_[0] == track_ && header_[2] == sector_ &&
 					(has_motor_on_line() || !(command_&0x02) || ((command_&0x08) >> 3) == header_[1])) {
-				printf("Found %d/%d\n", header_[0], header_[2]);
+				LOG("Found " << std::dec << int(header_[0]) << "/" << int(header_[2]));
 				if(get_crc_generator().get_value()) {
-					printf("CRC error; back to searching\n");
+					LOG("CRC error; back to searching");
 					update_status([] (Status &status) {
 						status.crc_error = true;
 					});
@@ -421,7 +451,6 @@ void WD1770::posit_event(int new_event_type) {
 				});
 				goto type2_read_or_write_data;
 			}
-			distance_into_section_ = 0;
 		}
 		goto type2_get_header;
 
@@ -452,7 +481,7 @@ void WD1770::posit_event(int new_event_type) {
 			status.data_request = true;
 		});
 		distance_into_section_++;
-		if(distance_into_section_ == 128 << header_[3]) {
+		if(distance_into_section_ == 128 << (header_[3]&3)) {
 			distance_into_section_ = 0;
 			goto type2_check_crc;
 		}
@@ -464,19 +493,24 @@ void WD1770::posit_event(int new_event_type) {
 		header_[distance_into_section_] = get_latest_token().byte_value;
 		distance_into_section_++;
 		if(distance_into_section_ == 2) {
+			distance_into_section_ = 0;
+			set_data_mode(DataMode::Scanning);
+
 			if(get_crc_generator().get_value()) {
-				printf("CRC error; terminating\n");
+				LOG("CRC error; terminating");
 				update_status([this] (Status &status) {
 					status.crc_error = true;
 				});
 				goto wait_for_command;
 			}
 
+			LOG("Finished reading sector " << std::dec << int(sector_));
+
 			if(command_ & 0x10) {
 				sector_++;
+				LOG("Advancing to search for sector " << std::dec << int(sector_));
 				goto test_type2_write_protection;
 			}
-			printf("Finished reading sector %d\n", sector_);
 			goto wait_for_command;
 		}
 		goto type2_check_crc;
@@ -530,7 +564,7 @@ void WD1770::posit_event(int new_event_type) {
 		*/
 		write_byte(data_);
 		distance_into_section_++;
-		if(distance_into_section_ == 128 << header_[3]) {
+		if(distance_into_section_ == 128 << (header_[3]&3)) {
 			goto type2_write_crc;
 		}
 
@@ -558,21 +592,21 @@ void WD1770::posit_event(int new_event_type) {
 			sector_++;
 			goto test_type2_write_protection;
 		}
-		printf("Wrote sector %d\n", sector_);
+		LOG("Wrote sector " << std::dec << int(sector_));
 		goto wait_for_command;
 
 
 	/*
 		Type 3 entry point.
 	*/
-//     +--------+----------+-------------------------+
-//     !	    !	       !          BITS           !
-//     ! TYPE   ! COMMAND  !  7  6	5  4  3  2  1  0 !
-//     +--------+----------+-------------------------+
-//     !	 3  ! Rd addr  !  1  1	0  0  h  E  0  0 !
-//     !	 3  ! Rd track !  1  1	1  0  h  E  0  0 !
-//     !	 3  ! Wt track !  1  1	1  1  h  E  P  0 !
-//     +--------+----------+-------------------------+
+	// +--------+----------+-------------------------+
+	// !	    !	       !          BITS           !
+	// ! TYPE   ! COMMAND  !  7  6	5  4  3  2  1  0 !
+	// +--------+----------+-------------------------+
+	// !	 3  ! Rd addr  !  1  1	0  0  h  E  0  0 !
+	// !	 3  ! Rd track !  1  1	1  0  h  E  0  0 !
+	// !	 3  ! Wt track !  1  1	1  1  h  E  P  0 !
+	// +--------+----------+-------------------------+
 	begin_type_3:
 		update_status([] (Status &status) {
 			status.type = Status::Three;
@@ -609,8 +643,8 @@ void WD1770::posit_event(int new_event_type) {
 		distance_into_section_ = 0;
 
 	read_address_get_header:
-		WAIT_FOR_EVENT(static_cast<int>(Event::IndexHole) | static_cast<int>(Event::Token));
-		if(new_event_type == static_cast<int>(Event::Token)) {
+		WAIT_FOR_EVENT(int(Event::IndexHole) | int(Event::Token));
+		if(new_event_type == int(Event::Token)) {
 			if(!distance_into_section_ && get_latest_token().type == Token::ID) {set_data_mode(DataMode::Reading); distance_into_section_++; }
 			else if(distance_into_section_ && distance_into_section_ < 7 && get_latest_token().type == Token::Byte) {
 				if(status_.data_request) {
@@ -624,9 +658,11 @@ void WD1770::posit_event(int new_event_type) {
 				update_status([] (Status &status) {
 					status.data_request = true;
 				});
-				distance_into_section_++;
+				++distance_into_section_;
 
 				if(distance_into_section_ == 7) {
+					distance_into_section_ = 0;
+
 					if(get_crc_generator().get_value()) {
 						update_status([] (Status &status) {
 							status.crc_error = true;
@@ -650,7 +686,7 @@ void WD1770::posit_event(int new_event_type) {
 		index_hole_count_ = 0;
 
 	read_track_read_byte:
-		WAIT_FOR_EVENT(static_cast<int>(Event::Token) | static_cast<int>(Event::IndexHole));
+		WAIT_FOR_EVENT(int(Event::Token) | int(Event::IndexHole));
 		if(index_hole_count_) {
 			goto wait_for_command;
 		}
@@ -717,7 +753,7 @@ void WD1770::posit_event(int new_event_type) {
 				case 0xfd: case 0xfe:
 					// clock is 0xc7 = 1010 0000 0010 1010 = 0xa022
 					write_raw_short(
-						static_cast<uint16_t>(
+						uint16_t(
 							0xa022 |
 							((data_ & 0x80) << 7) |
 							((data_ & 0x40) << 6) |
@@ -766,15 +802,18 @@ void WD1770::posit_event(int new_event_type) {
 }
 
 void WD1770::update_status(std::function<void(Status &)> updater) {
+	const Status old_status = status_;
+
 	if(delegate_) {
-		Status old_status = status_;
 		updater(status_);
-		bool did_change =
+		const bool did_change =
 			(status_.busy != old_status.busy) ||
-			(status_.data_request != old_status.data_request);
+			(status_.data_request != old_status.data_request) ||
+			(status_.interrupt_request != old_status.interrupt_request);
 		if(did_change) delegate_->wd1770_did_change_output(this);
-	}
-	else updater(status_);
+	} else updater(status_);
+
+	if(status_.busy != old_status.busy) update_clocking_observer();
 }
 
 void WD1770::set_head_load_request(bool head_load) {}
@@ -782,5 +821,14 @@ void WD1770::set_motor_on(bool motor_on) {}
 
 void WD1770::set_head_loaded(bool head_loaded) {
 	head_is_loaded_ = head_loaded;
-	if(head_loaded) posit_event(static_cast<int>(Event1770::HeadLoad));
+	if(head_loaded) posit_event(int(Event1770::HeadLoad));
+}
+
+bool WD1770::get_head_loaded() {
+	return head_is_loaded_;
+}
+
+ClockingHint::Preference WD1770::preferred_clocking() {
+	if(status_.busy) return ClockingHint::Preference::RealTime;
+	return Storage::Disk::MFMController::preferred_clocking();
 }

Components/1770/1770.hpp

@@ -36,30 +36,29 @@ class WD1770: public Storage::Disk::MFMController {
 		using Storage::Disk::MFMController::set_is_double_density;
 
 		/// Writes @c value to the register at @c address. Only the low two bits of the address are decoded.
-		void set_register(int address, uint8_t value);
+		void write(int address, uint8_t value);
 
 		/// Fetches the value of the register @c address. Only the low two bits of the address are decoded.
-		uint8_t get_register(int address);
+		uint8_t read(int address);
 
 		/// Runs the controller for @c number_of_cycles cycles.
 		void run_for(const Cycles cycles);
-		using Storage::Disk::Controller::run_for;
 
 		enum Flag: uint8_t {
-			NotReady		= 0x80,
+			NotReady		= 0x80,		// 0x80
 			MotorOn			= 0x80,
-			WriteProtect	= 0x40,
-			RecordType		= 0x20,
+			WriteProtect	= 0x40,		// 0x40
+			RecordType		= 0x20,		// 0x20
 			SpinUp			= 0x20,
 			HeadLoaded		= 0x20,
-			RecordNotFound	= 0x10,
+			RecordNotFound	= 0x10,		// 0x10
 			SeekError		= 0x10,
-			CRCError		= 0x08,
-			LostData		= 0x04,
+			CRCError		= 0x08,		// 0x08
+			LostData		= 0x04,		// 0x04
 			TrackZero		= 0x04,
-			DataRequest		= 0x02,
+			DataRequest		= 0x02,		// 0x02
 			Index			= 0x02,
-			Busy			= 0x01
+			Busy			= 0x01		// 0x01
 		};
 
 		/// @returns The current value of the IRQ line output.
@@ -74,11 +73,16 @@ class WD1770: public Storage::Disk::MFMController {
 		};
 		inline void set_delegate(Delegate *delegate)	{	delegate_ = delegate;			}
 
+		ClockingHint::Preference preferred_clocking() final;
+
 	protected:
 		virtual void set_head_load_request(bool head_load);
 		virtual void set_motor_on(bool motor_on);
 		void set_head_loaded(bool head_loaded);
 
+		/// @returns The last value posted to @c set_head_loaded.
+		bool get_head_loaded();
+
 	private:
 		Personality personality_;
 		inline bool has_motor_on_line() { return (personality_ != P1793 ) && (personality_ != P1773); }
@@ -95,6 +99,7 @@ class WD1770: public Storage::Disk::MFMController {
 			bool data_request = false;
 			bool interrupt_request = false;
 			bool busy = false;
+			bool track_zero = false;
 			enum {
 				One, Two, Three
 			} type = One;
@@ -122,7 +127,7 @@ class WD1770: public Storage::Disk::MFMController {
 		void posit_event(int type);
 		int interesting_event_mask_;
 		int resume_point_ = 0;
-		unsigned int delay_time_ = 0;
+		Cycles::IntType delay_time_ = 0;
 
 		// ID buffer
 		uint8_t header_[6];

Components/5380/ncr5380.cpp

@@ -0,0 +1,312 @@
+//
+//  ncr5380.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 10/08/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#include "ncr5380.hpp"
+
+#include "../../Outputs/Log.hpp"
+
+using namespace NCR::NCR5380;
+using SCSI::Line;
+
+NCR5380::NCR5380(SCSI::Bus &bus, int clock_rate) :
+	bus_(bus),
+	clock_rate_(clock_rate) {
+	device_id_ = bus_.add_device();
+	bus_.add_observer(this);
+}
+
+void NCR5380::write(int address, uint8_t value, bool dma_acknowledge) {
+	switch(address & 7) {
+		case 0:
+//			LOG("[SCSI 0] Set current SCSI bus state to " << PADHEX(2) << int(value));
+			data_bus_ = value;
+
+			if(dma_request_ && dma_operation_ == DMAOperation::Send) {
+//				printf("w %02x\n", value);
+				dma_acknowledge_ = true;
+				dma_request_ = false;
+				update_control_output();
+				bus_.set_device_output(device_id_, bus_output_);
+			}
+		break;
+
+		case 1: {
+//			LOG("[SCSI 1] Initiator command register set: " << PADHEX(2) << int(value));
+			initiator_command_ = value;
+
+			bus_output_ &= ~(Line::Reset | Line::Acknowledge | Line::Busy | Line::SelectTarget | Line::Attention);
+			if(value & 0x80) bus_output_ |= Line::Reset;
+			if(value & 0x08) bus_output_ |= Line::Busy;
+			if(value & 0x04) bus_output_ |= Line::SelectTarget;
+
+			/* bit 5 = differential enable if this were a 5381 */
+
+			test_mode_ = value & 0x40;
+			assert_data_bus_ = value & 0x01;
+			update_control_output();
+		} break;
+
+		case 2:
+//			LOG("[SCSI 2] Set mode: " << PADHEX(2) << int(value));
+			mode_ = value;
+
+			// bit 7: 1 = use block mode DMA mode (if DMA mode is also enabled)
+			// bit 6: 1 = be a SCSI target; 0 = be an initiator
+			// bit 5: 1 = check parity
+			// bit 4: 1 = generate an interrupt if parity checking is enabled and an error is found
+			// bit 3: 1 = generate an interrupt when an EOP is received from the DMA controller
+			// bit 2: 1 = generate an interrupt and reset low 6 bits of register 1 if an unexpected loss of Line::Busy occurs
+			// bit 1: 1 = use DMA mode
+			// bit 0: 1 = begin arbitration mode (device ID should be in register 0)
+			arbitration_in_progress_ = false;
+			switch(mode_ & 0x3) {
+				case 0x0:
+					bus_output_ &= ~SCSI::Line::Busy;
+					dma_request_ = false;
+					set_execution_state(ExecutionState::None);
+				break;
+
+				case 0x1:
+					arbitration_in_progress_ = true;
+					set_execution_state(ExecutionState::WaitingForBusy);
+					lost_arbitration_ = false;
+				break;
+
+				default:
+					assert_data_bus_ = false;
+					set_execution_state(ExecutionState::PerformingDMA);
+					bus_.update_observers();
+				break;
+			}
+			update_control_output();
+		break;
+
+		case 3: {
+//			LOG("[SCSI 3] Set target command: " << PADHEX(2) << int(value));
+			target_command_ = value;
+			update_control_output();
+		} break;
+
+		case 4:
+//			LOG("[SCSI 4] Set select enabled: " << PADHEX(2) << int(value));
+		break;
+
+		case 5:
+//			LOG("[SCSI 5] Start DMA send: " << PADHEX(2) << int(value));
+			dma_operation_ = DMAOperation::Send;
+		break;
+
+		case 6:
+//			LOG("[SCSI 6] Start DMA target receive: " << PADHEX(2) << int(value));
+			dma_operation_ = DMAOperation::TargetReceive;
+		break;
+
+		case 7:
+//			LOG("[SCSI 7] Start DMA initiator receive: " << PADHEX(2) << int(value));
+			dma_operation_ = DMAOperation::InitiatorReceive;
+		break;
+	}
+
+	// Data is output only if the data bus is asserted.
+	if(assert_data_bus_) {
+		bus_output_ = (bus_output_ & ~SCSI::Line::Data) | data_bus_;
+	} else {
+		bus_output_ &= ~SCSI::Line::Data;
+	}
+
+	// In test mode, still nothing is output. Otherwise throw out
+	// the current value of bus_output_.
+	if(test_mode_) {
+		bus_.set_device_output(device_id_, SCSI::DefaultBusState);
+	} else {
+		bus_.set_device_output(device_id_, bus_output_);
+	}
+}
+
+uint8_t NCR5380::read(int address, bool dma_acknowledge) {
+	switch(address & 7) {
+		case 0:
+//			LOG("[SCSI 0] Get current SCSI bus state: " << PADHEX(2) << (bus_.get_state() & 0xff));
+
+			if(dma_request_ && dma_operation_ == DMAOperation::InitiatorReceive) {
+				dma_acknowledge_ = true;
+				dma_request_ = false;
+				update_control_output();
+				bus_.set_device_output(device_id_, bus_output_);
+			}
+		return uint8_t(bus_.get_state());
+
+		case 1:
+//			LOG("[SCSI 1] Initiator command register get: " << (arbitration_in_progress_ ? 'p' : '-') <<  (lost_arbitration_ ? 'l' : '-'));
+		return
+			// Bits repeated as they were set.
+			(initiator_command_ & ~0x60) |
+
+			// Arbitration in progress.
+			(arbitration_in_progress_ ? 0x40 : 0x00) |
+
+			// Lost arbitration.
+			(lost_arbitration_ ? 0x20 : 0x00);
+
+		case 2:
+//			LOG("[SCSI 2] Get mode");
+		return mode_;
+
+		case 3:
+//			LOG("[SCSI 3] Get target command");
+		return target_command_;
+
+		case 4: {
+			const auto bus_state = bus_.get_state();
+			const uint8_t result =
+				((bus_state & Line::Reset)			? 0x80 : 0x00) |
+				((bus_state & Line::Busy)			? 0x40 : 0x00) |
+				((bus_state & Line::Request)		? 0x20 : 0x00) |
+				((bus_state & Line::Message)		? 0x10 : 0x00) |
+				((bus_state & Line::Control)		? 0x08 : 0x00) |
+				((bus_state & Line::Input)			? 0x04 : 0x00) |
+				((bus_state & Line::SelectTarget)	? 0x02 : 0x00) |
+				((bus_state & Line::Parity)			? 0x01 : 0x00);
+//			LOG("[SCSI 4] Get current bus state: " << PADHEX(2) << int(result));
+			return result;
+		}
+
+		case 5: {
+			const auto bus_state = bus_.get_state();
+			const bool phase_matches =
+				(target_output() & (Line::Message | Line::Control | Line::Input)) ==
+				(bus_state & (Line::Message | Line::Control | Line::Input));
+
+			const uint8_t result =
+				/* b7 = end of DMA */
+				((dma_request_ && state_ == ExecutionState::PerformingDMA) ? 0x40 : 0x00)	|
+				/* b5 = parity error */
+				/* b4 = IRQ active */
+				(phase_matches ? 0x08 : 0x00)	|
+				/* b2 = busy error */
+				((bus_state & Line::Attention) ? 0x02 : 0x00) |
+				((bus_state & Line::Acknowledge) ? 0x01 : 0x00);
+//			LOG("[SCSI 5] Get bus and status: " << PADHEX(2) << int(result));
+			return result;
+		}
+
+		case 6:
+//			LOG("[SCSI 6] Get input data");
+		return 0xff;
+
+		case 7:
+//			LOG("[SCSI 7] Reset parity/interrupt");
+		return 0xff;
+	}
+	return 0;
+}
+
+SCSI::BusState NCR5380::target_output() {
+	SCSI::BusState output = SCSI::DefaultBusState;
+	if(target_command_ & 0x08) output |= Line::Request;
+	if(target_command_ & 0x04) output |= Line::Message;
+	if(target_command_ & 0x02) output |= Line::Control;
+	if(target_command_ & 0x01) output |= Line::Input;
+	return output;
+}
+
+void NCR5380::update_control_output() {
+	bus_output_ &= ~(Line::Request | Line::Message | Line::Control | Line::Input | Line::Acknowledge | Line::Attention);
+	if(mode_ & 0x40) {
+		// This is a target; C/D, I/O, /MSG and /REQ are signalled on the bus.
+		bus_output_ |= target_output();
+	} else {
+		// This is an initiator; /ATN and /ACK are signalled on the bus.
+		if(
+			(initiator_command_ & 0x10) ||
+			(state_ == ExecutionState::PerformingDMA && dma_acknowledge_)
+		) bus_output_ |= Line::Acknowledge;
+		if(initiator_command_ & 0x02) bus_output_ |= Line::Attention;
+	}
+}
+
+void NCR5380::scsi_bus_did_change(SCSI::Bus *, SCSI::BusState new_state, double time_since_change) {
+	switch(state_) {
+		default: break;
+
+		/*
+			Official documentation:
+
+				Arbitration is accomplished using a bus-free filter to continuously monitor BSY.
+				If BSY remains inactive for at least 400 nsec then the SCSI bus is considered free
+				and arbitration may begin. Arbitration will begin if the bus is free, SEL is inactive
+				and the ARBITRATION bit (port 2, bit 0) is active. Once arbitration has begun
+				(BSY asserted), an arbitration delay of 2.2 /Lsec must elapse before the data bus
+				can be examined to deter- mine if arbitration has been won. This delay must be
+				implemented in the controlling software driver.
+
+			Personal notes:
+
+				I'm discounting that "arbitratation is accomplished" opening, and assuming that what needs
+				to happen is:
+
+					(i) wait for BSY to be inactive;
+					(ii) count 400 nsec;
+					(iii) check that BSY and SEL are inactive.
+		*/
+
+		case ExecutionState::WaitingForBusy:
+			if(!(new_state & SCSI::Line::Busy) || time_since_change < SCSI::DeskewDelay) return;
+			state_ = ExecutionState::WatchingBusy;
+
+		case ExecutionState::WatchingBusy:
+			if(!(new_state & SCSI::Line::Busy)) {
+				lost_arbitration_ = true;
+				set_execution_state(ExecutionState::None);
+			}
+
+			// Check for having hit 400ns (more or less) since BSY was inactive.
+			if(time_since_change >= SCSI::BusSettleDelay) {
+//				arbitration_in_progress_ = false;
+				if(new_state & SCSI::Line::SelectTarget) {
+					lost_arbitration_ = true;
+					set_execution_state(ExecutionState::None);
+				} else {
+					bus_output_ &= ~SCSI::Line::Busy;
+					set_execution_state(ExecutionState::None);
+				}
+			}
+
+			/* TODO: there's a bug here, given that the dropping of Busy isn't communicated onward. */
+		break;
+
+		case ExecutionState::PerformingDMA:
+			if(time_since_change < SCSI::DeskewDelay) return;
+
+			// Signal a DMA request if the request line is active, i.e. meaningful data is
+			// on the bus, and this device hasn't yet acknowledged it.
+			switch(new_state & (SCSI::Line::Request | SCSI::Line::Acknowledge)) {
+				case 0:
+					dma_request_ = false;
+				break;
+				case SCSI::Line::Request:
+					dma_request_ = true;
+				break;
+				case SCSI::Line::Request | SCSI::Line::Acknowledge:
+					dma_request_ = false;
+				break;
+				case SCSI::Line::Acknowledge:
+					dma_acknowledge_ = false;
+					dma_request_ = false;
+					update_control_output();
+					bus_.set_device_output(device_id_, bus_output_);
+				break;
+			}
+		break;
+	}
+}
+
+void NCR5380::set_execution_state(ExecutionState state) {
+	state_ = state;
+	if(state != ExecutionState::PerformingDMA) dma_operation_ = DMAOperation::Ready;
+}

Components/5380/ncr5380.hpp

@@ -0,0 +1,75 @@
+//
+//  ncr5380.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 10/08/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef ncr5380_hpp
+#define ncr5380_hpp
+
+#include <cstdint>
+
+#include "../../Storage/MassStorage/SCSI/SCSI.hpp"
+
+
+namespace NCR {
+namespace NCR5380 {
+
+/*!
+	Models the NCR 5380, a SCSI interface chip.
+*/
+class NCR5380 final: public SCSI::Bus::Observer {
+	public:
+		NCR5380(SCSI::Bus &bus, int clock_rate);
+
+		/*! Writes @c value to @c address.  */
+		void write(int address, uint8_t value, bool dma_acknowledge = false);
+
+		/*! Reads from @c address. */
+		uint8_t read(int address, bool dma_acknowledge = false);
+
+	private:
+		SCSI::Bus &bus_;
+
+		const int clock_rate_;
+		size_t device_id_;
+
+		SCSI::BusState bus_output_ = SCSI::DefaultBusState;
+		SCSI::BusState expected_phase_ = SCSI::DefaultBusState;
+		uint8_t mode_ = 0xff;
+		uint8_t initiator_command_ = 0xff;
+		uint8_t data_bus_ = 0xff;
+		uint8_t target_command_ = 0xff;
+		bool test_mode_ = false;
+		bool assert_data_bus_ = false;
+		bool dma_request_ = false;
+		bool dma_acknowledge_ = false;
+
+		enum class ExecutionState {
+			None,
+			WaitingForBusy,
+			WatchingBusy,
+			PerformingDMA,
+		} state_ = ExecutionState::None;
+		enum class DMAOperation {
+			Ready,
+			Send,
+			TargetReceive,
+			InitiatorReceive
+		} dma_operation_ = DMAOperation::Ready;
+		bool lost_arbitration_ = false, arbitration_in_progress_ = false;
+
+		void set_execution_state(ExecutionState state);
+
+		SCSI::BusState target_output();
+		void update_control_output();
+
+		void scsi_bus_did_change(SCSI::Bus *, SCSI::BusState new_state, double time_since_change) final;
+};
+
+}
+}
+
+#endif /* ncr5380_hpp */

Components/6522/6522.hpp

@@ -47,6 +47,12 @@ class PortHandler {
 
 		/// Sets the current logical value of the interrupt line.
 		void set_interrupt_status(bool status)									{}
+
+		/// Provides a measure of time elapsed between other calls.
+		void run_for(HalfCycles duration)										{}
+
+		/// Receives passed-on flush() calls from the 6522.
+		void flush()															{}
 };
 
 /*!
@@ -71,8 +77,31 @@ class IRQDelegatePortHandler: public PortHandler {
 		Delegate *delegate_ = nullptr;
 };
 
-class MOS6522Base: public MOS6522Storage {
+/*!
+	Implements a template for emulation of the MOS 6522 Versatile Interface Adaptor ('VIA').
+
+	The VIA provides:
+		* two timers, each of which may trigger interrupts and one of which may repeat;
+		* two digial input/output ports; and
+		* a serial-to-parallel shifter.
+
+	Consumers should derive their own curiously-recurring-template-pattern subclass,
+	implementing bus communications as required.
+*/
+template <class T> class MOS6522: public MOS6522Storage {
 	public:
+		MOS6522(T &bus_handler) noexcept : bus_handler_(bus_handler) {}
+		MOS6522(const MOS6522 &) = delete;
+
+		/*! Sets a register value. */
+		void write(int address, uint8_t value);
+
+		/*! Gets a register value. */
+		uint8_t read(int address);
+
+		/*! @returns the bus handler. */
+		T &bus_handler();
+
 		/// Sets the input value of line @c line on port @c port.
 		void set_control_line_input(Port port, Line line, bool value);
 
@@ -85,47 +114,32 @@ class MOS6522Base: public MOS6522Storage {
 		/// @returns @c true if the IRQ line is currently active; @c false otherwise.
 		bool get_interrupt_line();
 
-	private:
-		inline void do_phase1();
-		inline void do_phase2();
-		virtual void reevaluate_interrupts() = 0;
-};
-
-/*!
-	Implements a template for emulation of the MOS 6522 Versatile Interface Adaptor ('VIA').
-
-	The VIA provides:
-		* two timers, each of which may trigger interrupts and one of which may repeat;
-		* two digial input/output ports; and
-		* a serial-to-parallel shifter.
-
-	Consumers should derive their own curiously-recurring-template-pattern subclass,
-	implementing bus communications as required.
-*/
-template <class T> class MOS6522: public MOS6522Base {
-	public:
-		MOS6522(T &bus_handler) noexcept : bus_handler_(bus_handler) {}
-		MOS6522(const MOS6522 &) = delete;
-
-		/*! Sets a register value. */
-		void set_register(int address, uint8_t value);
-
-		/*! Gets a register value. */
-		uint8_t get_register(int address);
-
-		/*! @returns the bus handler. */
-		T &bus_handler();
+		/// Updates the port handler to the current time and then requests that it flush.
+		void flush();
 
 	private:
+		void do_phase1();
+		void do_phase2();
+		void shift_in();
+		void shift_out();
+
 		T &bus_handler_;
+		HalfCycles time_since_bus_handler_call_;
+
+		void access(int address);
 
 		uint8_t get_port_input(Port port, uint8_t output_mask, uint8_t output);
 		inline void reevaluate_interrupts();
+
+		/// Sets the current intended output value for the port and line;
+		/// if this affects the visible output, it will be passed to the handler.
+		void set_control_line_output(Port port, Line line, LineState value);
+		void evaluate_cb2_output();
 };
 
+}
+}
+
 #include "Implementation/6522Implementation.hpp"
 
-}
-}
-
 #endif /* _522_hpp */

Components/6522/Implementation/6522Base.cpp

@@ -1,116 +0,0 @@
-//
-//  6522Base.cpp
-//  Clock Signal
-//
-//  Created by Thomas Harte on 04/09/2017.
-//  Copyright 2017 Thomas Harte. All rights reserved.
-//
-
-#include "../6522.hpp"
-
-using namespace MOS::MOS6522;
-
-void MOS6522Base::set_control_line_input(Port port, Line line, bool value) {
-	switch(line) {
-		case Line::One:
-			if(	value != control_inputs_[port].line_one &&
-				value == !!(registers_.peripheral_control & (port ? 0x10 : 0x01))
-			) {
-				registers_.interrupt_flags |= port ? InterruptFlag::CB1ActiveEdge : InterruptFlag::CA1ActiveEdge;
-				reevaluate_interrupts();
-			}
-			control_inputs_[port].line_one = value;
-		break;
-
-		case Line::Two:
-			// TODO: output modes, but probably elsewhere?
-			if(	value != control_inputs_[port].line_two &&							// i.e. value has changed ...
-				!(registers_.peripheral_control & (port ? 0x80 : 0x08)) &&			// ... and line is input ...
-				value == !!(registers_.peripheral_control & (port ? 0x40 : 0x04))	// ... and it's either high or low, as required
-			) {
-				registers_.interrupt_flags |= port ? InterruptFlag::CB2ActiveEdge : InterruptFlag::CA2ActiveEdge;
-				reevaluate_interrupts();
-			}
-			control_inputs_[port].line_two = value;
-		break;
-	}
-}
-
-void MOS6522Base::do_phase2() {
-	registers_.last_timer[0] = registers_.timer[0];
-	registers_.last_timer[1] = registers_.timer[1];
-
-	if(registers_.timer_needs_reload) {
-		registers_.timer_needs_reload = false;
-		registers_.timer[0] = registers_.timer_latch[0];
-	} else {
-		registers_.timer[0] --;
-	}
-
-	registers_.timer[1] --;
-	if(registers_.next_timer[0] >= 0) {
-		registers_.timer[0] = static_cast<uint16_t>(registers_.next_timer[0]);
-		registers_.next_timer[0] = -1;
-	}
-	if(registers_.next_timer[1] >= 0) {
-		registers_.timer[1] = static_cast<uint16_t>(registers_.next_timer[1]);
-		registers_.next_timer[1] = -1;
-	}
-}
-
-void MOS6522Base::do_phase1() {
-	// IRQ is raised on the half cycle after overflow
-	if((registers_.timer[1] == 0xffff) && !registers_.last_timer[1] && timer_is_running_[1]) {
-		timer_is_running_[1] = false;
-		registers_.interrupt_flags |= InterruptFlag::Timer2;
-		reevaluate_interrupts();
-	}
-
-	if((registers_.timer[0] == 0xffff) && !registers_.last_timer[0] && timer_is_running_[0]) {
-		registers_.interrupt_flags |= InterruptFlag::Timer1;
-		reevaluate_interrupts();
-
-		if(registers_.auxiliary_control&0x40)
-			registers_.timer_needs_reload = true;
-		else
-			timer_is_running_[0] = false;
-	}
-}
-
-/*! Runs for a specified number of half cycles. */
-void MOS6522Base::run_for(const HalfCycles half_cycles) {
-	int number_of_half_cycles = half_cycles.as_int();
-
-	if(is_phase2_) {
-		do_phase2();
-		number_of_half_cycles--;
-	}
-
-	while(number_of_half_cycles >= 2) {
-		do_phase1();
-		do_phase2();
-		number_of_half_cycles -= 2;
-	}
-
-	if(number_of_half_cycles) {
-		do_phase1();
-		is_phase2_ = true;
-	} else {
-		is_phase2_ = false;
-	}
-}
-
-/*! Runs for a specified number of cycles. */
-void MOS6522Base::run_for(const Cycles cycles) {
-	int number_of_cycles = cycles.as_int();
-	while(number_of_cycles--) {
-		do_phase1();
-		do_phase2();
-	}
-}
-
-/*! @returns @c true if the IRQ line is currently active; @c false otherwise. */
-bool MOS6522Base::get_interrupt_line() {
-	uint8_t interrupt_status = registers_.interrupt_flags & registers_.interrupt_enable & 0x7f;
-	return !!interrupt_status;
-}

Components/6522/Implementation/6522Implementation.hpp

@@ -6,29 +6,63 @@
 //  Copyright 2017 Thomas Harte. All rights reserved.
 //
 
-template <typename T> void MOS6522<T>::set_register(int address, uint8_t value) {
-	address &= 0xf;
+#include "../../../Outputs/Log.hpp"
+
+namespace MOS {
+namespace MOS6522 {
+
+template <typename T> void MOS6522<T>::access(int address) {
 	switch(address) {
 		case 0x0:
+			// In both handshake and pulse modes, CB2 goes low on any read or write of Port B.
+			if(handshake_modes_[1] != HandshakeMode::None) {
+				set_control_line_output(Port::B, Line::Two, LineState::Off);
+			}
+		break;
+
+		case 0xf:
+		case 0x1:
+			// In both handshake and pulse modes, CA2 goes low on any read or write of Port A.
+			if(handshake_modes_[0] != HandshakeMode::None) {
+				set_control_line_output(Port::A, Line::Two, LineState::Off);
+			}
+		break;
+	}
+}
+
+template <typename T> void MOS6522<T>::write(int address, uint8_t value) {
+	address &= 0xf;
+	access(address);
+	switch(address) {
+		case 0x0:	// Write Port B.
+			// Store locally and communicate outwards.
 			registers_.output[1] = value;
-			bus_handler_.set_port_output(Port::B, value, registers_.data_direction[1]);	// TODO: handshake
+
+			bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
+			bus_handler_.set_port_output(Port::B, value, registers_.data_direction[1]);
 
 			registers_.interrupt_flags &= ~(InterruptFlag::CB1ActiveEdge | ((registers_.peripheral_control&0x20) ? 0 : InterruptFlag::CB2ActiveEdge));
 			reevaluate_interrupts();
 		break;
 		case 0xf:
-		case 0x1:
+		case 0x1:	// Write Port A.
 			registers_.output[0] = value;
-			bus_handler_.set_port_output(Port::A, value, registers_.data_direction[0]);	// TODO: handshake
+
+			bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
+			bus_handler_.set_port_output(Port::A, value, registers_.data_direction[0]);
+
+			if(handshake_modes_[1] != HandshakeMode::None) {
+				set_control_line_output(Port::A, Line::Two, LineState::Off);
+			}
 
 			registers_.interrupt_flags &= ~(InterruptFlag::CA1ActiveEdge | ((registers_.peripheral_control&0x02) ? 0 : InterruptFlag::CB2ActiveEdge));
 			reevaluate_interrupts();
 		break;
 
-		case 0x2:
+		case 0x2:	// Port B direction.
 			registers_.data_direction[1] = value;
 		break;
-		case 0x3:
+		case 0x3:	// Port A direction.
 			registers_.data_direction[0] = value;
 		break;
 
@@ -54,32 +88,57 @@ template <typename T> void MOS6522<T>::set_register(int address, uint8_t value)
 		break;
 
 		// Shift
-		case 0xa:	registers_.shift = value;				break;
+		case 0xa:
+			registers_.shift = value;
+			shift_bits_remaining_ = 8;
+			registers_.interrupt_flags &= ~InterruptFlag::ShiftRegister;
+			reevaluate_interrupts();
+		break;
 
 		// Control
 		case 0xb:
 			registers_.auxiliary_control = value;
+			evaluate_cb2_output();
 		break;
-		case 0xc:
-//			printf("Peripheral control %02x\n", value);
+		case 0xc: {
+//			const auto old_peripheral_control = registers_.peripheral_control;
 			registers_.peripheral_control = value;
 
-			// TODO: simplify below; trying to avoid improper logging of unimplemented warnings in input mode
-			if(value & 0x08) {
-				switch(value & 0x0e) {
-					default: printf("Unimplemented control line mode %d\n", (value >> 1)&7);		break;
-					case 0x0c:	bus_handler_.set_control_line_output(Port::A, Line::Two, false);	break;
-					case 0x0e:	bus_handler_.set_control_line_output(Port::A, Line::Two, true);		break;
+			int shift = 0;
+			for(int port = 0; port < 2; ++port) {
+				handshake_modes_[port] = HandshakeMode::None;
+				switch((value >> shift) & 0x0e) {
+					default: break;
+
+					case 0x00:	// Negative interrupt input; set Cx2 interrupt on negative Cx2 transition, clear on access to Port x register.
+					case 0x02:	// Independent negative interrupt input; set Cx2 interrupt on negative transition, don't clear automatically.
+					case 0x04:	// Positive interrupt input; set Cx2 interrupt on positive Cx2 transition, clear on access to Port x register.
+					case 0x06:	// Independent positive interrupt input; set Cx2 interrupt on positive transition, don't clear automatically.
+						set_control_line_output(Port(port), Line::Two, LineState::Input);
+					break;
+
+					case 0x08:	// Handshake: set Cx2 to low on any read or write of Port x; set to high on an active transition of Cx1.
+						handshake_modes_[port] = HandshakeMode::Handshake;
+						set_control_line_output(Port(port), Line::Two, LineState::Off);	// At a guess.
+					break;
+
+					case 0x0a:	// Pulse output: Cx2 is low for one cycle following a read or write of Port x.
+						handshake_modes_[port] = HandshakeMode::Pulse;
+						set_control_line_output(Port(port), Line::Two, LineState::On);
+					break;
+
+					case 0x0c:	// Manual output: Cx2 low.
+						set_control_line_output(Port(port), Line::Two, LineState::Off);
+					break;
+
+					case 0x0e:	// Manual output: Cx2 high.
+						set_control_line_output(Port(port), Line::Two, LineState::On);
+					break;
 				}
+
+				shift += 4;
 			}
-			if(value & 0x80) {
-				switch(value & 0xe0) {
-					default: printf("Unimplemented control line mode %d\n", (value >> 5)&7);		break;
-					case 0xc0:	bus_handler_.set_control_line_output(Port::B, Line::Two, false);	break;
-					case 0xe0:	bus_handler_.set_control_line_output(Port::B, Line::Two, true);		break;
-				}
-			}
-		break;
+		} break;
 
 		// Interrupt control
 		case 0xd:
@@ -96,14 +155,15 @@ template <typename T> void MOS6522<T>::set_register(int address, uint8_t value)
 	}
 }
 
-template <typename T> uint8_t MOS6522<T>::get_register(int address) {
+template <typename T> uint8_t MOS6522<T>::read(int address) {
 	address &= 0xf;
+	access(address);
 	switch(address) {
 		case 0x0:
 			registers_.interrupt_flags &= ~(InterruptFlag::CB1ActiveEdge | InterruptFlag::CB2ActiveEdge);
 			reevaluate_interrupts();
 		return get_port_input(Port::B, registers_.data_direction[1], registers_.output[1]);
-		case 0xf:	// TODO: handshake, latching
+		case 0xf:
 		case 0x1:
 			registers_.interrupt_flags &= ~(InterruptFlag::CA1ActiveEdge | InterruptFlag::CA2ActiveEdge);
 			reevaluate_interrupts();
@@ -128,7 +188,11 @@ template <typename T> uint8_t MOS6522<T>::get_register(int address) {
 		return registers_.timer[1] & 0x00ff;
 		case 0x9:	return registers_.timer[1] >> 8;
 
-		case 0xa:	return registers_.shift;
+		case 0xa:
+			shift_bits_remaining_ = 8;
+			registers_.interrupt_flags &= ~InterruptFlag::ShiftRegister;
+			reevaluate_interrupts();
+		return registers_.shift;
 
 		case 0xb:	return registers_.auxiliary_control;
 		case 0xc:	return registers_.peripheral_control;
@@ -141,7 +205,8 @@ template <typename T> uint8_t MOS6522<T>::get_register(int address) {
 }
 
 template <typename T> uint8_t MOS6522<T>::get_port_input(Port port, uint8_t output_mask, uint8_t output) {
-	uint8_t input = bus_handler_.get_port_input(port);
+	bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
+	const uint8_t input = bus_handler_.get_port_input(port);
 	return (input & ~output_mask) | (output & output_mask);
 }
 
@@ -154,6 +219,238 @@ template <typename T> void MOS6522<T>::reevaluate_interrupts() {
 	bool new_interrupt_status = get_interrupt_line();
 	if(new_interrupt_status != last_posted_interrupt_status_) {
 		last_posted_interrupt_status_ = new_interrupt_status;
+
+		bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
 		bus_handler_.set_interrupt_status(new_interrupt_status);
 	}
 }
+
+template <typename T> void MOS6522<T>::set_control_line_input(Port port, Line line, bool value) {
+	switch(line) {
+		case Line::One:
+			if(value != control_inputs_[port].lines[line]) {
+				// In handshake mode, any transition on C[A/B]1 sets output high on C[A/B]2.
+				if(handshake_modes_[port] == HandshakeMode::Handshake) {
+					set_control_line_output(port, Line::Two, LineState::On);
+				}
+
+				// Set the proper transition interrupt bit if enabled.
+				if(value == !!(registers_.peripheral_control & (port ? 0x10 : 0x01))) {
+					registers_.interrupt_flags |= port ? InterruptFlag::CB1ActiveEdge : InterruptFlag::CA1ActiveEdge;
+					reevaluate_interrupts();
+				}
+
+				// If this is a transition on CB1, consider updating the shift register.
+				// TODO: and at least one full clock since the shift register was written?
+				if(port == Port::B) {
+					switch(shift_mode()) {
+						default: 													break;
+						case ShiftMode::InUnderCB1:		if(value)	shift_in();		break;	// Shifts in are captured on a low-to-high transition.
+						case ShiftMode::OutUnderCB1:	if(!value)	shift_out();	break;	// Shifts out are updated on a high-to-low transition.
+					}
+				}
+			}
+			control_inputs_[port].lines[line] = value;
+		break;
+
+		case Line::Two:
+			if(	value != control_inputs_[port].lines[line] &&						// i.e. value has changed ...
+				!(registers_.peripheral_control & (port ? 0x80 : 0x08)) &&			// ... and line is input ...
+				value == !!(registers_.peripheral_control & (port ? 0x40 : 0x04))	// ... and it's either high or low, as required
+			) {
+				registers_.interrupt_flags |= port ? InterruptFlag::CB2ActiveEdge : InterruptFlag::CA2ActiveEdge;
+				reevaluate_interrupts();
+			}
+			control_inputs_[port].lines[line] = value;
+		break;
+	}
+}
+
+template <typename T> void MOS6522<T>::do_phase2() {
+	++ time_since_bus_handler_call_;
+
+	registers_.last_timer[0] = registers_.timer[0];
+	registers_.last_timer[1] = registers_.timer[1];
+
+	if(registers_.timer_needs_reload) {
+		registers_.timer_needs_reload = false;
+		registers_.timer[0] = registers_.timer_latch[0];
+	} else {
+		registers_.timer[0] --;
+	}
+
+	registers_.timer[1] --;
+	if(registers_.next_timer[0] >= 0) {
+		registers_.timer[0] = static_cast<uint16_t>(registers_.next_timer[0]);
+		registers_.next_timer[0] = -1;
+	}
+	if(registers_.next_timer[1] >= 0) {
+		registers_.timer[1] = static_cast<uint16_t>(registers_.next_timer[1]);
+		registers_.next_timer[1] = -1;
+	}
+
+	// In pulse modes, CA2 and CB2 go high again on the next clock edge.
+	if(handshake_modes_[1] == HandshakeMode::Pulse) {
+		set_control_line_output(Port::B, Line::Two, LineState::On);
+	}
+	if(handshake_modes_[0] == HandshakeMode::Pulse) {
+		set_control_line_output(Port::A, Line::Two, LineState::On);
+	}
+
+	// If the shift register is shifting according to the input clock, do a shift.
+	switch(shift_mode()) {
+		default: 											break;
+		case ShiftMode::InUnderPhase2:		shift_in();		break;
+		case ShiftMode::OutUnderPhase2:		shift_out();	break;
+	}
+}
+
+template <typename T> void MOS6522<T>::do_phase1() {
+	++ time_since_bus_handler_call_;
+
+	// IRQ is raised on the half cycle after overflow
+	if((registers_.timer[1] == 0xffff) && !registers_.last_timer[1] && timer_is_running_[1]) {
+		timer_is_running_[1] = false;
+
+		// If the shift register is shifting according to this timer, do a shift.
+		// TODO: "shift register is driven by only the low order 8 bits of timer 2"?
+		switch(shift_mode()) {
+			default: 												break;
+			case ShiftMode::InUnderT2:				shift_in();		break;
+			case ShiftMode::OutUnderT2FreeRunning: 	shift_out();	break;
+			case ShiftMode::OutUnderT2:				shift_out();	break;	// TODO: present a clock on CB1.
+		}
+
+		registers_.interrupt_flags |= InterruptFlag::Timer2;
+		reevaluate_interrupts();
+	}
+
+	if((registers_.timer[0] == 0xffff) && !registers_.last_timer[0] && timer_is_running_[0]) {
+		registers_.interrupt_flags |= InterruptFlag::Timer1;
+		reevaluate_interrupts();
+
+		// Determine whether to reload.
+		if(registers_.auxiliary_control&0x40)
+			registers_.timer_needs_reload = true;
+		else
+			timer_is_running_[0] = false;
+
+		// Determine whether to toggle PB7.
+		if(registers_.auxiliary_control&0x80) {
+			registers_.output[1] ^= 0x80;
+			bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
+			bus_handler_.set_port_output(Port::B, registers_.output[1], registers_.data_direction[1]);
+		}
+	}
+}
+
+/*! Runs for a specified number of half cycles. */
+template <typename T> void MOS6522<T>::run_for(const HalfCycles half_cycles) {
+	auto number_of_half_cycles = half_cycles.as_integral();
+	if(!number_of_half_cycles) return;
+
+	if(is_phase2_) {
+		do_phase2();
+		number_of_half_cycles--;
+	}
+
+	while(number_of_half_cycles >= 2) {
+		do_phase1();
+		do_phase2();
+		number_of_half_cycles -= 2;
+	}
+
+	if(number_of_half_cycles) {
+		do_phase1();
+		is_phase2_ = true;
+	} else {
+		is_phase2_ = false;
+	}
+}
+
+template <typename T> void MOS6522<T>::flush() {
+	bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
+	bus_handler_.flush();
+}
+
+/*! Runs for a specified number of cycles. */
+template <typename T> void MOS6522<T>::run_for(const Cycles cycles) {
+	auto number_of_cycles = cycles.as_integral();
+	while(number_of_cycles--) {
+		do_phase1();
+		do_phase2();
+	}
+}
+
+/*! @returns @c true if the IRQ line is currently active; @c false otherwise. */
+template <typename T> bool MOS6522<T>::get_interrupt_line() {
+	uint8_t interrupt_status = registers_.interrupt_flags & registers_.interrupt_enable & 0x7f;
+	return !!interrupt_status;
+}
+
+template <typename T> void MOS6522<T>::evaluate_cb2_output() {
+	// CB2 is a special case, being both the line the shift register can output to,
+	// and one that can be used as an input or handshaking output according to the
+	// peripheral control register.
+
+	// My guess: other CB2 functions work only if the shift register is disabled (?).
+	if(shift_mode() != ShiftMode::Disabled) {
+		// Shift register is enabled, one way or the other; but announce only output.
+		if(is_shifting_out()) {
+			// Output mode; set the level according to the current top of the shift register.
+			bus_handler_.set_control_line_output(Port::B, Line::Two, !!(registers_.shift & 0x80));
+		} else {
+			// Input mode.
+			bus_handler_.set_control_line_output(Port::B, Line::Two, true);
+		}
+	} else {
+		// Shift register is disabled.
+		bus_handler_.set_control_line_output(Port::B, Line::Two, control_outputs_[1].lines[1] != LineState::Off);
+	}
+}
+
+template <typename T> void MOS6522<T>::set_control_line_output(Port port, Line line, LineState value) {
+	if(port == Port::B && line == Line::Two) {
+		control_outputs_[port].lines[line] = value;
+		evaluate_cb2_output();
+	} else {
+		// Do nothing if unchanged.
+		if(value == control_outputs_[port].lines[line]) {
+			return;
+		}
+
+		control_outputs_[port].lines[line] = value;
+
+		if(value != LineState::Input) {
+			bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
+			bus_handler_.set_control_line_output(port, line, value != LineState::Off);
+		}
+	}
+}
+
+template <typename T> void MOS6522<T>::shift_in() {
+	registers_.shift = uint8_t((registers_.shift << 1) | (control_inputs_[1].lines[1] ? 1 : 0));
+	--shift_bits_remaining_;
+	if(!shift_bits_remaining_) {
+		registers_.interrupt_flags |= InterruptFlag::ShiftRegister;
+		reevaluate_interrupts();
+	}
+}
+
+template <typename T> void MOS6522<T>::shift_out() {
+	// When shifting out, the shift register rotates rather than strictly shifts.
+	// TODO: is that true for all modes?
+	if(shift_mode() == ShiftMode::OutUnderT2FreeRunning || shift_bits_remaining_) {
+		registers_.shift = uint8_t((registers_.shift << 1) | (registers_.shift >> 7));
+		evaluate_cb2_output();
+
+		--shift_bits_remaining_;
+		if(!shift_bits_remaining_) {
+			registers_.interrupt_flags |= InterruptFlag::ShiftRegister;
+			reevaluate_interrupts();
+		}
+	}
+}
+
+}
+}

Components/6522/Implementation/6522Storage.hpp

@@ -21,7 +21,7 @@ class MOS6522Storage {
 
 		// The registers
 		struct Registers {
-			// "A  low  reset  (RES)  input  clears  all  R6522  internal registers to logic 0"
+			// "A low reset (RES) input clears all R6522 internal registers to logic 0"
 			uint8_t output[2] = {0, 0};
 			uint8_t input[2] = {0, 0};
 			uint8_t data_direction[2] = {0, 0};
@@ -37,14 +37,27 @@ class MOS6522Storage {
 			bool timer_needs_reload = false;
 		} registers_;
 
-		// control state
+		// Control state.
 		struct {
-			bool line_one = false;
-			bool line_two = false;
+			bool lines[2] = {false, false};
 		} control_inputs_[2];
 
+		enum class LineState {
+			On, Off, Input
+		};
+		struct {
+			LineState lines[2] = {LineState::Input, LineState::Input};
+		} control_outputs_[2];
+
+		enum class HandshakeMode {
+			None,
+			Handshake,
+			Pulse
+		} handshake_modes_[2] = { HandshakeMode::None, HandshakeMode::None };
+
 		bool timer_is_running_[2] = {false, false};
 		bool last_posted_interrupt_status_ = false;
+		int shift_bits_remaining_ = 8;
 
 		enum InterruptFlag: uint8_t {
 			CA2ActiveEdge	= 1 << 0,
@@ -55,6 +68,23 @@ class MOS6522Storage {
 			Timer2			= 1 << 5,
 			Timer1			= 1 << 6,
 		};
+
+		enum class ShiftMode {
+			Disabled = 0,
+			InUnderT2 = 1,
+			InUnderPhase2 = 2,
+			InUnderCB1 = 3,
+			OutUnderT2FreeRunning = 4,
+			OutUnderT2 = 5,
+			OutUnderPhase2 = 6,
+			OutUnderCB1 = 7
+		};
+		ShiftMode shift_mode() const {
+			return ShiftMode((registers_.auxiliary_control >> 2) & 7);
+		}
+		bool is_shifting_out() const {
+			return registers_.auxiliary_control & 0x10;
+		}
 };
 
 }

Components/6532/6532.hpp

@@ -32,7 +32,7 @@ template <class T> class MOS6532 {
 		inline void set_ram(uint16_t address, uint8_t value)	{	ram_[address&0x7f] = value;		}
 		inline uint8_t get_ram(uint16_t address)				{	return ram_[address & 0x7f];	}
 
-		inline void set_register(int address, uint8_t value) {
+		inline void write(int address, uint8_t value) {
 			const uint8_t decodedAddress = address & 0x07;
 			switch(decodedAddress) {
 				// Port output
@@ -63,7 +63,7 @@ template <class T> class MOS6532 {
 			}
 		}
 
-		inline uint8_t get_register(int address) {
+		inline uint8_t read(int address) {
 			const uint8_t decodedAddress = address & 0x7;
 			switch(decodedAddress) {
 				// Port input
@@ -107,7 +107,7 @@ template <class T> class MOS6532 {
 		}
 
 		inline void run_for(const Cycles cycles) {
-			unsigned int number_of_cycles = static_cast<unsigned int>(cycles.as_int());
+			unsigned int number_of_cycles = static_cast<unsigned int>(cycles.as_integral());
 
 			// permit counting _to_ zero; counting _through_ zero initiates the other behaviour
 			if(timer_.value >= number_of_cycles) {

Components/6560/6560.hpp

@@ -34,7 +34,7 @@ class AudioGenerator: public ::Outputs::Speaker::SampleSource {
 	private:
 		Concurrency::DeferringAsyncTaskQueue &audio_queue_;
 
-		unsigned int counters_[4] = {2, 1, 0, 0}; 	// create a slight phase offset for the three channels
+		unsigned int counters_[4] = {2, 1, 0, 0};	// create a slight phase offset for the three channels
 		unsigned int shift_registers_[4] = {0, 0, 0, 0};
 		uint8_t control_registers_[4] = {0, 0, 0, 0};
 		int16_t volume_ = 0;
@@ -58,29 +58,18 @@ enum class OutputMode {
 	To run the VIC for a cycle, the caller should call @c get_address, make the requested bus access
 	and call @c set_graphics_value with the result.
 
-	@c set_register and @c get_register provide register access.
+	@c write and @c read provide register access.
 */
 template <class BusHandler> class MOS6560 {
 	public:
 		MOS6560(BusHandler &bus_handler) :
 				bus_handler_(bus_handler),
-				crt_(new Outputs::CRT::CRT(65*4, 4, Outputs::CRT::DisplayType::NTSC60, 2)),
+				crt_(65*4, 1, Outputs::Display::Type::NTSC60, Outputs::Display::InputDataType::Luminance8Phase8),
 				audio_generator_(audio_queue_),
 				speaker_(audio_generator_)
 		{
-			crt_->set_svideo_sampling_function(
-				"vec2 svideo_sample(usampler2D texID, vec2 coordinate, vec2 iCoordinate, float phase)"
-				"{"
-					"vec2 yc = texture(texID, coordinate).rg / vec2(255.0);"
-
-					"float phaseOffset = 6.283185308 * 2.0 * yc.y;"
-					"float chroma = step(yc.y, 0.75) * cos(phase + phaseOffset);"
-
-					"return vec2(yc.x, chroma);"
-				"}");
-
 			// default to s-video output
-			crt_->set_video_signal(Outputs::CRT::VideoSignal::SVideo);
+			crt_.set_display_type(Outputs::Display::DisplayType::SVideo);
 
 			// default to NTSC
 			set_output_mode(OutputMode::NTSC);
@@ -94,7 +83,9 @@ template <class BusHandler> class MOS6560 {
 			speaker_.set_input_rate(static_cast<float>(clock_rate / 4.0));
 		}
 
-		Outputs::CRT::CRT *get_crt() { return crt_.get(); }
+		void set_scan_target(Outputs::Display::ScanTarget *scan_target)		{ crt_.set_scan_target(scan_target); 			}
+		Outputs::Display::ScanStatus get_scaled_scan_status() const			{ return crt_.get_scaled_scan_status() / 4.0f;	}
+		void set_display_type(Outputs::Display::DisplayType display_type)	{ crt_.set_display_type(display_type); 			}
 		Outputs::Speaker::Speaker *get_speaker() { return &speaker_; }
 
 		void set_high_frequency_cutoff(float cutoff) {
@@ -117,26 +108,26 @@ template <class BusHandler> class MOS6560 {
 
 			// Chrominances are encoded such that 0-128 is a complete revolution of phase;
 			// anything above 191 disables the colour subcarrier. Phase is relative to the
-			// colour burst, so 0 is green.
+			// colour burst, so 0 is green (NTSC) or blue/violet (PAL).
 			const uint8_t pal_chrominances[16] = {
-				255,	255,	37,		101,
-				19,		86,		123,	59,
-				46,		53,		37,		101,
-				19,		86,		123,	59,
+				255,	255,	90,		20,
+				96,		42,		8,		72,
+				84,		90,		90,		20,
+				96,		42,		8,		72,
 			};
 			const uint8_t ntsc_chrominances[16] = {
-				255,	255,	7,		71,
-				25,		86,		48,		112,
-				0,		119,	7,		71,
-				25,		86,		48,		112,
+				255,	255,	121,	57,
+				103,	42,		80,		16,
+				0,		9,		121,	57,
+				103,	42,		80,		16,
 			};
 			const uint8_t *chrominances;
-			Outputs::CRT::DisplayType display_type;
+			Outputs::Display::Type display_type;
 
 			switch(output_mode) {
 				default:
 					chrominances = pal_chrominances;
-					display_type = Outputs::CRT::DisplayType::PAL50;
+					display_type = Outputs::Display::Type::PAL50;
 					timing_.cycles_per_line = 71;
 					timing_.line_counter_increment_offset = 4;
 					timing_.final_line_increment_position = timing_.cycles_per_line - timing_.line_counter_increment_offset;
@@ -146,7 +137,7 @@ template <class BusHandler> class MOS6560 {
 
 				case OutputMode::NTSC:
 					chrominances = ntsc_chrominances;
-					display_type = Outputs::CRT::DisplayType::NTSC60;
+					display_type = Outputs::Display::Type::NTSC60;
 					timing_.cycles_per_line = 65;
 					timing_.line_counter_increment_offset = 40;
 					timing_.final_line_increment_position = 58;
@@ -155,14 +146,14 @@ template <class BusHandler> class MOS6560 {
 				break;
 			}
 
-			crt_->set_new_display_type(static_cast<unsigned int>(timing_.cycles_per_line*4), display_type);
+			crt_.set_new_display_type(timing_.cycles_per_line*4, display_type);
 
 			switch(output_mode) {
 				case OutputMode::PAL:
-					crt_->set_visible_area(Outputs::CRT::Rect(0.1f, 0.07f, 0.9f, 0.9f));
+					crt_.set_visible_area(Outputs::Display::Rect(0.1f, 0.07f, 0.9f, 0.9f));
 				break;
 				case OutputMode::NTSC:
-					crt_->set_visible_area(Outputs::CRT::Rect(0.05f, 0.05f, 0.9f, 0.9f));
+					crt_.set_visible_area(Outputs::Display::Rect(0.05f, 0.05f, 0.9f, 0.9f));
 				break;
 			}
 
@@ -180,7 +171,7 @@ template <class BusHandler> class MOS6560 {
 			// keep track of the amount of time since the speaker was updated; lazy updates are applied
 			cycles_since_speaker_update_ += cycles;
 
-			int number_of_cycles = cycles.as_int();
+			auto number_of_cycles = cycles.as_integral();
 			while(number_of_cycles--) {
 				// keep an old copy of the vertical count because that test is a cycle later than the actual changes
 				int previous_vertical_counter = vertical_counter_;
@@ -284,17 +275,17 @@ template <class BusHandler> class MOS6560 {
 				// update the CRT
 				if(this_state_ != output_state_) {
 					switch(output_state_) {
-						case State::Sync:			crt_->output_sync(cycles_in_state_ * 4);														break;
-						case State::ColourBurst:	crt_->output_colour_burst(cycles_in_state_ * 4, (is_odd_frame_ || is_odd_line_) ? 128 : 0);		break;
-						case State::Border:			output_border(cycles_in_state_ * 4);															break;
-						case State::Pixels:			crt_->output_data(cycles_in_state_ * 4);														break;
+						case State::Sync:			crt_.output_sync(cycles_in_state_ * 4);														break;
+						case State::ColourBurst:	crt_.output_colour_burst(cycles_in_state_ * 4, (is_odd_frame_ || is_odd_line_) ? 128 : 0);	break;
+						case State::Border:			output_border(cycles_in_state_ * 4);														break;
+						case State::Pixels:			crt_.output_data(cycles_in_state_ * 4);														break;
 					}
 					output_state_ = this_state_;
 					cycles_in_state_ = 0;
 
 					pixel_pointer = nullptr;
 					if(output_state_ == State::Pixels) {
-						pixel_pointer = reinterpret_cast<uint16_t *>(crt_->allocate_write_area(260));
+						pixel_pointer = reinterpret_cast<uint16_t *>(crt_.begin_data(260));
 					}
 				}
 				cycles_in_state_++;
@@ -363,7 +354,7 @@ template <class BusHandler> class MOS6560 {
 		/*!
 			Writes to a 6560 register.
 		*/
-		void set_register(int address, uint8_t value) {
+		void write(int address, uint8_t value) {
 			address &= 0xf;
 			registers_.direct_values[address] = value;
 			switch(address) {
@@ -427,7 +418,7 @@ template <class BusHandler> class MOS6560 {
 		/*
 			Reads from a 6560 register.
 		*/
-		uint8_t get_register(int address) {
+		uint8_t read(int address) {
 			address &= 0xf;
 			switch(address) {
 				default: return registers_.direct_values[address];
@@ -438,7 +429,7 @@ template <class BusHandler> class MOS6560 {
 
 	private:
 		BusHandler &bus_handler_;
-		std::unique_ptr<Outputs::CRT::CRT> crt_;
+		Outputs::CRT::CRT crt_;
 
 		Concurrency::DeferringAsyncTaskQueue audio_queue_;
 		AudioGenerator audio_generator_;
@@ -451,12 +442,12 @@ template <class BusHandler> class MOS6560 {
 
 		// register state
 		struct {
-			bool interlaced, tall_characters;
+			bool interlaced = false, tall_characters = false;
 			uint8_t first_column_location, first_row_location;
 			uint8_t number_of_columns, number_of_rows;
 			uint16_t character_cell_start_address, video_matrix_start_address;
 			uint16_t backgroundColour, borderColour, auxiliary_colour;
-			bool invertedCells;
+			bool invertedCells = false;
 
 			uint8_t direct_values[16];
 		} registers_;
@@ -465,7 +456,7 @@ template <class BusHandler> class MOS6560 {
 		enum State {
 			Sync, ColourBurst, Border, Pixels
 		} this_state_, output_state_;
-		unsigned int cycles_in_state_;
+		int cycles_in_state_;
 
 		// counters that cover an entire field
 		int horizontal_counter_ = 0, vertical_counter_ = 0;
@@ -493,7 +484,7 @@ template <class BusHandler> class MOS6560 {
 		}
 
 		// latches dictating start and length of drawing
-		bool vertical_drawing_latch_, horizontal_drawing_latch_;
+		bool vertical_drawing_latch_ = false, horizontal_drawing_latch_ = false;
 		int rows_this_field_, columns_this_line_;
 
 		// current drawing position counter
@@ -511,10 +502,10 @@ template <class BusHandler> class MOS6560 {
 		uint16_t colours_[16];
 
 		uint16_t *pixel_pointer;
-		void output_border(unsigned int number_of_cycles) {
-			uint16_t *colour_pointer = reinterpret_cast<uint16_t *>(crt_->allocate_write_area(1));
+		void output_border(int number_of_cycles) {
+			uint16_t *colour_pointer = reinterpret_cast<uint16_t *>(crt_.begin_data(1));
 			if(colour_pointer) *colour_pointer = registers_.borderColour;
-			crt_->output_level(number_of_cycles);
+			crt_.output_level(number_of_cycles);
 		}
 
 		struct {

Components/6845/CRTC6845.hpp

@@ -111,7 +111,7 @@ template <class T> class CRTC6845 {
 		}
 
 		void run_for(Cycles cycles) {
-			int cyles_remaining = cycles.as_int();
+			auto cyles_remaining = cycles.as_integral();
 			while(cyles_remaining--) {
 				// check for end of visible characters
 				if(character_counter_ == registers_[1]) {

Components/6850/6850.cpp

@@ -0,0 +1,228 @@
+//
+//  6850.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 10/10/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#include "6850.hpp"
+
+#include <cassert>
+
+using namespace Motorola::ACIA;
+
+const HalfCycles ACIA::SameAsTransmit;
+
+ACIA::ACIA(HalfCycles transmit_clock_rate, HalfCycles receive_clock_rate) :
+	transmit_clock_rate_(transmit_clock_rate),
+	receive_clock_rate_((receive_clock_rate != SameAsTransmit) ? receive_clock_rate : transmit_clock_rate) {
+	transmit.set_writer_clock_rate(transmit_clock_rate);
+	request_to_send.set_writer_clock_rate(transmit_clock_rate);
+}
+
+uint8_t ACIA::read(int address) {
+	if(address&1) {
+		overran_ = false;
+		received_data_ |= NoValueMask;
+		update_interrupt_line();
+		return uint8_t(received_data_);
+	} else {
+		return get_status();
+	}
+}
+
+void ACIA::reset() {
+	transmit.reset_writing();
+	transmit.write(true);
+	request_to_send.reset_writing();
+
+	bits_received_ = bits_incoming_ = 0;
+	receive_interrupt_enabled_ = transmit_interrupt_enabled_ = false;
+	overran_ = false;
+	next_transmission_ = received_data_ = NoValueMask;
+
+	update_interrupt_line();
+	assert(!interrupt_line_);
+}
+
+void ACIA::write(int address, uint8_t value) {
+	if(address&1) {
+		next_transmission_ = value;
+		consider_transmission();
+		update_interrupt_line();
+	} else {
+		if((value&3) == 3) {
+			reset();
+		} else {
+			switch(value & 3) {
+				default:
+				case 0: divider_ = 1;	break;
+				case 1: divider_ = 16;	break;
+				case 2: divider_ = 64;	break;
+			}
+			switch((value >> 2) & 7) {
+				default:
+				case 0:	data_bits_ = 7; stop_bits_ = 2; parity_ = Parity::Even;	break;
+				case 1:	data_bits_ = 7; stop_bits_ = 2; parity_ = Parity::Odd;	break;
+				case 2:	data_bits_ = 7; stop_bits_ = 1; parity_ = Parity::Even;	break;
+				case 3:	data_bits_ = 7; stop_bits_ = 1; parity_ = Parity::Odd;	break;
+				case 4:	data_bits_ = 8; stop_bits_ = 2; parity_ = Parity::None;	break;
+				case 5:	data_bits_ = 8; stop_bits_ = 1; parity_ = Parity::None;	break;
+				case 6:	data_bits_ = 8; stop_bits_ = 1; parity_ = Parity::Even;	break;
+				case 7:	data_bits_ = 8; stop_bits_ = 1; parity_ = Parity::Odd;	break;
+			}
+			switch((value >> 5) & 3) {
+				case 0:	request_to_send.write(false); transmit_interrupt_enabled_ = false;	break;
+				case 1:	request_to_send.write(false); transmit_interrupt_enabled_ = true;	break;
+				case 2:	request_to_send.write(true); transmit_interrupt_enabled_ = false;	break;
+				case 3:
+					request_to_send.write(false);
+					transmit_interrupt_enabled_ = false;
+					transmit.reset_writing();
+					transmit.write(false);
+				break;
+			}
+			receive.set_read_delegate(this, Storage::Time(divider_ * 2, int(receive_clock_rate_.as_integral())));
+			receive_interrupt_enabled_ = value & 0x80;
+
+			update_interrupt_line();
+		}
+	}
+	update_clocking_observer();
+}
+
+void ACIA::consider_transmission() {
+	if(next_transmission_ != NoValueMask && !transmit.write_data_time_remaining()) {
+		// Establish start bit and [7 or 8] data bits.
+		if(data_bits_ == 7) next_transmission_ &= 0x7f;
+		int transmission = next_transmission_ << 1;
+
+		// Add a parity bit, if any.
+		int mask = 0x2 << data_bits_;
+		if(parity_ != Parity::None) {
+			transmission |= parity(uint8_t(next_transmission_)) ? mask : 0;
+			mask <<= 1;
+		}
+
+		// Add stop bits.
+		for(int c = 0; c < stop_bits_; ++c) {
+			transmission |= mask;
+			mask <<= 1;
+		}
+
+		// Output all that.
+		const int total_bits = expected_bits();
+		transmit.write(divider_ * 2, total_bits, transmission);
+
+		// Mark the transmit register as empty again.
+		next_transmission_ = NoValueMask;
+	}
+}
+
+ClockingHint::Preference ACIA::preferred_clocking() {
+	// Real-time clocking is required if a transmission is ongoing; this is a courtesy for whomever
+	// is on the receiving end.
+	if(transmit.transmission_data_time_remaining() > 0) return ClockingHint::Preference::RealTime;
+
+	// If a bit reception is ongoing that might lead to an interrupt, ask for real-time clocking
+	// because it's unclear when the interrupt might come.
+	if(bits_incoming_ && receive_interrupt_enabled_) return ClockingHint::Preference::RealTime;
+
+	// No clocking required then.
+	return ClockingHint::Preference::None;
+}
+
+bool ACIA::get_interrupt_line() const {
+	return interrupt_line_;
+}
+
+int ACIA::expected_bits() {
+	return 1 + data_bits_ + stop_bits_ + (parity_ != Parity::None);
+}
+
+uint8_t ACIA::parity(uint8_t value) {
+	value ^= value >> 4;
+	value ^= value >> 2;
+	value ^= value >> 1;
+	return value ^ (parity_ == Parity::Even);
+}
+
+bool ACIA::serial_line_did_produce_bit(Serial::Line *line, int bit) {
+	// Shift this bit into the 11-bit input register; this is big enough to hold
+	// the largest transmission symbol.
+	++bits_received_;
+	bits_incoming_ = (bits_incoming_ >> 1) | (bit << 10);
+
+	// If that's the now-expected number of bits, update.
+	const int bit_target = expected_bits();
+	if(bits_received_ >= bit_target) {
+		bits_received_ = 0;
+		overran_ |= get_status() & 1;
+		received_data_ = uint8_t(bits_incoming_ >> (12 - bit_target));
+		update_interrupt_line();
+		update_clocking_observer();
+		return false;
+	}
+
+	// TODO: overrun, and parity.
+
+	// Keep receiving, and consider a potential clocking change.
+	if(bits_received_ == 1) update_clocking_observer();
+	return true;
+}
+
+void ACIA::set_interrupt_delegate(InterruptDelegate *delegate) {
+	interrupt_delegate_ = delegate;
+}
+
+void ACIA::update_interrupt_line() {
+	const bool old_line = interrupt_line_;
+
+	/*
+		"Bit 7 of the control register is the rie bit. When the rie bit is high, the rdrf, ndcd,
+		and ovr bits will assert the nirq output. When the rie bit is low, nirq generation is disabled."
+
+		rie = read interrupt enable
+		rdrf = receive data register full (status word bit 0)
+		ndcd = data carrier detect (status word bit 2)
+		over = receiver overrun (status word bit 5)
+
+		"Bit 1 of the status register is the tdre bit. When high, the tdre bit indicates that data has been
+		transferred from the transmitter data register to the output shift register. At this point, the a6850
+		is ready to accept a new transmit data byte. However, if the ncts signal is high, the tdre bit remains
+		low regardless of the status of the transmitter data register. Also, if transmit interrupt is enabled,
+		the nirq output is asserted."
+
+		tdre = transmitter data register empty
+		ncts = clear to send
+	*/
+	const auto status = get_status();
+	interrupt_line_ =
+		(receive_interrupt_enabled_ && (status & 0x25)) ||
+		(transmit_interrupt_enabled_ && (status & 0x02));
+
+	if(interrupt_delegate_ && old_line != interrupt_line_) {
+		interrupt_delegate_->acia6850_did_change_interrupt_status(this);
+	}
+}
+
+uint8_t ACIA::get_status() {
+	return
+		((received_data_ & NoValueMask) ? 0x00 : 0x01) |
+		((next_transmission_ == NoValueMask) ? 0x02 : 0x00) |
+//		(data_carrier_detect.read() ? 0x04 : 0x00) |
+//		(clear_to_send.read() ? 0x08 : 0x00) |
+		(overran_ ? 0x20 : 0x00) |
+		(interrupt_line_ ? 0x80 : 0x00)
+	;
+
+	// b0: receive data full.
+	// b1: transmit data empty.
+	// b2: DCD.
+	// b3: CTS.
+	// b4: framing error (i.e. no first stop bit where expected).
+	// b5: receiver overran.
+	// b6: parity error.
+	// b7: IRQ state.
+}

Components/6850/6850.hpp

@@ -0,0 +1,132 @@
+//
+//  6850.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 10/10/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef Motorola_ACIA_6850_hpp
+#define Motorola_ACIA_6850_hpp
+
+#include <cstdint>
+#include "../../ClockReceiver/ClockReceiver.hpp"
+#include "../../ClockReceiver/ForceInline.hpp"
+#include "../../ClockReceiver/ClockingHintSource.hpp"
+#include "../Serial/Line.hpp"
+
+namespace Motorola {
+namespace ACIA {
+
+class ACIA: public ClockingHint::Source, private Serial::Line::ReadDelegate {
+	public:
+		static constexpr const HalfCycles SameAsTransmit = HalfCycles(0);
+
+		/*!
+			Constructs a new instance of ACIA which will receive a transmission clock at a rate of
+			@c transmit_clock_rate, and a receive clock at a rate of @c receive_clock_rate.
+		*/
+		ACIA(HalfCycles transmit_clock_rate, HalfCycles receive_clock_rate = SameAsTransmit);
+
+		/*!
+			Reads from the ACIA.
+
+			Bit 0 of the address is used as the ACIA's register select line —
+			so even addresses select control/status registers, odd addresses
+			select transmit/receive data registers.
+		*/
+		uint8_t read(int address);
+
+		/*!
+			Writes to the ACIA.
+
+			Bit 0 of the address is used as the ACIA's register select line —
+			so even addresses select control/status registers, odd addresses
+			select transmit/receive data registers.
+		*/
+		void write(int address, uint8_t value);
+
+		/*!
+			Advances @c transmission_cycles in time, which should be
+			counted relative to the @c transmit_clock_rate.
+		*/
+		forceinline void run_for(HalfCycles transmission_cycles) {
+			if(transmit.transmission_data_time_remaining() > HalfCycles(0)) {
+				const auto write_data_time_remaining = transmit.write_data_time_remaining();
+
+				// There's at most one further byte available to enqueue, so a single 'if'
+				// rather than a 'while' is correct here. It's the responsibilit of the caller
+				// to ensure run_for lengths are appropriate for longer sequences.
+				if(transmission_cycles >= write_data_time_remaining) {
+					if(next_transmission_ != NoValueMask) {
+						transmit.advance_writer(write_data_time_remaining);
+						consider_transmission();
+						transmit.advance_writer(transmission_cycles - write_data_time_remaining);
+					} else {
+						transmit.advance_writer(transmission_cycles);
+						update_clocking_observer();
+						update_interrupt_line();
+					}
+				} else {
+					transmit.advance_writer(transmission_cycles);
+				}
+			}
+		}
+
+		bool get_interrupt_line() const;
+		void reset();
+
+		// Input lines.
+		Serial::Line receive;
+		Serial::Line clear_to_send;
+		Serial::Line data_carrier_detect;
+
+		// Output lines.
+		Serial::Line transmit;
+		Serial::Line request_to_send;
+
+		// ClockingHint::Source.
+		ClockingHint::Preference preferred_clocking() final;
+
+		struct InterruptDelegate {
+			virtual void acia6850_did_change_interrupt_status(ACIA *acia) = 0;
+		};
+		void set_interrupt_delegate(InterruptDelegate *delegate);
+
+	private:
+		int divider_ = 1;
+		enum class Parity {
+			Even, Odd, None
+		} parity_ = Parity::None;
+		int data_bits_ = 7, stop_bits_ = 2;
+
+		static constexpr int NoValueMask = 0x100;
+		int next_transmission_ = NoValueMask;
+		int received_data_ = NoValueMask;
+
+		int bits_received_ = 0;
+		int bits_incoming_ = 0;
+		bool overran_ = false;
+
+		void consider_transmission();
+		int expected_bits();
+		uint8_t parity(uint8_t value);
+
+		bool receive_interrupt_enabled_ = false;
+		bool transmit_interrupt_enabled_ = false;
+
+		HalfCycles transmit_clock_rate_;
+		HalfCycles receive_clock_rate_;
+
+		bool serial_line_did_produce_bit(Serial::Line *line, int bit) final;
+
+		bool interrupt_line_ = false;
+		void update_interrupt_line();
+		InterruptDelegate *interrupt_delegate_ = nullptr;
+		uint8_t get_status();
+};
+
+}
+}
+
+#endif /* Motorola_ACIA_6850_hpp */

Components/68901/MFP68901.cpp

@@ -0,0 +1,374 @@
+//
+//  MFP68901.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 06/10/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#include "MFP68901.hpp"
+
+#include <algorithm>
+#include <cstring>
+
+#ifndef NDEBUG
+#define NDEBUG
+#endif
+
+#define LOG_PREFIX "[MFP] "
+#include "../../Outputs/Log.hpp"
+
+using namespace Motorola::MFP68901;
+
+ClockingHint::Preference MFP68901::preferred_clocking() {
+	// Rule applied: if any timer is actively running and permitted to produce an
+	// interrupt, request real-time running.
+	return
+		(timers_[0].mode >= TimerMode::Delay && interrupt_enable_&Interrupt::TimerA) ||
+		(timers_[1].mode >= TimerMode::Delay && interrupt_enable_&Interrupt::TimerB) ||
+		(timers_[2].mode >= TimerMode::Delay && interrupt_enable_&Interrupt::TimerC) ||
+		(timers_[3].mode >= TimerMode::Delay && interrupt_enable_&Interrupt::TimerD)
+			? ClockingHint::Preference::RealTime : ClockingHint::Preference::JustInTime;
+}
+
+uint8_t MFP68901::read(int address) {
+	address &= 0x1f;
+
+	// Interrupt block: various bits of state can be read, all passively.
+	if(address >= 0x03 && address <= 0x0b) {
+		const int shift = (address&1) << 3;
+		switch(address) {
+			case 0x03:	case 0x04:	return uint8_t(interrupt_enable_ >> shift);
+			case 0x05:	case 0x06:	return uint8_t(interrupt_pending_ >> shift);
+			case 0x07:	case 0x08:	return uint8_t(interrupt_in_service_ >> shift);
+			case 0x09:	case 0x0a:	return uint8_t(interrupt_mask_ >> shift);
+			case 0x0b:	return interrupt_vector_;
+
+			default: break;
+		}
+	}
+
+	switch(address) {
+		// GPIP block: input, and configured active edge and direction values.
+		case 0x00:	return (gpip_input_ & ~gpip_direction_) | (gpip_output_ & gpip_direction_);
+		case 0x01:	return gpip_active_edge_;
+		case 0x02:	return gpip_direction_;
+
+		/* Interrupt block dealt with above. */
+		default: break;
+
+		// Timer block: read back A, B and C/D control, and read current timer values.
+		case 0x0c:	case 0x0d:	return timer_ab_control_[address - 0xc];
+		case 0x0e:				return timer_cd_control_;
+		case 0x0f:	case 0x10:
+		case 0x11:	case 0x12:	return get_timer_data(address - 0xf);
+
+		// USART block: TODO.
+		case 0x13:		LOG("Read: sync character generator");	break;
+		case 0x14:		LOG("Read: USART control");				break;
+		case 0x15:		LOG("Read: receiver status");			break;
+		case 0x16:		LOG("Read: transmitter status");		break;
+		case 0x17:		LOG("Read: USART data");				break;
+	}
+	return 0x00;
+}
+
+void MFP68901::write(int address, uint8_t value) {
+	address &= 0x1f;
+
+	// Interrupt block: enabled and masked interrupts can be set; pending and in-service interrupts can be masked.
+	if(address >= 0x03 && address <= 0x0b) {
+		const int shift = (address&1) << 3;
+		const int preserve = 0xff00 >> shift;
+		const int word_value = value << shift;
+
+		switch(address) {
+			default: break;
+			case 0x03: case 0x04:	// Adjust enabled interrupts; disabled ones also cease to be pending.
+				interrupt_enable_ = (interrupt_enable_ & preserve) | word_value;
+				interrupt_pending_ &= interrupt_enable_;
+			break;
+			case 0x05: case 0x06:	// Resolve pending interrupts.
+				interrupt_pending_ &= (preserve | word_value);
+			break;
+			case 0x07: case 0x08:	// Resolve in-service interrupts.
+				interrupt_in_service_ &= (preserve | word_value);
+			break;
+			case 0x09: case 0x0a:	// Adjust interrupt mask.
+				interrupt_mask_ = (interrupt_mask_ & preserve) | word_value;
+			break;
+			case 0x0b:				// Set the interrupt vector, possibly changing end-of-interrupt mode.
+				interrupt_vector_ = value;
+
+				// If automatic end-of-interrupt mode has now been enabled, clear
+				// the in-process mask and re-evaluate.
+				if(interrupt_vector_ & 0x08) return;
+				interrupt_in_service_ = 0;
+			break;
+		}
+
+		// Whatever just happened may have affected the state of the interrupt line.
+		update_interrupts();
+		update_clocking_observer();
+		return;
+	}
+
+	constexpr int timer_prescales[] = {
+		1, 4, 10, 16, 50, 64, 100, 200
+	};
+
+	switch(address) {
+		// GPIP block: output and configuration of active edge and direction values.
+		case 0x00:
+			gpip_output_ = value;
+		break;
+		case 0x01:
+			gpip_active_edge_ = value;
+			reevaluate_gpip_interrupts();
+		break;
+		case 0x02:
+			gpip_direction_ = value;
+			reevaluate_gpip_interrupts();
+		break;
+
+		/* Interrupt block dealt with above. */
+		default: break;
+
+		// Timer block.
+		case 0x0c:
+		case 0x0d: {
+			const auto timer = address - 0xc;
+			const bool reset = value & 0x10;
+			timer_ab_control_[timer] = value;
+			switch(value & 0xf) {
+				case 0x0:	set_timer_mode(timer, TimerMode::Stopped, 1, reset);		break;
+				case 0x1:	set_timer_mode(timer, TimerMode::Delay, 4, reset);			break;
+				case 0x2:	set_timer_mode(timer, TimerMode::Delay, 10, reset);			break;
+				case 0x3:	set_timer_mode(timer, TimerMode::Delay, 16, reset);			break;
+				case 0x4:	set_timer_mode(timer, TimerMode::Delay, 50, reset);			break;
+				case 0x5:	set_timer_mode(timer, TimerMode::Delay, 64, reset);			break;
+				case 0x6:	set_timer_mode(timer, TimerMode::Delay, 100, reset);		break;
+				case 0x7:	set_timer_mode(timer, TimerMode::Delay, 200, reset);		break;
+				case 0x8:	set_timer_mode(timer, TimerMode::EventCount, 1, reset);		break;
+				case 0x9:	set_timer_mode(timer, TimerMode::PulseWidth, 4, reset);		break;
+				case 0xa:	set_timer_mode(timer, TimerMode::PulseWidth, 10, reset);	break;
+				case 0xb:	set_timer_mode(timer, TimerMode::PulseWidth, 16, reset);	break;
+				case 0xc:	set_timer_mode(timer, TimerMode::PulseWidth, 50, reset);	break;
+				case 0xd:	set_timer_mode(timer, TimerMode::PulseWidth, 64, reset);	break;
+				case 0xe:	set_timer_mode(timer, TimerMode::PulseWidth, 100, reset);	break;
+				case 0xf:	set_timer_mode(timer, TimerMode::PulseWidth, 200, reset);	break;
+			}
+		} break;
+		case 0x0e:
+			timer_cd_control_ = value;
+			set_timer_mode(3, (value & 7) ? TimerMode::Delay : TimerMode::Stopped, timer_prescales[value & 7], false);
+			set_timer_mode(2, ((value >> 4) & 7) ? TimerMode::Delay : TimerMode::Stopped, timer_prescales[(value >> 4) & 7], false);
+		break;
+		case 0x0f:	case 0x10:	case 0x11:	case 0x12:
+			set_timer_data(address - 0xf, value);
+		break;
+
+		// USART block: TODO.
+		case 0x13:		LOG("Write: sync character generator");	break;
+		case 0x14:		LOG("Write: USART control");			break;
+		case 0x15:		LOG("Write: receiver status");			break;
+		case 0x16:		LOG("Write: transmitter status");		break;
+		case 0x17:		LOG("Write: USART data");				break;
+	}
+
+	update_clocking_observer();
+}
+
+void MFP68901::run_for(HalfCycles time) {
+	cycles_left_ += time;
+
+	const int cycles = int(cycles_left_.flush<Cycles>().as_integral());
+	if(!cycles) return;
+
+	for(int c = 0; c < 4; ++c) {
+		if(timers_[c].mode >= TimerMode::Delay) {
+			// This code applies the timer prescaling only. prescale_count is used to count
+			// upwards rather than downwards for simplicity, but on the real hardware it's
+			// pretty safe to assume it actually counted downwards. So the clamp to 0 is
+			// because gymnastics may need to occur when the prescale value is altered, e.g.
+			// if a prescale of 256 is set and the prescale_count is currently 2 then the
+			// counter should roll over in 254 cycles. If the user at that point changes the
+			// prescale_count to 1 then the counter will need to be altered to -253 and
+			// allowed to keep counting up until it crosses both 0 and 1.
+			const int dividend = timers_[c].prescale_count + cycles;
+			const int decrements = std::max(dividend / timers_[c].prescale, 0);
+			if(decrements) {
+				decrement_timer(c, decrements);
+				timers_[c].prescale_count = dividend % timers_[c].prescale;
+			} else {
+				timers_[c].prescale_count += cycles;
+			}
+		}
+	}
+}
+
+HalfCycles MFP68901::get_next_sequence_point() {
+	return HalfCycles(-1);
+}
+
+// MARK: - Timers
+
+void MFP68901::set_timer_mode(int timer, TimerMode mode, int prescale, bool reset_timer) {
+	LOG("Timer " << timer << " mode set: " << int(mode) << "; prescale: " << prescale);
+	timers_[timer].mode = mode;
+	if(reset_timer) {
+		timers_[timer].prescale_count = 0;
+		timers_[timer].value = timers_[timer].reload_value;
+	} else {
+		// This hoop is because the prescale_count here goes upward but I'm assuming it goes downward in
+		// real hardware. Therefore this deals with the "switched to a lower prescaling" case whereby the
+		// old cycle should be allowed naturally to expire.
+		timers_[timer].prescale_count = prescale - (timers_[timer].prescale - timers_[timer].prescale_count);
+	}
+
+	timers_[timer].prescale = prescale;
+}
+
+void MFP68901::set_timer_data(int timer, uint8_t value) {
+	if(timers_[timer].mode == TimerMode::Stopped) {
+		timers_[timer].value = value;
+	}
+	timers_[timer].reload_value = value;
+}
+
+uint8_t MFP68901::get_timer_data(int timer) {
+	return timers_[timer].value;
+}
+
+void MFP68901::set_timer_event_input(int channel, bool value) {
+	if(timers_[channel].event_input == value) return;
+
+	timers_[channel].event_input = value;
+	if(timers_[channel].mode == TimerMode::EventCount && (value == !!(gpip_active_edge_ & (0x10 >> channel)))) {
+		// "The active state of the signal on TAI or TBI is dependent upon the associated
+		// Interrupt Channel’s edge bit (GPIP 4 for TAI and GPIP 3 for TBI [...] ).
+		// If the edge bit associated with the TAI or TBI input is a one, it will be active high.
+		decrement_timer(channel, 1);
+	}
+
+	// TODO:
+	//
+	// Altering the edge bit while the timer is in the event count mode can produce a count pulse.
+	// The interrupt channel associated with the input (I3 for I4 for TAI) is allowed to function normally.
+	// To count transitions reliably, the input must remain in each state (1/O) for a length of time equal
+	// to four periods of the timer clock.
+	//
+	// (the final bit probably explains 13 cycles of the DE to interrupt latency; not sure about the other ~15)
+}
+
+void MFP68901::decrement_timer(int timer, int amount) {
+	while(amount--) {
+		--timers_[timer].value;
+		if(timers_[timer].value < 1) {
+			switch(timer) {
+				case 0: begin_interrupts(Interrupt::TimerA);	break;
+				case 1: begin_interrupts(Interrupt::TimerB);	break;
+				case 2: begin_interrupts(Interrupt::TimerC);	break;
+				case 3: begin_interrupts(Interrupt::TimerD);	break;
+			}
+
+			// Re: reloading when in event counting mode; I found the data sheet thoroughly unclear on
+			// this, but it appears empirically to be correct. See e.g. Pompey Pirates menu 27.
+			if(timers_[timer].mode == TimerMode::Delay || timers_[timer].mode == TimerMode::EventCount) {
+				timers_[timer].value += timers_[timer].reload_value;	// TODO: properly.
+			}
+		}
+	}
+}
+
+// MARK: - GPIP
+void MFP68901::set_port_input(uint8_t input) {
+	gpip_input_ = input;
+	reevaluate_gpip_interrupts();
+}
+
+uint8_t MFP68901::get_port_output() {
+	return 0xff;	// TODO.
+}
+
+void MFP68901::reevaluate_gpip_interrupts() {
+	const uint8_t gpip_state = (gpip_input_ & ~gpip_direction_) ^ gpip_active_edge_;
+
+	// An interrupt is detected on any falling edge.
+	const uint8_t new_interrupt_mask = (gpip_state ^ gpip_interrupt_state_) & gpip_interrupt_state_;
+	if(new_interrupt_mask) {
+		begin_interrupts(
+			(new_interrupt_mask & 0x0f) |
+			((new_interrupt_mask & 0x30) << 2) |
+			((new_interrupt_mask & 0xc0) << 8)
+		);
+	}
+	gpip_interrupt_state_ = gpip_state;
+}
+
+// MARK: - Interrupts
+
+void MFP68901::begin_interrupts(int interrupt) {
+	interrupt_pending_ |= interrupt & interrupt_enable_;
+	update_interrupts();
+}
+
+void MFP68901::end_interrupts(int interrupt) {
+	interrupt_pending_ &= ~interrupt;
+	update_interrupts();
+}
+
+void MFP68901::update_interrupts() {
+	const auto old_interrupt_line = interrupt_line_;
+	const auto firing_interrupts = interrupt_pending_ & interrupt_mask_;
+
+	if(!firing_interrupts) {
+		interrupt_line_ = false;
+	} else {
+		if(interrupt_vector_ & 0x8) {
+			// Software interrupt mode: permit only if neither this interrupt
+			// nor a higher interrupt is currently in service.
+			const int highest_bit = msb16(firing_interrupts);
+			interrupt_line_ = !(interrupt_in_service_ & ~(highest_bit + highest_bit - 1));
+		} else {
+			// Auto-interrupt mode; just signal.
+			interrupt_line_ = true;
+		}
+	}
+
+	// Update the delegate if necessary.
+	if(interrupt_delegate_ && interrupt_line_ != old_interrupt_line) {
+		interrupt_delegate_->mfp68901_did_change_interrupt_status(this);
+	}
+}
+
+bool MFP68901::get_interrupt_line() {
+	return interrupt_line_;
+}
+
+int MFP68901::acknowledge_interrupt() {
+	if(!(interrupt_pending_ & interrupt_mask_)) {
+		return NoAcknowledgement;
+	}
+
+	const int mask = msb16(interrupt_pending_ & interrupt_mask_);
+
+	// Clear the pending bit regardless.
+	interrupt_pending_ &= ~mask;
+
+	// If this is software interrupt mode, set the in-service bit.
+	if(interrupt_vector_ & 0x8) {
+		interrupt_in_service_ |= mask;
+	}
+
+	update_interrupts();
+
+	int selected = 0;
+	while((1 << selected) != mask) ++selected;
+//	LOG("Interrupt acknowledged: " << selected);
+	return (interrupt_vector_ & 0xf0) | uint8_t(selected);
+}
+
+void MFP68901::set_interrupt_delegate(InterruptDelegate *delegate) {
+	interrupt_delegate_ = delegate;
+}

Components/68901/MFP68901.hpp

@@ -0,0 +1,187 @@
+//
+//  MFP68901.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 06/10/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef MFP68901_hpp
+#define MFP68901_hpp
+
+#include <cstdint>
+#include "../../ClockReceiver/ClockReceiver.hpp"
+#include "../../ClockReceiver/ClockingHintSource.hpp"
+
+namespace Motorola {
+namespace MFP68901 {
+
+class PortHandler {
+	public:
+		// TODO: announce changes in output.
+};
+
+/*!
+	Models the Motorola 68901 Multi-Function Peripheral ('MFP').
+*/
+class MFP68901: public ClockingHint::Source {
+	public:
+		/// @returns the result of a read from @c address.
+		uint8_t read(int address);
+
+		/// Performs a write of @c value to @c address.
+		void write(int address, uint8_t value);
+
+		/// Advances the MFP by the supplied number of HalfCycles.
+		void run_for(HalfCycles);
+
+		/// @returns the number of cycles until the next possible sequence point — the next time
+		/// at which the interrupt line _might_ change. This object conforms to ClockingHint::Source
+		/// so that mechanism can also be used to reduce the quantity of calls into this class.
+		///
+		/// @discussion TODO, alas.
+		HalfCycles get_next_sequence_point();
+
+		/// Sets the current level of either of the timer event inputs — TAI and TBI in datasheet terms.
+		void set_timer_event_input(int channel, bool value);
+
+		/// Sets a port handler, a receiver that will be notified upon any change in GPIP output.
+		///
+		/// @discussion TODO.
+		void set_port_handler(PortHandler *);
+
+		/// Sets the current input GPIP values.
+		void set_port_input(uint8_t);
+
+		/// @returns the current GPIP output values.
+		///
+		/// @discussion TODO.
+		uint8_t get_port_output();
+
+		/// @returns @c true if the interrupt output is currently active; @c false otherwise.s
+		bool get_interrupt_line();
+
+		static constexpr int NoAcknowledgement = 0x100;
+
+		/// Communicates an interrupt acknowledge cycle.
+		///
+		/// @returns the vector placed on the bus if any; @c NoAcknowledgement if nothing is loaded.
+		int acknowledge_interrupt();
+
+		struct InterruptDelegate {
+			/// Informs the delegate of a change in the interrupt line of the nominated MFP.
+			virtual void mfp68901_did_change_interrupt_status(MFP68901 *) = 0;
+		};
+		/// Sets a delegate that will be notified upon any change in the interrupt line.
+		void set_interrupt_delegate(InterruptDelegate *delegate);
+
+		// ClockingHint::Source.
+		ClockingHint::Preference preferred_clocking() final;
+
+	private:
+		// MARK: - Timers
+		enum class TimerMode {
+			Stopped, EventCount, Delay, PulseWidth
+		};
+		void set_timer_mode(int timer, TimerMode, int prescale, bool reset_timer);
+		void set_timer_data(int timer, uint8_t);
+		uint8_t get_timer_data(int timer);
+		void decrement_timer(int timer, int amount);
+
+		struct Timer {
+			TimerMode mode = TimerMode::Stopped;
+			uint8_t value = 0;
+			uint8_t reload_value = 0;
+			int prescale = 1;
+			int prescale_count = 1;
+			bool event_input = false;
+		} timers_[4];
+		uint8_t timer_ab_control_[2] = { 0, 0 };
+		uint8_t timer_cd_control_ = 0;
+
+		HalfCycles cycles_left_;
+
+		// MARK: - GPIP
+		uint8_t gpip_input_ = 0;
+		uint8_t gpip_output_ = 0;
+		uint8_t gpip_active_edge_ = 0;
+		uint8_t gpip_direction_ = 0;
+		uint8_t gpip_interrupt_state_ = 0;
+
+		void reevaluate_gpip_interrupts();
+
+		// MARK: - Interrupts
+
+		InterruptDelegate *interrupt_delegate_ = nullptr;
+
+		// Ad hoc documentation:
+		//
+		// An interrupt becomes pending if it is enabled at the time it occurs.
+		//
+		// If a pending interrupt is enabled in the interrupt mask, a processor
+		// interrupt is generated. Otherwise no processor interrupt is generated.
+		//
+		// (Disabling a bit in the enabled mask also instantaneously clears anything
+		// in the pending mask.)
+		//
+		// The user can write to the pending interrupt register; a write
+		// masks whatever is there — so you can disable bits but you cannot set them.
+		//
+		// If the vector register's 'S' bit is set then software end-of-interrupt mode applies:
+		// Acknowledgement of an interrupt clears that interrupt's pending bit, but also sets
+		// its in-service bit. That bit will remain set until the user writes a zero to its position.
+		// If any bits are set in the in-service register, then they will prevent lower-priority
+		// interrupts from being signalled to the CPU. Further interrupts of the same or a higher
+		// priority may occur.
+		//
+		// If the vector register's 'S' bit is clear then automatic end-of-interrupt mode applies:
+		// Acknowledgement of an interrupt will automatically clear the corresponding
+		// pending bit.
+		//
+		int interrupt_enable_ = 0;
+		int interrupt_pending_ = 0;
+		int interrupt_mask_ = 0;
+		int interrupt_in_service_ = 0;
+		bool interrupt_line_ = false;
+		uint8_t interrupt_vector_ = 0;
+
+		enum Interrupt {
+			GPIP0				= (1 << 0),
+			GPIP1				= (1 << 1),
+			GPIP2				= (1 << 2),
+			GPIP3				= (1 << 3),
+			TimerD				= (1 << 4),
+			TimerC				= (1 << 5),
+			GPIP4				= (1 << 6),
+			GPIP5				= (1 << 7),
+
+			TimerB				= (1 << 8),
+			TransmitError		= (1 << 9),
+			TransmitBufferEmpty	= (1 << 10),
+			ReceiveError		= (1 << 11),
+			ReceiveBufferFull	= (1 << 12),
+			TimerA				= (1 << 13),
+			GPIP6				= (1 << 14),
+			GPIP7				= (1 << 15),
+		};
+		void begin_interrupts(int interrupt);
+		void end_interrupts(int interrupt);
+		void update_interrupts();
+
+		/// @returns the most significant bit set in v, assuming it is one of the least significant 16.
+		inline static int msb16(int v) {
+			// Saturate all bits below the MSB.
+			v |= v >> 1;
+			v |= v >> 2;
+			v |= v >> 4;
+			v |= v >> 8;
+
+			// Throw away lesser bits.
+			return (v+1) >> 1;
+		}
+};
+
+}
+}
+
+#endif /* MFP68901_hpp */

Components/8255/i8255.hpp

@@ -27,7 +27,7 @@ template <class T> class i8255 {
 			Stores the value @c value to the register at @c address. If this causes a change in 8255 output
 			then the PortHandler will be informed.
 		*/
-		void set_register(int address, uint8_t value) {
+		void write(int address, uint8_t value) {
 			switch(address & 3) {
 				case 0:
 					if(!(control_ & 0x10)) {
@@ -60,7 +60,7 @@ template <class T> class i8255 {
 			Obtains the current value for the register at @c address. If this provides a reading
 			of input then the PortHandler will be queried.
 		*/
-		uint8_t get_register(int address) {
+		uint8_t read(int address) {
 			switch(address & 3) {
 				case 0:	return (control_ & 0x10) ? port_handler_.get_value(0) : outputs_[0];
 				case 1:	return (control_ & 0x02) ? port_handler_.get_value(1) : outputs_[1];

Components/8272/i8272.cpp

@@ -7,9 +7,8 @@
 //
 
 #include "i8272.hpp"
-//#include "../../Storage/Disk/Encodings/MFM/Encoder.hpp"
 
-#include <cstdio>
+#include "../../Outputs/Log.hpp"
 
 using namespace Intel::i8272;
 
@@ -83,8 +82,10 @@ i8272::i8272(BusHandler &bus_handler, Cycles clock_rate) :
 	posit_event(static_cast<int>(Event8272::CommandByte));
 }
 
-bool i8272::is_sleeping() {
-	return is_sleeping_ && Storage::Disk::MFMController::is_sleeping();
+ClockingHint::Preference i8272::preferred_clocking() {
+	const auto mfm_controller_preferred_clocking = Storage::Disk::MFMController::preferred_clocking();
+	if(mfm_controller_preferred_clocking != ClockingHint::Preference::None) return mfm_controller_preferred_clocking;
+	return is_sleeping_ ? ClockingHint::Preference::None : ClockingHint::Preference::JustInTime;
 }
 
 void i8272::run_for(Cycles cycles) {
@@ -94,11 +95,11 @@ void i8272::run_for(Cycles cycles) {
 
 	// check for an expired timer
 	if(delay_time_ > 0) {
-		if(cycles.as_int() >= delay_time_) {
+		if(cycles.as_integral() >= delay_time_) {
 			delay_time_ = 0;
 			posit_event(static_cast<int>(Event8272::Timer));
 		} else {
-			delay_time_ -= cycles.as_int();
+			delay_time_ -= cycles.as_integral();
 		}
 	}
 
@@ -107,13 +108,13 @@ void i8272::run_for(Cycles cycles) {
 		int drives_left = drives_seeking_;
 		for(int c = 0; c < 4; c++) {
 			if(drives_[c].phase == Drive::Seeking) {
-				drives_[c].step_rate_counter += cycles.as_int();
-				int steps = drives_[c].step_rate_counter / (8000 * step_rate_time_);
+				drives_[c].step_rate_counter += cycles.as_integral();
+				auto steps = drives_[c].step_rate_counter / (8000 * step_rate_time_);
 				drives_[c].step_rate_counter %= (8000 * step_rate_time_);
 				while(steps--) {
 					// Perform a step.
 					int direction = (drives_[c].target_head_position < drives_[c].head_position) ? -1 : 1;
-					printf("Target %d versus believed %d\n", drives_[c].target_head_position, drives_[c].head_position);
+					LOG("Target " << PADDEC(0) << drives_[c].target_head_position << " versus believed " << static_cast<int>(drives_[c].head_position));
 					select_drive(c);
 					get_drive().step(Storage::Disk::HeadPosition(direction));
 					if(drives_[c].target_head_position >= 0) drives_[c].head_position += direction;
@@ -140,12 +141,12 @@ void i8272::run_for(Cycles cycles) {
 			int head = c&1;
 
 			if(drives_[drive].head_unload_delay[head] > 0) {
-				if(cycles.as_int() >= drives_[drive].head_unload_delay[head]) {
+				if(cycles.as_integral() >= drives_[drive].head_unload_delay[head]) {
 					drives_[drive].head_unload_delay[head] = 0;
 					drives_[drive].head_is_loaded[head] = false;
 					head_timers_running_--;
 				} else {
-					drives_[drive].head_unload_delay[head] -= cycles.as_int();
+					drives_[drive].head_unload_delay[head] -= cycles.as_integral();
 				}
 				timers_left--;
 				if(!timers_left) break;
@@ -159,10 +160,10 @@ void i8272::run_for(Cycles cycles) {
 	}
 
 	is_sleeping_ = !delay_time_ && !drives_seeking_ && !head_timers_running_;
-	if(is_sleeping_) update_sleep_observer();
+	if(is_sleeping_) update_clocking_observer();
 }
 
-void i8272::set_register(int address, uint8_t value) {
+void i8272::write(int address, uint8_t value) {
 	// don't consider attempted sets to the status register
 	if(!address) return;
 
@@ -180,7 +181,7 @@ void i8272::set_register(int address, uint8_t value) {
 	}
 }
 
-uint8_t i8272::get_register(int address) {
+uint8_t i8272::read(int address) {
 	if(address) {
 		if(result_stack_.empty()) return 0xff;
 		uint8_t result = result_stack_.back();
@@ -198,7 +199,7 @@ uint8_t i8272::get_register(int address) {
 
 #define MS_TO_CYCLES(x)			x * 8000
 #define WAIT_FOR_EVENT(mask)	resume_point_ = __LINE__; interesting_event_mask_ = static_cast<int>(mask); return; case __LINE__:
-#define WAIT_FOR_TIME(ms)		resume_point_ = __LINE__; interesting_event_mask_ = static_cast<int>(Event8272::Timer); delay_time_ = MS_TO_CYCLES(ms); is_sleeping_ = false; update_sleep_observer(); case __LINE__: if(delay_time_) return;
+#define WAIT_FOR_TIME(ms)		resume_point_ = __LINE__; interesting_event_mask_ = static_cast<int>(Event8272::Timer); delay_time_ = MS_TO_CYCLES(ms); is_sleeping_ = false; update_clocking_observer(); case __LINE__: if(delay_time_) return;
 
 #define PASTE(x, y) x##y
 #define CONCAT(x, y) PASTE(x, y)
@@ -257,7 +258,7 @@ uint8_t i8272::get_register(int address) {
 		if(drives_[active_drive_].head_unload_delay[active_head_] == 0) {	\
 			head_timers_running_++;	\
 			is_sleeping_ = false;	\
-			update_sleep_observer();	\
+			update_clocking_observer();	\
 		}	\
 		drives_[active_drive_].head_unload_delay[active_head_] = MS_TO_CYCLES(head_unload_time_);\
 	}
@@ -291,7 +292,7 @@ void i8272::posit_event(int event_type) {
 			WAIT_FOR_EVENT(Event8272::CommandByte)
 			SetBusy();
 
-			static const std::size_t required_lengths[32] = {
+			static constexpr std::size_t required_lengths[32] = {
 				0,	0,	9,	3,	2,	9,	9,	2,
 				1,	9,	2,	0,	9,	6,	0,	3,
 				0,	9,	0,	0,	0,	0,	0,	0,
@@ -384,17 +385,17 @@ void i8272::posit_event(int event_type) {
 		// the index hole limit is breached or a sector is found with a cylinder, head, sector and size equal to the
 		// values in the internal registers.
 			index_hole_limit_ = 2;
-//			printf("Seeking %02x %02x %02x %02x\n", cylinder_, head_, sector_, size_);
+//			LOG("Seeking " << PADDEC(0) << cylinder_ << " " << head_ " " << sector_ << " " << size_);
 		find_next_sector:
 			FIND_HEADER();
 			if(!index_hole_limit_) {
 				// Two index holes have passed wihout finding the header sought.
-//				printf("Not found\n");
+//				LOG("Not found");
 				SetNoData();
 				goto abort;
 			}
 			index_hole_count_ = 0;
-//			printf("Header\n");
+//			LOG("Header");
 			READ_HEADER();
 			if(index_hole_count_) {
 				// This implies an index hole was sighted within the header. Error out.
@@ -405,11 +406,11 @@ void i8272::posit_event(int event_type) {
 				// This implies a CRC error in the header; mark as such but continue.
 				SetDataError();
 			}
-//			printf("Considering %02x %02x %02x %02x [%04x]\n", header_[0], header_[1], header_[2], header_[3], get_crc_generator().get_value());
+//			LOG("Considering << PADHEX(2) << header_[0] << " " << header_[1] << " " << header_[2] << " " << header_[3] << " [" << get_crc_generator().get_value() << "]");
 			if(header_[0] != cylinder_ || header_[1] != head_ || header_[2] != sector_ || header_[3] != size_) goto find_next_sector;
 
 			// Branch to whatever is supposed to happen next
-//			printf("Proceeding\n");
+//			LOG("Proceeding");
 			switch(command_[0] & 0x1f) {
 				case CommandReadData:
 				case CommandReadDeletedData:
@@ -423,7 +424,13 @@ void i8272::posit_event(int event_type) {
 
 	// Performs the read data or read deleted data command.
 	read_data:
-			printf("Read [deleted] data [%02x %02x %02x %02x ... %02x %02x]\n", command_[2], command_[3], command_[4], command_[5], command_[6], command_[8]);
+			LOG(PADHEX(2) << "Read [deleted] data ["
+				<< static_cast<int>(command_[2]) << " "
+				<< static_cast<int>(command_[3]) << " "
+				<< static_cast<int>(command_[4]) << " "
+				<< static_cast<int>(command_[5]) << " ... "
+				<< static_cast<int>(command_[6]) << " "
+				<< static_cast<int>(command_[8]) << "]");
 		read_next_data:
 			goto read_write_find_header;
 
@@ -507,7 +514,13 @@ void i8272::posit_event(int event_type) {
 			goto post_st012chrn;
 
 	write_data:
-			printf("Write [deleted] data [%02x %02x %02x %02x ... %02x %02x]\n", command_[2], command_[3], command_[4], command_[5], command_[6], command_[8]);
+			LOG(PADHEX(2) << "Write [deleted] data ["
+				<< static_cast<int>(command_[2]) << " "
+				<< static_cast<int>(command_[3]) << " "
+				<< static_cast<int>(command_[4]) << " "
+				<< static_cast<int>(command_[5]) << " ... "
+				<< static_cast<int>(command_[6]) << " "
+				<< static_cast<int>(command_[8]) << "]");
 
 			if(get_drive().get_is_read_only()) {
 				SetNotWriteable();
@@ -542,7 +555,7 @@ void i8272::posit_event(int event_type) {
 				goto write_loop;
 			}
 
-			printf("Wrote %d bytes\n", distance_into_section_);
+			LOG("Wrote " << PADDEC(0) << distance_into_section_ << " bytes");
 			write_crc();
 			expects_input_ = false;
 			WAIT_FOR_EVENT(Event::DataWritten);
@@ -558,7 +571,7 @@ void i8272::posit_event(int event_type) {
 	// Performs the read ID command.
 	read_id:
 		// Establishes the drive and head being addressed, and whether in double density mode.
-			printf("Read ID [%02x %02x]\n", command_[0], command_[1]);
+			LOG(PADHEX(2) << "Read ID [" << static_cast<int>(command_[0]) << " " << static_cast<int>(command_[1]) << "]");
 
 		// Sets a maximum index hole limit of 2 then waits either until it finds a header mark or sees too many index holes.
 		// If a header mark is found, reads in the following bytes that produce a header. Otherwise branches to data not found.
@@ -580,7 +593,11 @@ void i8272::posit_event(int event_type) {
 
 	// Performs read track.
 	read_track:
-			printf("Read track [%02x %02x %02x %02x]\n", command_[2], command_[3], command_[4], command_[5]);
+			LOG(PADHEX(2) << "Read track ["
+				<< static_cast<int>(command_[2]) << " "
+				<< static_cast<int>(command_[3]) << " "
+				<< static_cast<int>(command_[4]) << " "
+				<< static_cast<int>(command_[5]) << "]");
 
 			// Wait for the index hole.
 			WAIT_FOR_EVENT(Event::IndexHole);
@@ -621,7 +638,7 @@ void i8272::posit_event(int event_type) {
 
 	// Performs format [/write] track.
 	format_track:
-			printf("Format track\n");
+			LOG("Format track");
 			if(get_drive().get_is_read_only()) {
 				SetNotWriteable();
 				goto abort;
@@ -665,7 +682,12 @@ void i8272::posit_event(int event_type) {
 				break;
 			}
 
-			printf("W: %02x %02x %02x %02x, %04x\n", header_[0], header_[1], header_[2], header_[3], get_crc_generator().get_value());
+			LOG(PADHEX(2) << "W:"
+				<< static_cast<int>(header_[0]) << " "
+				<< static_cast<int>(header_[1]) << " "
+				<< static_cast<int>(header_[2]) << " "
+				<< static_cast<int>(header_[3]) << ", "
+				<< get_crc_generator().get_value());
 			write_crc();
 
 			// Write the sector body.
@@ -697,15 +719,15 @@ void i8272::posit_event(int event_type) {
 		goto post_st012chrn;
 
 	scan_low:
-		printf("Scan low unimplemented!!\n");
+		ERROR("Scan low unimplemented!!");
 		goto wait_for_command;
 
 	scan_low_or_equal:
-		printf("Scan low or equal unimplemented!!\n");
+		ERROR("Scan low or equal unimplemented!!");
 		goto wait_for_command;
 
 	scan_high_or_equal:
-		printf("Scan high or equal unimplemented!!\n");
+		ERROR("Scan high or equal unimplemented!!");
 		goto wait_for_command;
 
 	// Performs both recalibrate and seek commands. These commands occur asynchronously, so the actual work
@@ -720,7 +742,7 @@ void i8272::posit_event(int event_type) {
 				if(drives_[drive].phase != Drive::Seeking) {
 					drives_seeking_++;
 					is_sleeping_ = false;
-					update_sleep_observer();
+					update_clocking_observer();
 				}
 
 				// Set currently seeking, with a step to occur right now (yes, it sounds like jamming these
@@ -736,11 +758,11 @@ void i8272::posit_event(int event_type) {
 				// up in run_for understands to mean 'keep going until track 0 is active').
 				if(command_.size() > 2) {
 					drives_[drive].target_head_position = command_[2];
-					printf("Seek to %02x\n", command_[2]);
+					LOG(PADHEX(2) << "Seek to " << static_cast<int>(command_[2]));
 				} else {
 					drives_[drive].target_head_position = -1;
 					drives_[drive].head_position = 0;
-					printf("Recalibrate\n");
+					LOG("Recalibrate");
 				}
 
 				// Check whether any steps are even needed; if not then mark as completed already.
@@ -753,7 +775,7 @@ void i8272::posit_event(int event_type) {
 
 	// Performs sense interrupt status.
 	sense_interrupt_status:
-			printf("Sense interrupt status\n");
+			LOG("Sense interrupt status");
 			{
 				// Find the first drive that is in the CompletedSeeking state.
 				int found_drive = -1;
@@ -781,7 +803,7 @@ void i8272::posit_event(int event_type) {
 	// Performs specify.
 	specify:
 		// Just store the values, and terminate the command.
-			printf("Specify\n");
+			LOG("Specify");
 			step_rate_time_ = 16 - (command_[1] >> 4);			// i.e. 1 to 16ms
 			head_unload_time_ = (command_[1] & 0x0f) << 4;		// i.e. 16 to 240ms
 			head_load_time_ = command_[2] & ~1;					// i.e. 2 to 254 ms in increments of 2ms
@@ -792,7 +814,7 @@ void i8272::posit_event(int event_type) {
 			goto wait_for_command;
 
 	sense_drive_status:
-			printf("Sense drive status\n");
+			LOG("Sense drive status");
 			{
 				int drive = command_[1] & 3;
 				select_drive(drive);
@@ -831,11 +853,11 @@ void i8272::posit_event(int event_type) {
 	// Posts whatever is in result_stack_ as a result phase. Be aware that it is a stack, so the
 	// last thing in it will be returned first.
 	post_result:
-			printf("Result to %02x, main %02x: ", command_[0] & 0x1f, main_status_);
+			LOGNBR(PADHEX(2) << "Result to " << static_cast<int>(command_[0] & 0x1f) << ", main " << static_cast<int>(main_status_) << "; ");
 			for(std::size_t c = 0; c < result_stack_.size(); c++) {
-				printf("%02x ", result_stack_[result_stack_.size() - 1 - c]);
+				LOGNBR(" " << static_cast<int>(result_stack_[result_stack_.size() - 1 - c]));
 			}
-			printf("\n");
+			LOGNBR(std::endl);
 
 			// Set ready to send data to the processor, no longer in non-DMA execution phase.
 			is_executing_ = false;
@@ -843,7 +865,7 @@ void i8272::posit_event(int event_type) {
 			SetDataRequest();
 			SetDataDirectionToProcessor();
 
-			// The actual stuff of unwinding result_stack_ is handled by ::get_register; wait
+			// The actual stuff of unwinding result_stack_ is handled by ::read; wait
 			// until the processor has read all result bytes.
 			WAIT_FOR_EVENT(Event8272::ResultEmpty);
 

Components/8272/i8272.hpp

@@ -24,7 +24,7 @@ class BusHandler {
 		virtual void set_interrupt(bool irq) {}
 };
 
-class i8272: public Storage::Disk::MFMController {
+class i8272 : public Storage::Disk::MFMController {
 	public:
 		i8272(BusHandler &bus_handler, Cycles clock_rate);
 
@@ -33,13 +33,13 @@ class i8272: public Storage::Disk::MFMController {
 		void set_data_input(uint8_t value);
 		uint8_t get_data_output();
 
-		void set_register(int address, uint8_t value);
-		uint8_t get_register(int address);
+		void write(int address, uint8_t value);
+		uint8_t read(int address);
 
 		void set_dma_acknowledge(bool dack);
 		void set_terminal_count(bool tc);
 
-		bool is_sleeping();
+		ClockingHint::Preference preferred_clocking() final;
 
 	protected:
 		virtual void select_drive(int number) = 0;
@@ -67,13 +67,13 @@ class i8272: public Storage::Disk::MFMController {
 			ResultEmpty = (1 << 5),
 			NoLongerReady = (1 << 6)
 		};
-		void posit_event(int type);
+		void posit_event(int type) final;
 		int interesting_event_mask_ = static_cast<int>(Event8272::CommandByte);
 		int resume_point_ = 0;
 		bool is_access_command_ = false;
 
 		// The counter used for ::Timer events.
-		int delay_time_ = 0;
+		Cycles::IntType delay_time_ = 0;
 
 		// The connected drives.
 		struct Drive {
@@ -89,12 +89,12 @@ class i8272: public Storage::Disk::MFMController {
 			bool seek_failed = false;
 
 			// Seeking: transient state.
-			int step_rate_counter = 0;
+			Cycles::IntType step_rate_counter = 0;
 			int steps_taken = 0;
 			int target_head_position = 0;	// either an actual number, or -1 to indicate to step until track zero
 
 			// Head state.
-			int head_unload_delay[2] = {0, 0};
+			Cycles::IntType head_unload_delay[2] = {0, 0};
 			bool head_is_loaded[2] = {false, false};
 
 		} drives_[4];

Components/8530/z8530.cpp

@@ -0,0 +1,268 @@
+//
+//  8530.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 07/06/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#include "z8530.hpp"
+
+#include "../../Outputs/Log.hpp"
+
+using namespace Zilog::SCC;
+
+void z8530::reset() {
+	// TODO.
+}
+
+bool z8530::get_interrupt_line() {
+	return
+		(master_interrupt_control_ & 0x8) &&
+		(
+			channels_[0].get_interrupt_line() ||
+			channels_[1].get_interrupt_line()
+		);
+}
+
+std::uint8_t z8530::read(int address) {
+	if(address & 2) {
+		// Read data register for channel
+		return 0x00;
+	} else {
+		// Read control register for channel.
+		uint8_t result = 0;
+
+		switch(pointer_) {
+			default:
+				result = channels_[address & 1].read(address & 2, pointer_);
+			break;
+
+			case 2:		// Handled non-symmetrically between channels.
+				if(address & 1) {
+					LOG("[SCC] Unimplemented: register 2 status bits");
+				} else {
+					result = interrupt_vector_;
+
+					// Modify the vector if permitted.
+//					if(master_interrupt_control_ & 1) {
+						for(int port = 0; port < 2; ++port) {
+							// TODO: the logic below assumes that DCD is the only implemented interrupt. Fix.
+							if(channels_[port].get_interrupt_line()) {
+								const uint8_t shift = 1 + 3*((master_interrupt_control_ & 0x10) >> 4);
+								const uint8_t mask = uint8_t(~(7 << shift));
+								result = uint8_t(
+									(result & mask) |
+									((1 | ((port == 1) ? 4 : 0)) << shift)
+								);
+								break;
+							}
+						}
+//					}
+				}
+			break;
+		}
+
+		pointer_ = 0;
+		update_delegate();
+		return result;
+	}
+
+	return 0x00;
+}
+
+void z8530::write(int address, std::uint8_t value) {
+	if(address & 2) {
+		// Write data register for channel.
+	} else {
+		// Write control register for channel.
+
+		// Most registers are per channel, but a couple are shared; sever
+		// them here.
+		switch(pointer_) {
+			default:
+				channels_[address & 1].write(address & 2, pointer_, value);
+			break;
+
+			case 2:	// Interrupt vector register; shared between both channels.
+				interrupt_vector_ = value;
+				LOG("[SCC] Interrupt vector set to " << PADHEX(2) << int(value));
+			break;
+
+			case 9:	// Master interrupt and reset register; also shared between both channels.
+				LOG("[SCC] Master interrupt and reset register: " << PADHEX(2) << int(value));
+				master_interrupt_control_ = value;
+			break;
+		}
+
+		// The pointer number resets to 0 after every access, but if it is zero
+		// then crib at least the next set of pointer bits (which, similarly, are shared
+		// between the two channels).
+		if(pointer_) {
+			pointer_ = 0;
+		} else {
+			// The lowest three bits are the lowest three bits of the pointer.
+			pointer_ = value & 7;
+
+			// If the command part of the byte is a 'point high', also set the
+			// top bit of the pointer.
+			if(((value >> 3)&7) == 1) {
+				pointer_ |= 8;
+			}
+		}
+	}
+	update_delegate();
+}
+
+void z8530::set_dcd(int port, bool level) {
+	channels_[port].set_dcd(level);
+	update_delegate();
+}
+
+// MARK: - Channel implementations
+
+uint8_t z8530::Channel::read(bool data, uint8_t pointer) {
+	// If this is a data read, just return it.
+	if(data) {
+		return data_;
+	} else {
+		// Otherwise, this is a control read...
+		switch(pointer) {
+			default:
+				LOG("[SCC] Unrecognised control read from register " << int(pointer));
+			return 0x00;
+
+			case 0:
+			return dcd_ ? 0x8 : 0x0;
+
+			case 0xf:
+			return external_interrupt_status_;
+		}
+	}
+
+	return 0x00;
+}
+
+void z8530::Channel::write(bool data, uint8_t pointer, uint8_t value) {
+	if(data) {
+		data_ = value;
+		return;
+	} else {
+		switch(pointer) {
+			default:
+				LOG("[SCC] Unrecognised control write: " << PADHEX(2) << int(value) << " to register " << int(pointer));
+			break;
+
+			case 0x0:	// Write register 0 — CRC reset and other functions.
+				// Decode CRC reset instructions.
+				switch(value >> 6) {
+					default:	/* Do nothing. */		break;
+					case 1:
+						LOG("[SCC] TODO: reset Rx CRC checker.");
+					break;
+					case 2:
+						LOG("[SCC] TODO: reset Tx CRC checker.");
+					break;
+					case 3:
+						LOG("[SCC] TODO: reset Tx underrun/EOM latch.");
+					break;
+				}
+
+				// Decode command code.
+				switch((value >> 3)&7) {
+					default:	/* Do nothing. */		break;
+					case 2:
+//						LOG("[SCC] reset ext/status interrupts.");
+						external_status_interrupt_ = false;
+						external_interrupt_status_ = 0;
+					break;
+					case 3:
+						LOG("[SCC] TODO: send abort (SDLC).");
+					break;
+					case 4:
+						LOG("[SCC] TODO: enable interrupt on next Rx character.");
+					break;
+					case 5:
+						LOG("[SCC] TODO: reset Tx interrupt pending.");
+					break;
+					case 6:
+						LOG("[SCC] TODO: reset error.");
+					break;
+					case 7:
+						LOG("[SCC] TODO: reset highest IUS.");
+					break;
+				}
+			break;
+
+			case 0x1:	// Write register 1 — Transmit/Receive Interrupt and Data Transfer Mode Definition.
+				interrupt_mask_ = value;
+			break;
+
+			case 0x4:	// Write register 4 — Transmit/Receive Miscellaneous Parameters and Modes.
+				// Bits 0 and 1 select parity mode.
+				if(!(value&1)) {
+					parity_ = Parity::Off;
+				} else {
+					parity_ = (value&2) ? Parity::Even : Parity::Odd;
+				}
+
+				// Bits 2 and 3 select stop bits.
+				switch((value >> 2)&3) {
+					default:	stop_bits_ = StopBits::Synchronous;			break;
+					case 1:		stop_bits_ = StopBits::OneBit;				break;
+					case 2:		stop_bits_ = StopBits::OneAndAHalfBits;		break;
+					case 3:		stop_bits_ = StopBits::TwoBits;				break;
+				}
+
+				// Bits 4 and 5 pick a sync mode.
+				switch((value >> 4)&3) {
+					default:	sync_mode_ = Sync::Monosync;	break;
+					case 1:		sync_mode_ = Sync::Bisync;		break;
+					case 2:		sync_mode_ = Sync::SDLC;		break;
+					case 3:		sync_mode_ = Sync::External;	break;
+				}
+
+				// Bits 6 and 7 select a clock rate multiplier, unless synchronous
+				// mode is enabled (and this is ignored if sync mode is external).
+				if(stop_bits_ == StopBits::Synchronous) {
+					clock_rate_multiplier_ = 1;
+				} else {
+					switch((value >> 6)&3) {
+						default:	clock_rate_multiplier_ = 1;		break;
+						case 1:		clock_rate_multiplier_ = 16;	break;
+						case 2:		clock_rate_multiplier_ = 32;	break;
+						case 3:		clock_rate_multiplier_ = 64;	break;
+					}
+				}
+			break;
+
+			case 0xf:	// Write register 15 — External/Status Interrupt Control.
+				external_interrupt_mask_ = value;
+			break;
+		}
+	}
+}
+
+void z8530::Channel::set_dcd(bool level) {
+	if(dcd_ == level) return;
+	dcd_ = level;
+
+	if(external_interrupt_mask_ & 0x8) {
+		external_status_interrupt_ = true;
+		external_interrupt_status_ |= 0x8;
+	}
+}
+
+bool z8530::Channel::get_interrupt_line() {
+	return
+		(interrupt_mask_ & 1) && external_status_interrupt_;
+	// TODO: other potential causes of an interrupt.
+}
+
+void z8530::update_delegate() {
+	const bool interrupt_line = get_interrupt_line();
+	if(interrupt_line != previous_interrupt_line_) {
+		previous_interrupt_line_ = interrupt_line;
+		if(delegate_) delegate_->did_change_interrupt_status(this, interrupt_line);
+	}
+}

Components/8530/z8530.hpp

@@ -0,0 +1,99 @@
+//
+//  z8530.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 07/06/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef z8530_hpp
+#define z8530_hpp
+
+#include <cstdint>
+
+namespace Zilog {
+namespace SCC {
+
+/*!
+	Models the Zilog 8530 SCC, a serial adaptor.
+*/
+class z8530 {
+	public:
+		/*
+			**Interface for emulated machine.**
+
+			Notes on addressing below:
+
+			There's no inherent ordering of the two 'address' lines,
+			A/B and C/D, but the methods below assume:
+
+				A/B = A0
+				C/D = A1
+		*/
+		std::uint8_t read(int address);
+		void write(int address, std::uint8_t value);
+		void reset();
+		bool get_interrupt_line();
+
+		struct Delegate {
+			virtual void did_change_interrupt_status(z8530 *, bool new_status) = 0;
+		};
+		void set_delegate(Delegate *delegate) {
+			delegate_ = delegate;
+		}
+
+		/*
+			**Interface for serial port input.**
+		*/
+		void set_dcd(int port, bool level);
+
+	private:
+		class Channel {
+			public:
+				uint8_t read(bool data, uint8_t pointer);
+				void write(bool data, uint8_t pointer, uint8_t value);
+				void set_dcd(bool level);
+				bool get_interrupt_line();
+
+			private:
+				uint8_t data_ = 0xff;
+
+				enum class Parity {
+					Even, Odd, Off
+				} parity_ = Parity::Off;
+
+				enum class StopBits {
+					Synchronous, OneBit, OneAndAHalfBits, TwoBits
+				} stop_bits_ = StopBits::Synchronous;
+
+				enum class Sync {
+					Monosync, Bisync, SDLC, External
+				} sync_mode_ = Sync::Monosync;
+
+				int clock_rate_multiplier_ = 1;
+
+				uint8_t interrupt_mask_ = 0;			// i.e. Write Register 0x1.
+
+				uint8_t external_interrupt_mask_ = 0;	// i.e. Write Register 0xf.
+				bool external_status_interrupt_ = false;
+				uint8_t external_interrupt_status_ = 0;
+
+				bool dcd_ = false;
+		} channels_[2];
+
+		uint8_t pointer_ = 0;
+
+		uint8_t interrupt_vector_ = 0;
+
+		uint8_t master_interrupt_control_ = 0;
+
+		bool previous_interrupt_line_ = false;
+		void update_delegate();
+		Delegate *delegate_ = nullptr;
+};
+
+}
+}
+
+
+#endif /* z8530_hpp */

Components/9918/9918.hpp

@@ -17,6 +17,7 @@
 #include <cstdint>
 
 namespace TI {
+namespace TMS {
 
 /*!
 	Provides emulation of the TMS9918a, TMS9928 and TMS9929. Likely in the future to be the
@@ -29,30 +30,25 @@ namespace TI {
 	These chips have only one non-on-demand interaction with the outside world: an interrupt line.
 	See get_time_until_interrupt and get_interrupt_line for asynchronous operation options.
 */
-class TMS9918: public TMS9918Base {
+class TMS9918: public Base {
 	public:
-		enum Personality {
-			TMS9918A,	// includes the 9928 and 9929; set TV standard and output device as desired.
-		};
-
 		/*!
 			Constructs an instance of the drive controller that behaves according to personality @c p.
 			@param p The type of controller to emulate.
 		*/
 		TMS9918(Personality p);
 
-		enum TVStandard {
-			/*! i.e. 50Hz output at around 312.5 lines/field */
-			PAL,
-			/*! i.e. 60Hz output at around 262.5 lines/field */
-			NTSC
-		};
-
 		/*! Sets the TV standard for this TMS, if that is hard-coded in hardware. */
 		void set_tv_standard(TVStandard standard);
 
-		/*! Provides the CRT this TMS is connected to. */
-		Outputs::CRT::CRT *get_crt();
+		/*! Sets the scan target this TMS will post content to. */
+		void set_scan_target(Outputs::Display::ScanTarget *);
+
+		/// Gets the current scan status.
+		Outputs::Display::ScanStatus get_scaled_scan_status() const;
+
+		/*! Sets the type of display the CRT will request. */
+		void set_display_type(Outputs::Display::DisplayType);
 
 		/*!
 			Runs the VCP for the number of cycles indicate; it is an implicit assumption of the code
@@ -61,26 +57,46 @@ class TMS9918: public TMS9918Base {
 		void run_for(const HalfCycles cycles);
 
 		/*! Sets a register value. */
-		void set_register(int address, uint8_t value);
+		void write(int address, uint8_t value);
 
 		/*! Gets a register value. */
-		uint8_t get_register(int address);
+		uint8_t read(int address);
+
+		/*! Gets the current scan line; provided by the Master System only. */
+		uint8_t get_current_line();
+
+		/*! Gets the current latched horizontal counter; provided by the Master System only. */
+		uint8_t get_latched_horizontal_counter();
+
+		/*! Latches the current horizontal counter. */
+		void latch_horizontal_counter();
 
 		/*!
-			Returns the amount of time until get_interrupt_line would next return true if
-			there are no interceding calls to set_register or get_register.
+			Returns the amount of time until @c get_interrupt_line would next return true if
+			there are no interceding calls to @c write or to @c read.
 
 			If get_interrupt_line is true now, returns zero. If get_interrupt_line would
 			never return true, returns -1.
 		*/
 		HalfCycles get_time_until_interrupt();
 
+		/*!
+			Returns the amount of time until the nominated line interrupt position is
+			reached on line @c line. If no line interrupt position is defined for
+			this VDP, returns the time until the 'beginning' of that line, whatever
+			that may mean.
+
+			@line is relative to the first pixel line of the display and may be negative.
+		*/
+		HalfCycles get_time_until_line(int line);
+
 		/*!
 			@returns @c true if the interrupt line is currently active; @c false otherwise.
 		*/
 		bool get_interrupt_line();
 };
 
-};
+}
+}
 
 #endif /* TMS9918_hpp */

Components/9918/Implementation/9918Base.hpp

@@ -12,90 +12,848 @@
 #include "../../../Outputs/CRT/CRT.hpp"
 #include "../../../ClockReceiver/ClockReceiver.hpp"
 
+#include <cassert>
 #include <cstdint>
 #include <memory>
+#include <vector>
 
 namespace TI {
+namespace TMS {
+
+enum Personality {
+	TMS9918A,	// includes the 9928 and 9929; set TV standard and output device as desired.
+	V9938,
+	V9958,
+	SMSVDP,
+	SMS2VDP,
+	GGVDP,
+};
+
+enum class TVStandard {
+	/*! i.e. 50Hz output at around 312.5 lines/field */
+	PAL,
+	/*! i.e. 60Hz output at around 262.5 lines/field */
+	NTSC
+};
+
+#define is_sega_vdp(x) ((x) >= SMSVDP)
+
+class Base {
+	public:
+		static const uint32_t palette_pack(uint8_t r, uint8_t g, uint8_t b) {
+			uint32_t result = 0;
+			uint8_t *const result_ptr = reinterpret_cast<uint8_t *>(&result);
+			result_ptr[0] = r;
+			result_ptr[1] = g;
+			result_ptr[2] = b;
+			result_ptr[3] = 0;
+			return result;
+		}
 
-class TMS9918Base {
 	protected:
-		TMS9918Base();
+		const static int output_lag = 11;	// i.e. pixel output will occur 11 cycles after corresponding data read.
 
-		std::unique_ptr<Outputs::CRT::CRT> crt_;
+		// The default TMS palette.
+		const uint32_t palette[16] = {
+			palette_pack(0, 0, 0),
+			palette_pack(0, 0, 0),
+			palette_pack(33, 200, 66),
+			palette_pack(94, 220, 120),
 
-		uint8_t ram_[16384];
+			palette_pack(84, 85, 237),
+			palette_pack(125, 118, 252),
+			palette_pack(212, 82, 77),
+			palette_pack(66, 235, 245),
 
+			palette_pack(252, 85, 84),
+			palette_pack(255, 121, 120),
+			palette_pack(212, 193, 84),
+			palette_pack(230, 206, 128),
+
+			palette_pack(33, 176, 59),
+			palette_pack(201, 91, 186),
+			palette_pack(204, 204, 204),
+			palette_pack(255, 255, 255)
+		};
+
+		Base(Personality p);
+
+		const Personality personality_;
+		Outputs::CRT::CRT crt_;
+		TVStandard tv_standard_ = TVStandard::NTSC;
+
+		// Holds the contents of this VDP's connected DRAM.
+		std::vector<uint8_t> ram_;
+
+		// Holds the state of the DRAM/CRAM-access mechanism.
 		uint16_t ram_pointer_ = 0;
 		uint8_t read_ahead_buffer_ = 0;
 		enum class MemoryAccess {
 			Read, Write, None
 		} queued_access_ = MemoryAccess::None;
+		int cycles_until_access_ = 0;
+		int minimum_access_column_ = 0;
+		int vram_access_delay() {
+			// This seems to be correct for all currently-modelled VDPs;
+			// it's the delay between an external device scheduling a
+			// read or write and the very first time that can occur
+			// (though, in practice, it won't happen until the next
+			// external slot after this number of cycles after the
+			// device has requested the read or write).
+			return 6;
+		}
 
+		// Holds the main status register.
 		uint8_t status_ = 0;
 
-		bool write_phase_ = false;
-		uint8_t low_write_ = 0;
+		// Current state of programmer input.
+		bool write_phase_ = false;	// Determines whether the VDP is expecting the low or high byte of a write.
+		uint8_t low_write_ = 0;		// Buffers the low byte of a write.
 
-		// The various register flags.
-		int next_screen_mode_ = 0, screen_mode_ = 0;
-		bool next_blank_screen_ = true, blank_screen_ = true;
+		// Various programmable flags.
+		bool mode1_enable_ = false;
+		bool mode2_enable_ = false;
+		bool mode3_enable_ = false;
+		bool blank_display_ = false;
 		bool sprites_16x16_ = false;
 		bool sprites_magnified_ = false;
 		bool generate_interrupts_ = false;
 		int sprite_height_ = 8;
-		uint16_t pattern_name_address_ = 0;
-		uint16_t colour_table_address_ = 0;
-		uint16_t pattern_generator_table_address_ = 0;
-		uint16_t sprite_attribute_table_address_ = 0;
-		uint16_t sprite_generator_table_address_ = 0;
+
+		size_t pattern_name_address_ = 0;				// i.e. address of the tile map.
+		size_t colour_table_address_ = 0;				// address of the colour map (if applicable).
+		size_t pattern_generator_table_address_ = 0;	// address of the tile contents.
+		size_t sprite_attribute_table_address_ = 0;		// address of the sprite list.
+		size_t sprite_generator_table_address_ = 0;		// address of the sprite contents.
 
 		uint8_t text_colour_ = 0;
 		uint8_t background_colour_ = 0;
 
-		HalfCycles half_cycles_into_frame_;
-		int column_ = 0, row_ = 0, output_column_ = 0;
+		// This implementation of this chip officially accepts a 3.58Mhz clock, but runs
+		// internally at 5.37Mhz. The following two help to maintain a lossless conversion
+		// from the one to the other.
 		int cycles_error_ = 0;
-		uint32_t *pixel_target_ = nullptr, *pixel_base_ = nullptr;
+		HalfCycles half_cycles_before_internal_cycles(int internal_cycles);
 
-		void output_border(int cycles);
+		// Internal mechanisms for position tracking.
+		int latched_column_ = 0;
 
-		// Vertical timing details.
-		int frame_lines_ = 262;
-		int first_vsync_line_ = 227;
+		// A helper function to output the current border colour for
+		// the number of cycles supplied.
+		void output_border(int cycles, uint32_t cram_dot);
+
+		// A struct to contain timing information for the current mode.
+		struct {
+			/*
+				Vertical layout:
+
+				Lines 0 to [pixel_lines]: standard data fetch and drawing will occur.
+				... to [first_vsync_line]: refresh fetches will occur and border will be output.
+				.. to [2.5 or 3 lines later]: vertical sync is output.
+				... to [total lines - 1]: refresh fetches will occur and border will be output.
+				... for one line: standard data fetch will occur, without drawing.
+			*/
+			int total_lines = 262;
+			int pixel_lines = 192;
+			int first_vsync_line = 227;
+
+			// Maximum number of sprite slots to populate;
+			// if sprites beyond this number should be visible
+			// then the appropriate status information will be set.
+			int maximum_visible_sprites = 4;
+
+			// Set the position, in cycles, of the two interrupts,
+			// within a line.
+			struct {
+				int column = 4;
+				int row = 193;
+			} end_of_frame_interrupt_position;
+			int line_interrupt_position = -1;
+
+			// Enables or disabled the recognition of the sprite
+			// list terminator, and sets the terminator value.
+			bool allow_sprite_terminator = true;
+			uint8_t sprite_terminator = 0xd0;
+		} mode_timing_;
+
+		uint8_t line_interrupt_target = 0xff;
+		uint8_t line_interrupt_counter = 0;
+		bool enable_line_interrupts_ = false;
+		bool line_interrupt_pending_ = false;
+
+		// The screen mode is a necessary predecessor to picking the line mode,
+		// which is the thing latched per line.
+		enum class ScreenMode {
+			Blank,
+			Text,
+			MultiColour,
+			ColouredText,
+			Graphics,
+			SMSMode4
+		} screen_mode_;
 
-		// Horizontal selections.
 		enum class LineMode {
-			Text = 0,
-			Character = 1,
-			Refresh = 2
-		} line_mode_ = LineMode::Text;
-		int first_pixel_column_, first_right_border_column_;
+			Text,
+			Character,
+			Refresh,
+			SMS
+		};
 
-		uint8_t pattern_names_[40];
-		uint8_t pattern_buffer_[40];
-		uint8_t colour_buffer_[40];
+		// Temporary buffers collect a representation of this line prior to pixel serialisation.
+		struct LineBuffer {
+			// The line mode describes the proper timing diagram for this line.
+			LineMode line_mode = LineMode::Text;
 
-		struct SpriteSet {
+			// Holds the horizontal scroll position to apply to this line;
+			// of those VDPs currently implemented, affects the Master System only.
+			uint8_t latched_horizontal_scroll = 0;
+
+			// The names array holds pattern names, as an offset into memory, and
+			// potentially flags also.
+			struct {
+				size_t offset = 0;
+				uint8_t flags = 0;
+			} names[40];
+
+			// The patterns array holds tile patterns, corresponding 1:1 with names.
+			// Four bytes per pattern is the maximum required by any
+			// currently-implemented VDP.
+			uint8_t patterns[40][4];
+
+			/*
+				Horizontal layout (on a 342-cycle clock):
+
+					15 cycles right border
+					58 cycles blanking & sync
+					13 cycles left border
+
+					... i.e. to cycle 86, then:
+
+					border up to first_pixel_output_column;
+					pixels up to next_border_column;
+					border up to the end.
+
+				e.g. standard 256-pixel modes will want to set
+				first_pixel_output_column = 86, next_border_column = 342.
+			*/
+			int first_pixel_output_column = 94;
+			int next_border_column = 334;
+
+			// An active sprite is one that has been selected for composition onto
+			// this line.
 			struct ActiveSprite {
-				int index = 0;
-				int row = 0;
+				int index = 0;		// The original in-table index of this sprite.
+				int row = 0;		// The row of the sprite that should be drawn.
+				int x = 0;			// The sprite's x position on screen.
 
-				uint8_t info[4];
-				uint8_t image[2];
+				uint8_t image[4];		// Up to four bytes of image information.
+				int shift_position = 0;	// An offset representing how much of the image information has already been drawn.
+			} active_sprites[8];
 
-				int shift_position = 0;
-			} active_sprites[4];
-			int active_sprite_slot = 0;
-		} sprite_sets_[2];
-		int active_sprite_set_ = 0;
-		bool sprites_stopped_ = false;
+			int active_sprite_slot = 0;		// A pointer to the slot into which a new active sprite will be deposited, if required.
+			bool sprites_stopped = false;	// A special TMS feature is that a sentinel value can be used to prevent any further sprites
+											// being evaluated for display. This flag determines whether the sentinel has yet been reached.
 
-		int access_pointer_ = 0;
+			void reset_sprite_collection();
+		} line_buffers_[313];
+		void posit_sprite(LineBuffer &buffer, int sprite_number, int sprite_y, int screen_row);
 
-		inline void test_sprite(int sprite_number, int screen_row);
-		inline void get_sprite_contents(int start, int cycles, int screen_row);
+		// There is a delay between reading into the line buffer and outputting from there to the screen. That delay
+		// is observeable because reading time affects availability of memory accesses and therefore time in which
+		// to update sprites and tiles, but writing time affects when the palette is used and when the collision flag
+		// may end up being set. So the two processes are slightly decoupled. The end of reading one line may overlap
+		// with the beginning of writing the next, hence the two separate line buffers.
+		struct LineBufferPointer {
+			int row, column;
+		} read_pointer_, write_pointer_;
+
+		// The SMS VDP has a programmer-set colour palette, with a dedicated patch of RAM. But the RAM is only exactly
+		// fast enough for the pixel clock. So when the programmer writes to it, that causes a one-pixel glitch; there
+		// isn't the bandwidth for the read both write to occur simultaneously. The following buffer therefore keeps
+		// track of pending collisions, for visual reproduction.
+		struct CRAMDot {
+			LineBufferPointer location;
+			uint32_t value;
+		};
+		std::vector<CRAMDot> upcoming_cram_dots_;
+
+		// Extra information that affects the Master System output mode.
+		struct {
+			// Programmer-set flags.
+			bool vertical_scroll_lock = false;
+			bool horizontal_scroll_lock = false;
+			bool hide_left_column = false;
+			bool shift_sprites_8px_left = false;
+			bool mode4_enable = false;
+			uint8_t horizontal_scroll = 0;
+			uint8_t vertical_scroll = 0;
+
+			// The Master System's additional colour RAM.
+			uint32_t colour_ram[32];
+			bool cram_is_selected = false;
+
+			// Holds the vertical scroll position for this frame; this is latched
+			// once and cannot dynamically be changed until the next frame.
+			uint8_t latched_vertical_scroll = 0;
+
+			size_t pattern_name_address;
+			size_t sprite_attribute_table_address;
+			size_t sprite_generator_table_address;
+		} master_system_;
+
+		void set_current_screen_mode() {
+			if(blank_display_) {
+				screen_mode_ = ScreenMode::Blank;
+				return;
+			}
+
+			if(is_sega_vdp(personality_) && master_system_.mode4_enable) {
+				screen_mode_ = ScreenMode::SMSMode4;
+				mode_timing_.maximum_visible_sprites = 8;
+				return;
+			}
+
+			mode_timing_.maximum_visible_sprites = 4;
+			if(!mode1_enable_ && !mode2_enable_ && !mode3_enable_) {
+				screen_mode_ = ScreenMode::ColouredText;
+				return;
+			}
+
+			if(mode1_enable_ && !mode2_enable_ && !mode3_enable_) {
+				screen_mode_ = ScreenMode::Text;
+				return;
+			}
+
+			if(!mode1_enable_ && mode2_enable_ && !mode3_enable_) {
+				screen_mode_ = ScreenMode::Graphics;
+				return;
+			}
+
+			if(!mode1_enable_ && !mode2_enable_ && mode3_enable_) {
+				screen_mode_ = ScreenMode::MultiColour;
+				return;
+			}
+
+			// TODO: undocumented TMS modes.
+			screen_mode_ = ScreenMode::Blank;
+		}
+
+		void do_external_slot(int access_column) {
+			// Don't do anything if the required time for the access to become executable
+			// has yet to pass.
+			if(access_column < minimum_access_column_) {
+				return;
+			}
+
+			switch(queued_access_) {
+				default: return;
+
+				case MemoryAccess::Write:
+					if(master_system_.cram_is_selected) {
+						// Adjust the palette.
+						master_system_.colour_ram[ram_pointer_ & 0x1f] = palette_pack(
+							static_cast<uint8_t>(((read_ahead_buffer_ >> 0) & 3) * 255 / 3),
+							static_cast<uint8_t>(((read_ahead_buffer_ >> 2) & 3) * 255 / 3),
+							static_cast<uint8_t>(((read_ahead_buffer_ >> 4) & 3) * 255 / 3)
+						);
+
+						// Schedule a CRAM dot; this is scheduled for wherever it should appear
+						// on screen. So it's wherever the output stream would be now. Which
+						// is output_lag cycles ago from the point of view of the input stream.
+						upcoming_cram_dots_.emplace_back();
+						CRAMDot &dot = upcoming_cram_dots_.back();
+
+						dot.location.column = write_pointer_.column - output_lag;
+						dot.location.row = write_pointer_.row;
+
+						// Handle before this row conditionally; then handle after (or, more realistically,
+						// exactly at the end of) naturally.
+						if(dot.location.column < 0) {
+							--dot.location.row;
+							dot.location.column += 342;
+						}
+						dot.location.row += dot.location.column / 342;
+						dot.location.column %= 342;
+
+						dot.value = master_system_.colour_ram[ram_pointer_ & 0x1f];
+					} else {
+						ram_[ram_pointer_ & 16383] = read_ahead_buffer_;
+					}
+				break;
+				case MemoryAccess::Read:
+					read_ahead_buffer_ = ram_[ram_pointer_ & 16383];
+				break;
+			}
+			++ram_pointer_;
+			queued_access_ = MemoryAccess::None;
+		}
+
+/*
+	Fetching routines follow below; they obey the following rules:
+
+		1)	input is a start position and an end position; they should perform the proper
+			operations for the period: start <= time < end.
+		2)	times are measured relative to a 172-cycles-per-line clock (so: they directly
+			count access windows on the TMS and Master System).
+		3)	time 0 is the beginning of the access window immediately after the last pattern/data
+			block fetch that would contribute to this line, in a normal 32-column mode. So:
+
+				* it's cycle 309 on Mattias' TMS diagram;
+				* it's cycle 1238 on his V9938 diagram;
+				* it's after the last background render block in Mask of Destiny's Master System timing diagram.
+
+			That division point was selected, albeit arbitrarily, because it puts all the tile
+			fetches for a single line into the same [0, 171] period.
+
+		4)	all of these functions are templated with a `use_end` parameter. That will be true if
+			end is < 172, false otherwise. So functions can use it to eliminate should-exit-not checks,
+			for the more usual path of execution.
+
+	Provided for the benefit of the methods below:
+
+		*	the function external_slot(), which will perform any pending VRAM read/write.
+		*	the macros slot(n) and external_slot(n) which can be used to schedule those things inside a
+			switch(start)-based implementation.
+
+	All functions should just spool data to intermediary storage. This is because for most VDPs there is
+	a decoupling between fetch pattern and output pattern, and it's neater to keep the same division
+	for the exceptions.
+*/
+
+#define slot(n)	\
+		if(use_end && end == n) return;\
+		case n
+
+#define external_slot(n)	\
+	slot(n): do_external_slot((n)*2);
+
+#define external_slots_2(n)	\
+	external_slot(n);		\
+	external_slot(n+1);
+
+#define external_slots_4(n)	\
+	external_slots_2(n);	\
+	external_slots_2(n+2);
+
+#define external_slots_8(n)	\
+	external_slots_4(n);	\
+	external_slots_4(n+4);
+
+#define external_slots_16(n)	\
+	external_slots_8(n);		\
+	external_slots_8(n+8);
+
+#define external_slots_32(n)	\
+	external_slots_16(n);		\
+	external_slots_16(n+16);
+
+
+/***********************************************
+             TMS9918 Fetching Code
+************************************************/
+
+		template<bool use_end> void fetch_tms_refresh(int start, int end) {
+#define refresh(location)		\
+	slot(location):				\
+	external_slot(location+1);
+
+#define refreshes_2(location)	\
+	refresh(location);			\
+	refresh(location+2);
+
+#define refreshes_4(location)	\
+	refreshes_2(location);		\
+	refreshes_2(location+4);
+
+#define refreshes_8(location)	\
+	refreshes_4(location);		\
+	refreshes_4(location+8);
+
+			switch(start) {
+				default: assert(false);
+
+				/* 44 external slots */
+				external_slots_32(0)
+				external_slots_8(32)
+				external_slots_4(40)
+
+				/* 64 refresh/external slot pairs (= 128 windows) */
+				refreshes_8(44);
+				refreshes_8(60);
+				refreshes_8(76);
+				refreshes_8(92);
+				refreshes_8(108);
+				refreshes_8(124);
+				refreshes_8(140);
+				refreshes_8(156);
+
+				return;
+			}
+
+#undef refreshes_8
+#undef refreshes_4
+#undef refreshes_2
+#undef refresh
+		}
+
+		template<bool use_end> void fetch_tms_text(int start, int end) {
+#define fetch_tile_name(location, column)		slot(location): line_buffer.names[column].offset = ram_[row_base + column];
+#define fetch_tile_pattern(location, column)	slot(location): line_buffer.patterns[column][0] = ram_[row_offset + size_t(line_buffer.names[column].offset << 3)];
+
+#define fetch_column(location, column)	\
+	fetch_tile_name(location, column);	\
+	external_slot(location+1);	\
+	fetch_tile_pattern(location+2, column);
+
+#define fetch_columns_2(location, column)	\
+	fetch_column(location, column);	\
+	fetch_column(location+3, column+1);
+
+#define fetch_columns_4(location, column)	\
+	fetch_columns_2(location, column);	\
+	fetch_columns_2(location+6, column+2);
+
+#define fetch_columns_8(location, column)	\
+	fetch_columns_4(location, column);	\
+	fetch_columns_4(location+12, column+4);
+
+			LineBuffer &line_buffer = line_buffers_[write_pointer_.row];
+			const size_t row_base = pattern_name_address_ & (0x3c00 | static_cast<size_t>(write_pointer_.row >> 3) * 40);
+			const size_t row_offset = pattern_generator_table_address_ & (0x3800 | (write_pointer_.row & 7));
+
+			switch(start) {
+				default: assert(false);
+
+					/* 47 external slots (= 47 windows) */
+					external_slots_32(0)
+					external_slots_8(32)
+					external_slots_4(40)
+					external_slots_2(44)
+					external_slot(46)
+
+					/* 40 column fetches (= 120 windows) */
+					fetch_columns_8(47, 0);
+					fetch_columns_8(71, 8);
+					fetch_columns_8(95, 16);
+					fetch_columns_8(119, 24);
+					fetch_columns_8(143, 32);
+
+					/* 5 more external slots */
+					external_slots_4(167);
+					external_slot(171);
+
+				return;
+			}
+
+#undef fetch_columns_8
+#undef fetch_columns_4
+#undef fetch_columns_2
+#undef fetch_column
+#undef fetch_tile_pattern
+#undef fetch_tile_name
+		}
+
+		template<bool use_end> void fetch_tms_character(int start, int end) {
+#define sprite_fetch_coordinates(location, sprite)	\
+	slot(location):		\
+	slot(location+1):	\
+		line_buffer.active_sprites[sprite].x = \
+			ram_[\
+				sprite_attribute_table_address_ & size_t(0x3f81 | (line_buffer.active_sprites[sprite].index << 2))\
+			];
+
+		// This implementation doesn't refetch Y; it's unclear to me
+		// whether it's refetched.
+
+#define sprite_fetch_graphics(location, sprite)	\
+	slot(location):		\
+	slot(location+1):	\
+	slot(location+2):	\
+	slot(location+3):	{\
+		const uint8_t name = ram_[\
+				sprite_attribute_table_address_ & size_t(0x3f82 | (line_buffer.active_sprites[sprite].index << 2))\
+			] & (sprites_16x16_ ? ~3 : ~0);\
+		line_buffer.active_sprites[sprite].image[2] = ram_[\
+				sprite_attribute_table_address_ & size_t(0x3f83 | (line_buffer.active_sprites[sprite].index << 2))\
+			];\
+		line_buffer.active_sprites[sprite].x -= (line_buffer.active_sprites[sprite].image[2] & 0x80) >> 2;\
+		const size_t graphic_location = sprite_generator_table_address_ & size_t(0x3800 | (name << 3) | line_buffer.active_sprites[sprite].row);	\
+		line_buffer.active_sprites[sprite].image[0] = ram_[graphic_location];\
+		line_buffer.active_sprites[sprite].image[1] = ram_[graphic_location+16];\
+	}
+
+#define sprite_fetch_block(location, sprite)	\
+	sprite_fetch_coordinates(location, sprite)	\
+	sprite_fetch_graphics(location+2, sprite)
+
+#define sprite_y_read(location, sprite)	\
+	slot(location): posit_sprite(sprite_selection_buffer, sprite, ram_[sprite_attribute_table_address_ & (((sprite) << 2) | 0x3f80)], write_pointer_.row);
+
+#define fetch_tile_name(column) line_buffer.names[column].offset = ram_[(row_base + column) & 0x3fff];
+
+#define fetch_tile(column)	{\
+		line_buffer.patterns[column][1] = ram_[(colour_base + size_t((line_buffer.names[column].offset << 3) >> colour_name_shift)) & 0x3fff];		\
+		line_buffer.patterns[column][0] = ram_[(pattern_base + size_t(line_buffer.names[column].offset << 3)) & 0x3fff];	\
+	}
+
+#define background_fetch_block(location, column, sprite)	\
+	slot(location):	fetch_tile_name(column)		\
+	external_slot(location+1);	\
+	slot(location+2):	\
+	slot(location+3): fetch_tile(column)	\
+	slot(location+4): fetch_tile_name(column+1)	\
+	sprite_y_read(location+5, sprite);	\
+	slot(location+6):	\
+	slot(location+7): fetch_tile(column+1)	\
+	slot(location+8): fetch_tile_name(column+2)	\
+	sprite_y_read(location+9, sprite+1);	\
+	slot(location+10):	\
+	slot(location+11): fetch_tile(column+2)	\
+	slot(location+12): fetch_tile_name(column+3)	\
+	sprite_y_read(location+13, sprite+2);	\
+	slot(location+14):	\
+	slot(location+15): fetch_tile(column+3)
+
+			LineBuffer &line_buffer = line_buffers_[write_pointer_.row];
+			LineBuffer &sprite_selection_buffer = line_buffers_[(write_pointer_.row + 1) % mode_timing_.total_lines];
+			const size_t row_base = pattern_name_address_ & (size_t((write_pointer_.row << 2)&~31) | 0x3c00);
+
+			size_t pattern_base = pattern_generator_table_address_;
+			size_t colour_base = colour_table_address_;
+			int colour_name_shift = 6;
+
+			if(screen_mode_ == ScreenMode::Graphics) {
+				// If this is high resolution mode, allow the row number to affect the pattern and colour addresses.
+				pattern_base &= size_t(0x2000 | ((write_pointer_.row & 0xc0) << 5));
+				colour_base &= size_t(0x2000 | ((write_pointer_.row & 0xc0) << 5));
+
+				colour_base += size_t(write_pointer_.row & 7);
+				colour_name_shift = 0;
+			} else {
+				colour_base &= size_t(0xffc0);
+				pattern_base &= size_t(0x3800);
+			}
+
+			if(screen_mode_ == ScreenMode::MultiColour) {
+				pattern_base += size_t((write_pointer_.row >> 2) & 7);
+			} else {
+				pattern_base += size_t(write_pointer_.row & 7);
+			}
+
+			switch(start) {
+				default: assert(false);
+
+				external_slots_2(0);
+
+				sprite_fetch_block(2, 0);
+				sprite_fetch_block(8, 1);
+				sprite_fetch_coordinates(14, 2);
+
+				external_slots_4(16);
+				external_slot(20);
+
+				sprite_fetch_graphics(21, 2);
+				sprite_fetch_block(25, 3);
+
+				slot(31):
+					sprite_selection_buffer.reset_sprite_collection();
+					do_external_slot(31*2);
+				external_slots_2(32);
+				external_slot(34);
+
+				sprite_y_read(35, 0);
+				sprite_y_read(36, 1);
+				sprite_y_read(37, 2);
+				sprite_y_read(38, 3);
+				sprite_y_read(39, 4);
+				sprite_y_read(40, 5);
+				sprite_y_read(41, 6);
+				sprite_y_read(42, 7);
+
+				background_fetch_block(43, 0, 8);
+				background_fetch_block(59, 4, 11);
+				background_fetch_block(75, 8, 14);
+				background_fetch_block(91, 12, 17);
+				background_fetch_block(107, 16, 20);
+				background_fetch_block(123, 20, 23);
+				background_fetch_block(139, 24, 26);
+				background_fetch_block(155, 28, 29);
+
+				return;
+			}
+
+#undef background_fetch_block
+#undef fetch_tile
+#undef fetch_tile_name
+#undef sprite_y_read
+#undef sprite_fetch_block
+#undef sprite_fetch_graphics
+#undef sprite_fetch_coordinates
+		}
+
+
+/***********************************************
+          Master System Fetching Code
+************************************************/
+
+		template<bool use_end> void fetch_sms(int start, int end) {
+#define sprite_fetch(sprite)	{\
+		line_buffer.active_sprites[sprite].x = \
+			ram_[\
+				master_system_.sprite_attribute_table_address & size_t(0x3f80 | (line_buffer.active_sprites[sprite].index << 1))\
+			] - (master_system_.shift_sprites_8px_left ? 8 : 0);	\
+		const uint8_t name = ram_[\
+				master_system_.sprite_attribute_table_address & size_t(0x3f81 | (line_buffer.active_sprites[sprite].index << 1))\
+			] & (sprites_16x16_ ? ~1 : ~0);\
+		const size_t graphic_location = master_system_.sprite_generator_table_address & size_t(0x2000 | (name << 5) | (line_buffer.active_sprites[sprite].row << 2));	\
+		line_buffer.active_sprites[sprite].image[0] = ram_[graphic_location];	\
+		line_buffer.active_sprites[sprite].image[1] = ram_[graphic_location+1];	\
+		line_buffer.active_sprites[sprite].image[2] = ram_[graphic_location+2];	\
+		line_buffer.active_sprites[sprite].image[3] = ram_[graphic_location+3];	\
+	}
+
+#define sprite_fetch_block(location, sprite)	\
+	slot(location):		\
+	slot(location+1):	\
+	slot(location+2):	\
+	slot(location+3):	\
+	slot(location+4):	\
+	slot(location+5):	\
+		sprite_fetch(sprite);\
+		sprite_fetch(sprite+1);
+
+#define sprite_y_read(location, sprite)	\
+	slot(location):	\
+		posit_sprite(sprite_selection_buffer, sprite, ram_[master_system_.sprite_attribute_table_address & ((sprite) | 0x3f00)], write_pointer_.row);	\
+		posit_sprite(sprite_selection_buffer, sprite+1, ram_[master_system_.sprite_attribute_table_address & ((sprite + 1) | 0x3f00)], write_pointer_.row);	\
+
+#define fetch_tile_name(column, row_info)	{\
+		const size_t scrolled_column = (column - horizontal_offset) & 0x1f;\
+		const size_t address = row_info.pattern_address_base + (scrolled_column << 1);	\
+		line_buffer.names[column].flags = ram_[address+1];	\
+		line_buffer.names[column].offset = static_cast<size_t>(	\
+			(((line_buffer.names[column].flags&1) << 8) | ram_[address]) << 5	\
+		) + row_info.sub_row[(line_buffer.names[column].flags&4) >> 2];	\
+	}
+
+#define fetch_tile(column)	\
+	line_buffer.patterns[column][0] = ram_[line_buffer.names[column].offset];	\
+	line_buffer.patterns[column][1] = ram_[line_buffer.names[column].offset+1];	\
+	line_buffer.patterns[column][2] = ram_[line_buffer.names[column].offset+2];	\
+	line_buffer.patterns[column][3] = ram_[line_buffer.names[column].offset+3];
+
+#define background_fetch_block(location, column, sprite, row_info)	\
+	slot(location):	fetch_tile_name(column, row_info)		\
+	external_slot(location+1);					\
+	slot(location+2):	\
+	slot(location+3):	\
+	slot(location+4):	\
+		fetch_tile(column)					\
+		fetch_tile_name(column+1, row_info)			\
+		sprite_y_read(location+5, sprite);	\
+	slot(location+6):	\
+	slot(location+7):	\
+	slot(location+8):	\
+		fetch_tile(column+1)					\
+		fetch_tile_name(column+2, row_info)				\
+		sprite_y_read(location+9, sprite+2);	\
+	slot(location+10):	\
+	slot(location+11):	\
+	slot(location+12):	\
+		fetch_tile(column+2)					\
+		fetch_tile_name(column+3, row_info)				\
+		sprite_y_read(location+13, sprite+4);	\
+	slot(location+14):	\
+	slot(location+15): fetch_tile(column+3)
+
+			// Determine the coarse horizontal scrolling offset; this isn't applied on the first two lines if the programmer has requested it.
+			LineBuffer &line_buffer = line_buffers_[write_pointer_.row];
+			LineBuffer &sprite_selection_buffer = line_buffers_[(write_pointer_.row + 1) % mode_timing_.total_lines];
+			const int horizontal_offset = (write_pointer_.row >= 16 || !master_system_.horizontal_scroll_lock) ? (line_buffer.latched_horizontal_scroll >> 3) : 0;
+
+			// Limit address bits in use if this is a SMS2 mode.
+			const bool is_tall_mode = mode_timing_.pixel_lines != 192;
+			const size_t pattern_name_address = master_system_.pattern_name_address | (is_tall_mode ? 0x800 : 0);
+			const size_t pattern_name_offset = is_tall_mode ? 0x100 : 0;
+
+			// Determine row info for the screen both (i) if vertical scrolling is applied; and (ii) if it isn't.
+			// The programmer can opt out of applying vertical scrolling to the right-hand portion of the display.
+			const int scrolled_row = (write_pointer_.row + master_system_.latched_vertical_scroll) % (is_tall_mode ? 256 : 224);
+			struct RowInfo {
+				size_t pattern_address_base;
+				size_t sub_row[2];
+			};
+			const RowInfo scrolled_row_info = {
+				(pattern_name_address & size_t(((scrolled_row & ~7) << 3) | 0x3800)) - pattern_name_offset,
+				{static_cast<size_t>((scrolled_row & 7) << 2), 28 ^ static_cast<size_t>((scrolled_row & 7) << 2)}
+			};
+			RowInfo row_info;
+			if(master_system_.vertical_scroll_lock) {
+				row_info.pattern_address_base = (pattern_name_address & size_t(((write_pointer_.row & ~7) << 3) | 0x3800)) - pattern_name_offset;
+				row_info.sub_row[0] = size_t((write_pointer_.row & 7) << 2);
+				row_info.sub_row[1] = 28 ^ size_t((write_pointer_.row & 7) << 2);
+			} else row_info = scrolled_row_info;
+
+			// ... and do the actual fetching, which follows this routine:
+			switch(start) {
+				default: assert(false);
+
+				sprite_fetch_block(0, 0);
+				sprite_fetch_block(6, 2);
+
+				external_slots_4(12);
+				external_slot(16);
+
+				sprite_fetch_block(17, 4);
+				sprite_fetch_block(23, 6);
+
+				slot(29):
+					sprite_selection_buffer.reset_sprite_collection();
+					do_external_slot(29*2);
+				external_slot(30);
+
+				sprite_y_read(31, 0);
+				sprite_y_read(32, 2);
+				sprite_y_read(33, 4);
+				sprite_y_read(34, 6);
+				sprite_y_read(35, 8);
+				sprite_y_read(36, 10);
+				sprite_y_read(37, 12);
+				sprite_y_read(38, 14);
+
+				background_fetch_block(39, 0, 16, scrolled_row_info);
+				background_fetch_block(55, 4, 22, scrolled_row_info);
+				background_fetch_block(71, 8, 28, scrolled_row_info);
+				background_fetch_block(87, 12, 34, scrolled_row_info);
+				background_fetch_block(103, 16, 40, scrolled_row_info);
+				background_fetch_block(119, 20, 46, scrolled_row_info);
+				background_fetch_block(135, 24, 52, row_info);
+				background_fetch_block(151, 28, 58, row_info);
+
+				external_slots_4(167);
+
+				return;
+			}
+
+#undef background_fetch_block
+#undef fetch_tile
+#undef fetch_tile_name
+#undef sprite_y_read
+#undef sprite_fetch_block
+#undef sprite_fetch
+		}
+
+#undef external_slot
+#undef slot
+
+		uint32_t *pixel_target_ = nullptr, *pixel_origin_ = nullptr;
+		bool asked_for_write_area_ = false;
+		void draw_tms_character(int start, int end);
+		void draw_tms_text(int start, int end);
+		void draw_sms(int start, int end, uint32_t cram_dot);
 };
 
+}
 }
 
 #endif /* TMS9918Base_hpp */

Components/AY38910/AY38910.cpp

@@ -12,45 +12,56 @@
 
 using namespace GI::AY38910;
 
-AY38910::AY38910(Concurrency::DeferringAsyncTaskQueue &task_queue) : task_queue_(task_queue) {
-	// set up envelope lookup tables
+AY38910::AY38910(Personality personality, Concurrency::DeferringAsyncTaskQueue &task_queue) : task_queue_(task_queue) {
+	// Don't use the low bit of the envelope position if this is an AY.
+	envelope_position_mask_ |= personality == Personality::AY38910;
+
+	// Set up envelope lookup tables.
 	for(int c = 0; c < 16; c++) {
-		for(int p = 0; p < 32; p++) {
+		for(int p = 0; p < 64; p++) {
 			switch(c) {
 				case 0: case 1: case 2: case 3: case 9:
-					envelope_shapes_[c][p] = (p < 16) ? (p^0xf) : 0;
-					envelope_overflow_masks_[c] = 0x1f;
+					/* Envelope: \____ */
+					envelope_shapes_[c][p] = (p < 32) ? (p^0x1f) : 0;
+					envelope_overflow_masks_[c] = 0x3f;
 				break;
 				case 4: case 5: case 6: case 7: case 15:
-					envelope_shapes_[c][p] = (p < 16) ? p : 0;
-					envelope_overflow_masks_[c] = 0x1f;
+					/* Envelope: /____ */
+					envelope_shapes_[c][p] = (p < 32) ? p : 0;
+					envelope_overflow_masks_[c] = 0x3f;
 				break;
 
 				case 8:
-					envelope_shapes_[c][p] = (p & 0xf) ^ 0xf;
+					/* Envelope: \\\\\\\\ */
+					envelope_shapes_[c][p] = (p & 0x1f) ^ 0x1f;
 					envelope_overflow_masks_[c] = 0x00;
 				break;
 				case 12:
-					envelope_shapes_[c][p] = (p & 0xf);
+					/* Envelope: //////// */
+					envelope_shapes_[c][p] = (p & 0x1f);
 					envelope_overflow_masks_[c] = 0x00;
 				break;
 
 				case 10:
-					envelope_shapes_[c][p] = (p & 0xf) ^ ((p < 16) ? 0xf : 0x0);
+					/* Envelope: \/\/\/\/ */
+					envelope_shapes_[c][p] = (p & 0x1f) ^ ((p < 32) ? 0x1f : 0x0);
 					envelope_overflow_masks_[c] = 0x00;
 				break;
 				case 14:
-					envelope_shapes_[c][p] = (p & 0xf) ^ ((p < 16) ? 0x0 : 0xf);
+					/* Envelope: /\/\/\/\ */
+					envelope_shapes_[c][p] = (p & 0x1f) ^ ((p < 32) ? 0x0 : 0x1f);
 					envelope_overflow_masks_[c] = 0x00;
 				break;
 
 				case 11:
-					envelope_shapes_[c][p] = (p < 16) ? (p^0xf) : 0xf;
-					envelope_overflow_masks_[c] = 0x1f;
+					/* Envelope: \------	(if - is high) */
+					envelope_shapes_[c][p] = (p < 32) ? (p^0x1f) : 0x1f;
+					envelope_overflow_masks_[c] = 0x3f;
 				break;
 				case 13:
-					envelope_shapes_[c][p] = (p < 16) ? p : 0xf;
-					envelope_overflow_masks_[c] = 0x1f;
+					/* Envelope: /------- */
+					envelope_shapes_[c][p] = (p < 32) ? p : 0x1f;
+					envelope_overflow_masks_[c] = 0x3f;
 				break;
 			}
 		}
@@ -61,18 +72,27 @@ AY38910::AY38910(Concurrency::DeferringAsyncTaskQueue &task_queue) : task_queue_
 
 void AY38910::set_sample_volume_range(std::int16_t range) {
 	// set up volume lookup table
-	const float max_volume = static_cast<float>(range) / 3.0f;	// As there are three channels.
-	const float root_two = sqrtf(2.0f);
-	for(int v = 0; v < 16; v++) {
-		volumes_[v] = static_cast<int>(max_volume / powf(root_two, static_cast<float>(v ^ 0xf)));
+	const float max_volume = float(range) / 3.0f;	// As there are three channels.
+	constexpr float root_two = 1.414213562373095f;
+	for(int v = 0; v < 32; v++) {
+		volumes_[v] = int(max_volume / powf(root_two, float(v ^ 0x1f) / 2.0f));
 	}
-	volumes_[0] = 0;
+	volumes_[0] = 0;	// Tie level 0 to silence.
 	evaluate_output_volume();
 }
 
 void AY38910::get_samples(std::size_t number_of_samples, int16_t *target) {
+	// Note on structure below: the real AY has a built-in divider of 8
+	// prior to applying its tone and noise dividers. But the YM fills the
+	// same total periods for noise and tone with double-precision envelopes.
+	// Therefore this class implements a divider of 4 and doubles the tone
+	// and noise periods. The envelope ticks along at the divide-by-four rate,
+	// but if this is an AY rather than a YM then its lowest bit is forced to 1,
+	// matching the YM datasheet's depiction of envelope level 31 as equal to
+	// programmatic volume 15, envelope level 29 as equal to programmatic 14, etc.
+
 	std::size_t c = 0;
-	while((master_divider_&7) && c < number_of_samples) {
+	while((master_divider_&3) && c < number_of_samples) {
 		target[c] = output_volume_;
 		master_divider_++;
 		c++;
@@ -83,49 +103,49 @@ void AY38910::get_samples(std::size_t number_of_samples, int16_t *target) {
 	if(tone_counters_[c]) tone_counters_[c]--;\
 	else {\
 		tone_outputs_[c] ^= 1;\
-		tone_counters_[c] = tone_periods_[c];\
+		tone_counters_[c] = tone_periods_[c] << 1;\
 	}
 
-		// update the tone channels
+		// Update the tone channels.
 		step_channel(0);
 		step_channel(1);
 		step_channel(2);
 
 #undef step_channel
 
-		// ... the noise generator. This recomputes the new bit repeatedly but harmlessly, only shifting
+		// Update the noise generator. This recomputes the new bit repeatedly but harmlessly, only shifting
 		// it into the official 17 upon divider underflow.
 		if(noise_counter_) noise_counter_--;
 		else {
-			noise_counter_ = noise_period_;
+			noise_counter_ = noise_period_ << 1;	// To cover the double resolution of envelopes.
 			noise_output_ ^= noise_shift_register_&1;
 			noise_shift_register_ |= ((noise_shift_register_ ^ (noise_shift_register_ >> 3))&1) << 17;
 			noise_shift_register_ >>= 1;
 		}
 
-		// ... and the envelope generator. Table based for pattern lookup, with a 'refill' step: a way of
-		// implementing non-repeating patterns by locking them to table position 0x1f.
+		// Update the envelope generator. Table based for pattern lookup, with a 'refill' step: a way of
+		// implementing non-repeating patterns by locking them to the final table position.
 		if(envelope_divider_) envelope_divider_--;
 		else {
 			envelope_divider_ = envelope_period_;
 			envelope_position_ ++;
-			if(envelope_position_ == 32) envelope_position_ = envelope_overflow_masks_[output_registers_[13]];
+			if(envelope_position_ == 64) envelope_position_ = envelope_overflow_masks_[output_registers_[13]];
 		}
 
 		evaluate_output_volume();
 
-		for(int ic = 0; ic < 8 && c < number_of_samples; ic++) {
+		for(int ic = 0; ic < 4 && c < number_of_samples; ic++) {
 			target[c] = output_volume_;
 			c++;
 			master_divider_++;
 		}
 	}
 
-	master_divider_ &= 7;
+	master_divider_ &= 3;
 }
 
 void AY38910::evaluate_output_volume() {
-	int envelope_volume = envelope_shapes_[output_registers_[13]][envelope_position_];
+	int envelope_volume = envelope_shapes_[output_registers_[13]][envelope_position_ | envelope_position_mask_];
 
 	// The output level for a channel is:
 	//	1 if neither tone nor noise is enabled;
@@ -142,9 +162,20 @@ void AY38910::evaluate_output_volume() {
 	};
 #undef level
 
-		// Channel volume is a simple selection: if the bit at 0x10 is set, use the envelope volume; otherwise use the lower four bits
+	// This remapping table seeks to map 'channel volumes', i.e. the levels produced from the
+	// 16-step progammatic volumes set per channel to 'envelope volumes', i.e. the 32-step
+	// volumes that are produced by the envelope generators (on a YM at least). My reading of
+	// the data sheet is that '0' is still off, but 15 should be as loud as peak envelope. So
+	// I've thrown in the discontinuity at the low end, where it'll be very quiet.
+	const int channel_volumes[] = {
+		0, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31
+	};
+	static_assert(sizeof(channel_volumes) == 16*sizeof(int));
+
+		// Channel volume is a simple selection: if the bit at 0x10 is set, use the envelope volume; otherwise use the lower four bits,
+		// mapped to the range 1–31 in case this is a YM.
 #define channel_volume(c)	\
-	((output_registers_[c] >> 4)&1) * envelope_volume + (((output_registers_[c] >> 4)&1)^1) * (output_registers_[c]&0xf)
+	((output_registers_[c] >> 4)&1) * envelope_volume + (((output_registers_[c] >> 4)&1)^1) * channel_volumes[output_registers_[c]&0xf]
 
 	const int volumes[3] = {
 		channel_volume(8),
@@ -173,11 +204,15 @@ void AY38910::select_register(uint8_t r) {
 }
 
 void AY38910::set_register_value(uint8_t value) {
+	// There are only 16 registers.
 	if(selected_register_ > 15) return;
-	registers_[selected_register_] = value;
+
+	// If this is a register that affects audio output, enqueue a mutation onto the
+	// audio generation thread.
 	if(selected_register_ < 14) {
-		int selected_register = selected_register_;
+		const int selected_register = selected_register_;
 		task_queue_.defer([=] () {
+			// Perform any register-specific mutation to output generation.
 			uint8_t masked_value = value;
 			switch(selected_register) {
 				case 0: case 2: case 4:
@@ -208,12 +243,34 @@ void AY38910::set_register_value(uint8_t value) {
 					envelope_position_ = 0;
 				break;
 			}
+
+			// Store a copy of the current register within the storage used by the audio generation
+			// thread, and apply any changes to output volume.
 			output_registers_[selected_register] = masked_value;
 			evaluate_output_volume();
 		});
-	} else {
-		if(port_handler_) port_handler_->set_port_output(selected_register_ == 15, value);
 	}
+
+	// Decide which outputs are going to need updating (if any).
+	bool update_port_a = false;
+	bool update_port_b = true;
+	if(port_handler_) {
+		if(selected_register_ == 7) {
+			const uint8_t io_change = registers_[7] ^ value;
+			update_port_b = !!(io_change&0x80);
+			update_port_a = !!(io_change&0x40);
+		} else {
+			update_port_b = selected_register_ == 15;
+			update_port_a = selected_register_ != 15;
+		}
+	}
+
+	// Keep a copy of the new value that is usable from the emulation thread.
+	registers_[selected_register_] = value;
+
+	// Update ports as required.
+	if(update_port_b) set_port_output(true);
+	if(update_port_a) set_port_output(false);
 }
 
 uint8_t AY38910::get_register_value() {
@@ -225,14 +282,10 @@ uint8_t AY38910::get_register_value() {
 	};
 
 	if(selected_register_ > 15) return 0xff;
-	switch(selected_register_) {
-		default:	return registers_[selected_register_] & register_masks[selected_register_];
-		case 14:	return (registers_[0x7] & 0x40) ? registers_[14] : port_inputs_[0];
-		case 15:	return (registers_[0x7] & 0x80) ? registers_[15] : port_inputs_[1];
-	}
+	return registers_[selected_register_] & register_masks[selected_register_];
 }
 
-// MARK: - Port handling
+// MARK: - Port querying
 
 uint8_t AY38910::get_port_output(bool port_b) {
 	return registers_[port_b ? 15 : 14];
@@ -242,6 +295,8 @@ uint8_t AY38910::get_port_output(bool port_b) {
 
 void AY38910::set_port_handler(PortHandler *handler) {
 	port_handler_ = handler;
+	set_port_output(true);
+	set_port_output(false);
 }
 
 void AY38910::set_data_input(uint8_t r) {
@@ -249,12 +304,27 @@ void AY38910::set_data_input(uint8_t r) {
 	update_bus();
 }
 
+void AY38910::set_port_output(bool port_b) {
+	// Per the data sheet: "each [IO] pin is provided with an on-chip pull-up resistor,
+	// so that when in the "input" mode, all pins will read normally high". Therefore,
+	// report programmer selection of input mode as creating an output of 0xff.
+	if(port_handler_) {
+		const bool is_output = !!(registers_[7] & (port_b ? 0x80 : 0x40));
+		port_handler_->set_port_output(port_b, is_output ? registers_[port_b ? 15 : 14] : 0xff);
+	}
+}
+
 uint8_t AY38910::get_data_output() {
-	if(control_state_ == Read && selected_register_ >= 14) {
-		if(port_handler_) {
-			return port_handler_->get_port_input(selected_register_ == 15);
-		} else {
-			return 0xff;
+	if(control_state_ == Read && selected_register_ >= 14 && selected_register_ < 16) {
+		// Per http://cpctech.cpc-live.com/docs/psgnotes.htm if a port is defined as output then the
+		// value returned to the CPU when reading it is the and of the output value and any input.
+		// If it's defined as input then you just get the input.
+		const uint8_t mask = port_handler_ ? port_handler_->get_port_input(selected_register_ == 15) : 0xff;
+
+		switch(selected_register_) {
+			default:	break;
+			case 14:	return mask & ((registers_[0x7] & 0x40) ? registers_[14] : 0xff);
+			case 15:	return mask & ((registers_[0x7] & 0x80) ? registers_[15] : 0xff);
 		}
 	}
 	return data_output_;
@@ -276,8 +346,10 @@ void AY38910::set_control_lines(ControlLines control_lines) {
 }
 
 void AY38910::update_bus() {
+	// Assume no output, unless this turns out to be a read.
+	data_output_ = 0xff;
 	switch(control_state_) {
-		default: break;
+		default:			break;
 		case LatchAddress:	select_register(data_input_);			break;
 		case Write:			set_register_value(data_input_);		break;
 		case Read:			data_output_ = get_register_value();	break;

Components/AY38910/AY38910.hpp

@@ -35,9 +35,10 @@ class PortHandler {
 		}
 
 		/*!
-			Requests the current input on an AY port.
+			Sets the current output on an AY port.
 
-			@param port_b @c true if the input being queried is Port B. @c false if it is Port A.
+			@param port_b @c true if the output being posted is Port B. @c false if it is Port A.
+			@param value the value now being output.
 		*/
 		virtual void set_port_output(bool port_b, uint8_t value) {}
 };
@@ -51,6 +52,13 @@ enum ControlLines {
 	BDIR	= (1 << 2)
 };
 
+enum class Personality {
+	/// Provides 16 volume levels to envelopes.
+	AY38910,
+	/// Provides 32 volume levels to envelopes.
+	YM2149F
+};
+
 /*!
 	Provides emulation of an AY-3-8910 / YM2149, which is a three-channel sound chip with a
 	noise generator and a volume envelope generator, which also provides two bidirectional
@@ -59,7 +67,7 @@ enum ControlLines {
 class AY38910: public ::Outputs::Speaker::SampleSource {
 	public:
 		/// Creates a new AY38910.
-		AY38910(Concurrency::DeferringAsyncTaskQueue &task_queue);
+		AY38910(Personality, Concurrency::DeferringAsyncTaskQueue &);
 
 		/// Sets the value the AY would read from its data lines if it were not outputting.
 		void set_data_input(uint8_t r);
@@ -83,7 +91,7 @@ class AY38910: public ::Outputs::Speaker::SampleSource {
 		*/
 		void set_port_handler(PortHandler *);
 
-		// to satisfy ::Outputs::Speaker (included via ::Outputs::Filter; not for public consumption
+		// to satisfy ::Outputs::Speaker (included via ::Outputs::Filter.
 		void get_samples(std::size_t number_of_samples, int16_t *target);
 		bool is_zero_level();
 		void set_sample_volume_range(std::int16_t range);
@@ -92,9 +100,8 @@ class AY38910: public ::Outputs::Speaker::SampleSource {
 		Concurrency::DeferringAsyncTaskQueue &task_queue_;
 
 		int selected_register_ = 0;
-		uint8_t registers_[16];
+		uint8_t registers_[16] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 		uint8_t output_registers_[16] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-		uint8_t port_inputs_[2];
 
 		int master_divider_ = 0;
 
@@ -109,11 +116,11 @@ class AY38910: public ::Outputs::Speaker::SampleSource {
 
 		int envelope_period_ = 0;
 		int envelope_divider_ = 0;
-		int envelope_position_ = 0;
-		int envelope_shapes_[16][32];
+		int envelope_position_ = 0, envelope_position_mask_ = 0;
+		int envelope_shapes_[16][64];
 		int envelope_overflow_masks_[16];
 
-		int volumes_[16];
+		int volumes_[32];
 
 		enum ControlState {
 			Inactive,
@@ -129,10 +136,11 @@ class AY38910: public ::Outputs::Speaker::SampleSource {
 		uint8_t data_input_, data_output_;
 
 		int16_t output_volume_;
-		inline void evaluate_output_volume();
+		void evaluate_output_volume();
 
-		inline void update_bus();
+		void update_bus();
 		PortHandler *port_handler_ = nullptr;
+		void set_port_output(bool port_b);
 };
 
 }

Components/DiskII/DiskII.cpp

@@ -19,12 +19,14 @@ namespace  {
 	const uint8_t input_flux = 0x1;
 }
 
-DiskII::DiskII() :
+DiskII::DiskII(int clock_rate) :
+	clock_rate_(clock_rate),
 	inputs_(input_command),
-	drives_{{2045454, 300, 1}, {2045454, 300, 1}}
+	drives_{{clock_rate, 300, 1}, {clock_rate, 300, 1}}
 {
-	drives_[0].set_sleep_observer(this);
-	drives_[1].set_sleep_observer(this);
+	drives_[0].set_clocking_hint_observer(this);
+	drives_[1].set_clocking_hint_observer(this);
+	drives_[active_drive_].set_event_delegate(this);
 }
 
 void DiskII::set_control(Control control, bool on) {
@@ -36,14 +38,11 @@ void DiskII::set_control(Control control, bool on) {
 		case Control::P3: stepper_mask_ = (stepper_mask_ & 0x7) | (on ? 0x8 : 0x0);	break;
 
 		case Control::Motor:
-			// TODO: does the motor control trigger both motors at once?
-			drives_[0].set_motor_on(on);
-			drives_[1].set_motor_on(on);
-		break;
+			motor_is_enabled_ = on;
+			drives_[active_drive_].set_motor_on(on);
+		return;
 	}
 
-//	printf("%0x: Set control %d %s\n", stepper_mask_, control, on ? "on" : "off");
-
 	// If the stepper magnet selections have changed, and any is on, see how
 	// that moves the head.
 	if(previous_stepper_mask ^ stepper_mask_ && stepper_mask_) {
@@ -63,78 +62,105 @@ void DiskII::set_control(Control control, bool on) {
 	}
 }
 
-void DiskII::set_mode(Mode mode) {
-//	printf("Set mode %d\n", mode);
-	inputs_ = (inputs_ & ~input_mode) | ((mode == Mode::Write) ? input_mode : 0);
-	set_controller_can_sleep();
-}
-
 void DiskII::select_drive(int drive) {
-//	printf("Select drive %d\n", drive);
-	active_drive_ = drive & 1;
+	if((drive&1) == active_drive_) return;
+
 	drives_[active_drive_].set_event_delegate(this);
 	drives_[active_drive_^1].set_event_delegate(nullptr);
+
+	drives_[active_drive_].set_motor_on(false);
+	active_drive_ = drive & 1;
+	drives_[active_drive_].set_motor_on(motor_is_enabled_);
 }
 
-void DiskII::set_data_register(uint8_t value) {
-//	printf("Set data register (?)\n");
-	inputs_ |= input_command;
-	data_register_ = value;
-	set_controller_can_sleep();
-}
-
-uint8_t DiskII::get_shift_register() {
-//	if(shift_register_ & 0x80) printf("[%02x] ", shift_register_);
-	inputs_ &= ~input_command;
-	set_controller_can_sleep();
-	return shift_register_;
-}
+// The read pulse is controlled by a special IC that outputs a 1us pulse for every field reversal on the disk.
 
 void DiskII::run_for(const Cycles cycles) {
-	if(is_sleeping()) return;
+	if(preferred_clocking() == ClockingHint::Preference::None) return;
 
-	int integer_cycles = cycles.as_int();
-
-	if(!controller_can_sleep_) {
-		while(integer_cycles--) {
-			const int address = (state_ & 0xf0) | inputs_ | ((shift_register_&0x80) >> 6);
-			inputs_ |= input_flux;
-			state_ = state_machine_[static_cast<std::size_t>(address)];
-			switch(state_ & 0xf) {
-				case 0x0:	shift_register_ = 0;													break;	// clear
-				case 0x9:	shift_register_ = static_cast<uint8_t>(shift_register_ << 1);			break;	// shift left, bringing in a zero
-				case 0xd:	shift_register_ = static_cast<uint8_t>((shift_register_ << 1) | 1);		break;	// shift left, bringing in a one
-				case 0xb:	shift_register_ = data_register_;										break;	// load
-
-				case 0xa:	// shift right, bringing in write protected status
-					shift_register_ = (shift_register_ >> 1) | (is_write_protected() ? 0x80 : 0x00);
-				break;
-				default: break;
-			}
-
-			// TODO: surely there's a less heavyweight solution than this?
-			if(!drive_is_sleeping_[0]) drives_[0].run_for(Cycles(1));
-			if(!drive_is_sleeping_[1]) drives_[1].run_for(Cycles(1));
+	auto integer_cycles = cycles.as_integral();
+	while(integer_cycles--) {
+		const int address = (state_ & 0xf0) | inputs_ | ((shift_register_&0x80) >> 6);
+		if(flux_duration_) {
+			--flux_duration_;
+			if(!flux_duration_) inputs_ |= input_flux;
 		}
-	} else {
-		if(!drive_is_sleeping_[0]) drives_[0].run_for(cycles);
-		if(!drive_is_sleeping_[1]) drives_[1].run_for(cycles);
+		state_ = state_machine_[static_cast<std::size_t>(address)];
+		switch(state_ & 0xf) {
+			default:	shift_register_ = 0;													break;	// clear
+			case 0x8:																			break;	// nop
+
+			case 0x9:	shift_register_ = static_cast<uint8_t>(shift_register_ << 1);			break;	// shift left, bringing in a zero
+			case 0xd:	shift_register_ = static_cast<uint8_t>((shift_register_ << 1) | 1);		break;	// shift left, bringing in a one
+
+			case 0xa:	// shift right, bringing in write protected status
+				shift_register_ = (shift_register_ >> 1) | (is_write_protected() ? 0x80 : 0x00);
+
+				// If the controller is in the sense write protect loop but the register will never change,
+				// short circuit further work and return now.
+				if(shift_register_ == (is_write_protected() ? 0xff : 0x00)) {
+					if(!drive_is_sleeping_[0]) drives_[0].run_for(Cycles(integer_cycles));
+					if(!drive_is_sleeping_[1]) drives_[1].run_for(Cycles(integer_cycles));
+					decide_clocking_preference();
+					return;
+				}
+			break;
+			case 0xb:	shift_register_ = data_input_;											break;	// load data register from data bus
+		}
+
+		// Currently writing?
+		if(inputs_&input_mode) {
+			// state_ & 0x80 should be the current level sent to the disk;
+			// therefore transitions in that bit should become flux transitions
+			drives_[active_drive_].write_bit(!!((state_ ^ address) & 0x80));
+		}
+
+		// TODO: surely there's a less heavyweight solution than inline updates?
+		if(!drive_is_sleeping_[0]) drives_[0].run_for(Cycles(1));
+		if(!drive_is_sleeping_[1]) drives_[1].run_for(Cycles(1));
 	}
 
-	set_controller_can_sleep();
+	// Per comp.sys.apple2.programmer there is a delay between the controller
+	// motor switch being flipped and the drive motor actually switching off.
+	// This models that, accepting overrun as a risk.
+	if(motor_off_time_ >= 0) {
+		motor_off_time_ -= cycles.as_integral();
+		if(motor_off_time_ < 0) {
+			set_control(Control::Motor, false);
+		}
+	}
+	decide_clocking_preference();
 }
 
-void DiskII::set_controller_can_sleep() {
-	// Permit the controller to sleep if it's in sense write protect mode, and the shift register
-	// has already filled with the result of shifting eight times.
-	controller_can_sleep_ =
-		(inputs_ == (input_command | input_flux)) &&
-		(shift_register_ == (is_write_protected() ? 0xff : 0x00));
-	if(is_sleeping()) update_sleep_observer();
+void DiskII::decide_clocking_preference() {
+	ClockingHint::Preference prior_preference = clocking_preference_;
+
+	// If in read mode, clocking is either:
+	//
+	//	just-in-time, if drives are running or the shift register has any 1s in it or a flux event hasn't yet passed; or
+	//	none, given that drives are not running, the shift register has already emptied and there's no flux about to be received.
+	if(!(inputs_ & ~input_flux)) {
+		clocking_preference_ = (!motor_is_enabled_ && !shift_register_ && (inputs_&input_flux)) ? ClockingHint::Preference::None : ClockingHint::Preference::JustInTime;
+	}
+
+	// If in writing mode, clocking is real time.
+	if(inputs_ & input_mode) {
+		clocking_preference_ = ClockingHint::Preference::RealTime;
+	}
+
+	// If in sense-write-protect mode, clocking is just-in-time if the shift register hasn't yet filled with the value that
+	// corresponds to the current write protect status. Otherwise it is none.
+	if((inputs_ & ~input_flux) == input_command) {
+		clocking_preference_ = (shift_register_ == (is_write_protected() ? 0xff : 0x00)) ? ClockingHint::Preference::None : ClockingHint::Preference::JustInTime;
+	}
+
+	// Announce a change if there was one.
+	if(prior_preference != clocking_preference_)
+		update_clocking_observer();
 }
 
 bool DiskII::is_write_protected() {
-	return true;
+	return !!(stepper_mask_ & 2) | drives_[active_drive_].get_is_read_only();
 }
 
 void DiskII::set_state_machine(const std::vector<uint8_t> &state_machine) {
@@ -143,9 +169,9 @@ void DiskII::set_state_machine(const std::vector<uint8_t> &state_machine) {
 
 			state b0, state b2, state b3, pulse, Q7, Q6, shift, state b1
 
-		... and has the top nibble reflected. Beneath Apple Pro-DOS uses a
-		different order and several of the online copies are reformatted
-		into that order.
+		... and has the top nibble of each value stored in the ROM reflected.
+		Beneath Apple Pro-DOS uses a different order and several of the
+		online copies are reformatted into that order.
 
 		So the code below remaps into Beneath Apple Pro-DOS order if the
 		supplied state machine isn't already in that order.
@@ -185,32 +211,29 @@ void DiskII::set_disk(const std::shared_ptr<Storage::Disk::Disk> &disk, int driv
 	drives_[drive].set_disk(disk);
 }
 
-void DiskII::process_event(const Storage::Disk::Track::Event &event) {
+void DiskII::process_event(const Storage::Disk::Drive::Event &event) {
 	if(event.type == Storage::Disk::Track::Event::FluxTransition) {
 		inputs_ &= ~input_flux;
-		set_controller_can_sleep();
+		flux_duration_ = 2;	// Upon detection of a flux transition, the flux flag should stay set for 1us. Emulate that as two cycles.
+		decide_clocking_preference();
 	}
 }
 
-void DiskII::set_component_is_sleeping(Sleeper *component, bool is_sleeping) {
-	drive_is_sleeping_[0] = drives_[0].is_sleeping();
-	drive_is_sleeping_[1] = drives_[1].is_sleeping();
-	update_sleep_observer();
+void DiskII::set_component_prefers_clocking(ClockingHint::Source *component, ClockingHint::Preference preference) {
+	drive_is_sleeping_[0] = drives_[0].preferred_clocking() == ClockingHint::Preference::None;
+	drive_is_sleeping_[1] = drives_[1].preferred_clocking() == ClockingHint::Preference::None;
+	decide_clocking_preference();
 }
 
-bool DiskII::is_sleeping() {
-	return controller_can_sleep_ && drive_is_sleeping_[0] && drive_is_sleeping_[1];
+ClockingHint::Preference DiskII::preferred_clocking() {
+	return clocking_preference_;
 }
 
-void DiskII::set_register(int address, uint8_t value) {
-	trigger_address(address, value);
+void DiskII::set_data_input(uint8_t input) {
+	data_input_ = input;
 }
 
-uint8_t DiskII::get_register(int address) {
-	return trigger_address(address, 0xff);
-}
-
-uint8_t DiskII::trigger_address(int address, uint8_t value) {
+int DiskII::read_address(int address) {
 	switch(address & 0xf) {
 		default:
 		case 0x0:	set_control(Control::P0, false);	break;
@@ -222,22 +245,40 @@ uint8_t DiskII::trigger_address(int address, uint8_t value) {
 		case 0x6:	set_control(Control::P3, false);	break;
 		case 0x7:	set_control(Control::P3, true);		break;
 
-		case 0x8:	set_control(Control::Motor, false);	break;
-		case 0x9:	set_control(Control::Motor, true);	break;
+		case 0x8:
+			shift_register_ = 0;
+			motor_off_time_ = clock_rate_;
+		break;
+		case 0x9:
+			set_control(Control::Motor, true);
+			motor_off_time_ = -1;
+		break;
 
 		case 0xa:	select_drive(0);					break;
 		case 0xb:	select_drive(1);					break;
 
-		case 0xc:	return get_shift_register();
-		case 0xd:	set_data_register(value);			break;
-
-		case 0xe:	set_mode(Mode::Read);				break;
-		case 0xf:	set_mode(Mode::Write);				break;
+		case 0xc:	inputs_ &= ~input_command;			break;
+		case 0xd:	inputs_ |= input_command;			break;
+		case 0xe:
+			if(inputs_ & input_mode)
+				drives_[active_drive_].end_writing();
+			inputs_ &= ~input_mode;
+		break;
+		case 0xf:
+			if(!(inputs_ & input_mode))
+				drives_[active_drive_].begin_writing(Storage::Time(1, int(clock_rate_)), false);
+			inputs_ |= input_mode;
+		break;
 	}
-	return 0xff;
+	decide_clocking_preference();
+	return (address & 1) ? 0xff : shift_register_;
 }
 
 void DiskII::set_activity_observer(Activity::Observer *observer) {
 	drives_[0].set_activity_observer(observer, "Drive 1", true);
 	drives_[1].set_activity_observer(observer, "Drive 2", true);
 }
+
+Storage::Disk::Drive &DiskII::get_drive(int index) {
+	return drives_[index];
+}

Components/DiskII/DiskII.hpp

@@ -10,7 +10,7 @@
 #define DiskII_hpp
 
 #include "../../ClockReceiver/ClockReceiver.hpp"
-#include "../../ClockReceiver/Sleeper.hpp"
+#include "../../ClockReceiver/ClockingHintSource.hpp"
 
 #include "../../Storage/Disk/Disk.hpp"
 #include "../../Storage/Disk/Drive.hpp"
@@ -26,24 +26,65 @@ namespace Apple {
 /*!
 	Provides an emulation of the Apple Disk II.
 */
-class DiskII:
+class DiskII :
 	public Storage::Disk::Drive::EventDelegate,
-	public Sleeper::SleepObserver,
-	public Sleeper {
+	public ClockingHint::Source,
+	public ClockingHint::Observer {
 	public:
-		DiskII();
+		DiskII(int clock_rate);
 
-		void set_register(int address, uint8_t value);
-		uint8_t get_register(int address);
+		/// Sets the current external value of the data bus.
+		void set_data_input(uint8_t input);
 
+		/*!
+			Submits an access to address @c address.
+
+			@returns The 8-bit value loaded to the data bus by the DiskII if any;
+				@c DidNotLoad otherwise.
+		*/
+		int read_address(int address);
+
+		/*!
+			The value returned by @c read_address if accessing that address
+			didn't cause the disk II to place anything onto the bus.
+		*/
+		static constexpr int DidNotLoad = -1;
+
+		/// Advances the controller by @c cycles.
 		void run_for(const Cycles cycles);
+
+		/*!
+			Supplies the image of the state machine (i.e. P6) ROM,
+			which dictates how the Disk II will respond to input.
+
+			To reduce processing costs, some assumptions are made by
+			the implementation as to the content of this ROM.
+			Including:
+
+			*	If Q6 is set and Q7 is reset, the controller is testing
+				for write protect. If and when the shift register has
+				become full with the state of the write protect value,
+				no further processing is required.
+
+			*	If both Q6 and Q7 are reset, the drive motor is disabled,
+				and the shift register is all zeroes, no further processing
+				is required.
+		*/
 		void set_state_machine(const std::vector<uint8_t> &);
 
+		/// Inserts @c disk into the drive @c drive.
 		void set_disk(const std::shared_ptr<Storage::Disk::Disk> &disk, int drive);
-		bool is_sleeping() override;
 
+		// As per Sleeper.
+		ClockingHint::Preference preferred_clocking() final;
+
+		// The Disk II functions as a potential target for @c Activity::Sources.
 		void set_activity_observer(Activity::Observer *observer);
 
+		// Returns the Storage::Disk::Drive in use for drive @c index.
+		// *NOT FOR HARDWARE EMULATION USAGE*.
+		Storage::Disk::Drive &get_drive(int index);
+
 	private:
 		enum class Control {
 			P0, P1, P2, P3,
@@ -55,29 +96,33 @@ class DiskII:
 		void set_control(Control control, bool on);
 		void set_mode(Mode mode);
 		void select_drive(int drive);
-		void set_data_register(uint8_t value);
-		uint8_t get_shift_register();
 
 		uint8_t trigger_address(int address, uint8_t value);
-		void process_event(const Storage::Disk::Track::Event &event) override;
-		void set_component_is_sleeping(Sleeper *component, bool is_sleeping) override;
+		void process_event(const Storage::Disk::Drive::Event &event) final;
+		void set_component_prefers_clocking(ClockingHint::Source *component, ClockingHint::Preference preference) final;
+
+		const Cycles::IntType clock_rate_ = 0;
 
 		uint8_t state_ = 0;
 		uint8_t inputs_ = 0;
 		uint8_t shift_register_ = 0;
-		uint8_t data_register_ = 0;
 
 		int stepper_mask_ = 0;
 		int stepper_position_ = 0;
+		Cycles::IntType motor_off_time_ = -1;
 
 		bool is_write_protected();
 		std::array<uint8_t, 256> state_machine_;
 		Storage::Disk::Drive drives_[2];
 		bool drive_is_sleeping_[2];
-		bool controller_can_sleep_ = false;
 		int active_drive_ = 0;
+		bool motor_is_enabled_ = false;
 
-		void set_controller_can_sleep();
+		void decide_clocking_preference();
+		ClockingHint::Preference clocking_preference_ = ClockingHint::Preference::RealTime;
+
+		uint8_t data_input_ = 0;
+		int flux_duration_ = 0;
 };
 
 }

Components/DiskII/IWM.cpp

@@ -0,0 +1,406 @@
+//
+//  IWM.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 05/05/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#include "IWM.hpp"
+
+#include "../../Outputs/Log.hpp"
+
+using namespace Apple;
+
+namespace  {
+	constexpr int CA0		= 1 << 0;
+	constexpr int CA1		= 1 << 1;
+	constexpr int CA2		= 1 << 2;
+	constexpr int LSTRB		= 1 << 3;
+	constexpr int ENABLE	= 1 << 4;
+	constexpr int DRIVESEL	= 1 << 5;	/* This means drive select, like on the original Disk II. */
+	constexpr int Q6		= 1 << 6;
+	constexpr int Q7		= 1 << 7;
+	constexpr int SEL		= 1 << 8;	/* This is an additional input, not available on a Disk II, with a confusingly-similar name to SELECT but a distinct purpose. */
+}
+
+IWM::IWM(int clock_rate) :
+	clock_rate_(clock_rate) {}
+
+// MARK: - Bus accessors
+
+uint8_t IWM::read(int address) {
+	access(address);
+
+	// Per Inside Macintosh:
+	//
+	// "Before you can read from any of the disk registers you must set up the state of the IWM so that it
+	// can pass the data through to the MC68000's address space where you'll be able to read it. To do that,
+	// you must first turn off Q7 by reading or writing dBase+q7L. Then turn on Q6 by accessing dBase+q6H.
+	// After that, the IWM will be able to pass data from the disk's RD/SENSE line through to you."
+	//
+	// My understanding:
+	//
+	//	Q6 = 1, Q7 = 0 reads the status register. The meaning of the top 'SENSE' bit is then determined by
+	//	the CA0,1,2 and SEL switches as described in Inside Macintosh, summarised above as RD/SENSE.
+
+	if(address&1) {
+		return 0xff;
+	}
+
+	switch(state_ & (Q6 | Q7 | ENABLE)) {
+		default:
+			LOG("[IWM] Invalid read\n");
+		return 0xff;
+
+		// "Read all 1s".
+//			printf("Reading all 1s\n");
+//		return 0xff;
+
+		case 0:
+		case ENABLE: {				/* Read data register. Zeroing afterwards is a guess. */
+			const auto result = data_register_;
+
+			if(data_register_ & 0x80) {
+//				printf("\n\nIWM:%02x\n\n", data_register_);
+//				printf(".");
+				data_register_ = 0;
+			}
+//			LOG("Reading data register: " << PADHEX(2) << int(result));
+
+			return result;
+		}
+
+		case Q6: case Q6|ENABLE: {
+			/*
+				[If A = 0], Read status register:
+
+				bits 0-4: same as mode register.
+				bit 5: 1 = either /ENBL1 or /ENBL2 is currently low.
+				bit 6: 1 = MZ (reserved for future compatibility; should always be read as 0).
+				bit 7: 1 = SENSE input high; 0 = SENSE input low.
+
+				(/ENBL1 is low when the first drive's motor is on; /ENBL2 is low when the second drive's motor is on.
+				If the 1-second timer is enabled, motors remain on for one second after being programmatically disabled.)
+			*/
+
+			return uint8_t(
+				(mode_&0x1f) |
+				((state_ & ENABLE) ? 0x20 : 0x00) |
+				(sense() & 0x80)
+			);
+		} break;
+
+		case Q7: case Q7|ENABLE:
+			/*
+				Read write-handshake register:
+
+				bits 0-5: reserved for future use (currently read as 1).
+				bit 6: 1 = write state (0 = underrun has occurred; 1 = no underrun so far).
+				bit 7: 1 = write data buffer ready for data (1 = ready; 0 = busy).
+			*/
+//			LOG("Reading write handshake: " << PADHEX(2) << (0x3f | write_handshake_));
+		return 0x3f | write_handshake_;
+	}
+
+	return 0xff;
+}
+
+void IWM::write(int address, uint8_t input) {
+	access(address);
+
+	switch(state_ & (Q6 | Q7 | ENABLE)) {
+		default: break;
+
+		case Q7|Q6:
+			/*
+				Write mode register:
+
+				bit 0: 1 = latch mode (should be set in asynchronous mode).
+				bit 1: 0 = synchronous handshake protocol; 1 = asynchronous.
+				bit 2: 0 = 1-second on-board timer enable; 1 = timer disable.
+				bit 3: 0 = slow mode; 1 = fast mode.
+				bit 4: 0 = 7Mhz; 1 = 8Mhz (7 or 8 mHz clock descriptor).
+				bit 5: 1 = test mode; 0 = normal operation.
+				bit 6: 1 = MZ-reset.
+				bit 7: reserved for future expansion.
+			*/
+
+			mode_ = input;
+
+			switch(mode_ & 0x18) {
+				case 0x00:		bit_length_ = Cycles(24);		break;	// slow mode, 7Mhz
+				case 0x08:		bit_length_ = Cycles(12);		break;	// fast mode, 7Mhz
+				case 0x10:		bit_length_ = Cycles(32);		break;	// slow mode, 8Mhz
+				case 0x18:		bit_length_ = Cycles(16);		break;	// fast mode, 8Mhz
+			}
+			LOG("IWM mode is now " << PADHEX(2) << int(mode_));
+		break;
+
+		case Q7|Q6|ENABLE:	// Write data register.
+			next_output_ = input;
+			write_handshake_ &= ~0x80;
+		break;
+	}
+}
+
+// MARK: - Switch access
+
+void IWM::access(int address) {
+	// Keep a record of switch state; bits in state_
+	// should correlate with the anonymous namespace constants
+	// defined at the top of this file — CA0, CA1, etc.
+	address &= 0xf;
+	const auto mask = 1 << (address >> 1);
+	const auto old_state = state_;
+
+	if(address & 1) {
+		state_ |= mask;
+	} else {
+		state_ &= ~mask;
+	}
+
+	// React appropriately to ENABLE and DRIVESEL changes, and changes into/out of write mode.
+	if(old_state != state_) {
+		push_drive_state();
+
+		switch(mask) {
+			default: break;
+
+			case ENABLE:
+				if(address & 1) {
+					if(drives_[active_drive_]) drives_[active_drive_]->set_enabled(true);
+				} else {
+					// If the 1-second delay is enabled, set up a timer for that.
+					if(!(mode_ & 4)) {
+						cycles_until_disable_ = Cycles(clock_rate_);
+					} else {
+						if(drives_[active_drive_]) drives_[active_drive_]->set_enabled(false);
+					}
+				}
+			break;
+
+			case DRIVESEL: {
+				const int new_drive = address & 1;
+				if(new_drive != active_drive_) {
+					if(drives_[active_drive_]) drives_[active_drive_]->set_enabled(false);
+					active_drive_ = new_drive;
+					if(drives_[active_drive_]) {
+						drives_[active_drive_]->set_enabled(state_ & ENABLE || (cycles_until_disable_ > Cycles(0)));
+						push_drive_state();
+					}
+				}
+			} break;
+
+			case Q6:
+			case Q7:
+				select_shift_mode();
+			break;
+		}
+	}
+}
+
+void IWM::set_select(bool enabled) {
+	// Store SEL as an extra state bit.
+	if(enabled) state_ |= SEL;
+	else state_ &= ~SEL;
+	push_drive_state();
+}
+
+void IWM::push_drive_state() {
+	if(drives_[active_drive_])  {
+		const uint8_t drive_control_lines =
+			((state_ & CA0) ? IWMDrive::CA0 : 0) |
+			((state_ & CA1) ? IWMDrive::CA1 : 0) |
+			((state_ & CA2) ? IWMDrive::CA2 : 0) |
+			((state_ & SEL) ? IWMDrive::SEL : 0) |
+			((state_ & LSTRB) ? IWMDrive::LSTRB : 0);
+		drives_[active_drive_]->set_control_lines(drive_control_lines);
+	}
+}
+
+// MARK: - Active logic
+
+void IWM::run_for(const Cycles cycles) {
+	// Check for a timeout of the motor-off timer.
+	if(cycles_until_disable_ > Cycles(0)) {
+		cycles_until_disable_ -= cycles;
+		if(cycles_until_disable_ <= Cycles(0)) {
+			cycles_until_disable_ = Cycles(0);
+			if(drives_[active_drive_])
+				drives_[active_drive_]->set_enabled(false);
+		}
+	}
+
+	// Activity otherwise depends on mode and motor state.
+	auto integer_cycles = cycles.as_integral();
+	switch(shift_mode_) {
+		case ShiftMode::Reading: {
+			// Per the IWM patent, column 7, around line 35 onwards: "The expected time
+			// is widened by approximately one-half an interval before and after the
+			// expected time since the data is not precisely spaced when read due to
+			// variations in drive speed and other external factors". The error_margin
+			// here implements the 'after' part of that contract.
+			const auto error_margin = Cycles(bit_length_.as_integral() >> 1);
+
+			if(drive_is_rotating_[active_drive_]) {
+				while(integer_cycles--) {
+					drives_[active_drive_]->run_for(Cycles(1));
+					++cycles_since_shift_;
+					if(cycles_since_shift_ == bit_length_ + error_margin) {
+						propose_shift(0);
+					}
+				}
+			} else {
+				while(cycles_since_shift_ + integer_cycles >= bit_length_ + error_margin) {
+					const auto run_length = bit_length_ + error_margin - cycles_since_shift_;
+					integer_cycles -= run_length.as_integral();
+					cycles_since_shift_ += run_length;
+					propose_shift(0);
+				}
+				cycles_since_shift_ += Cycles(integer_cycles);
+			}
+		} break;
+
+		case ShiftMode::Writing:
+			if(drives_[active_drive_]->is_writing()) {
+				while(cycles_since_shift_ + integer_cycles >= bit_length_) {
+					const auto cycles_until_write = bit_length_ - cycles_since_shift_;
+					drives_[active_drive_]->run_for(cycles_until_write);
+
+					// Output a flux transition if the top bit is set.
+					drives_[active_drive_]->write_bit(shift_register_ & 0x80);
+					shift_register_ <<= 1;
+
+					integer_cycles -= cycles_until_write.as_integral();
+					cycles_since_shift_ = Cycles(0);
+
+					--output_bits_remaining_;
+					if(!output_bits_remaining_) {
+						if(!(write_handshake_ & 0x80)) {
+							write_handshake_ |= 0x80;
+							shift_register_ = next_output_;
+							output_bits_remaining_ = 8;
+//							LOG("Next byte: " << PADHEX(2) << int(shift_register_));
+						} else {
+							write_handshake_ &= ~0x40;
+							drives_[active_drive_]->end_writing();
+//							printf("\n");
+							LOG("Overrun; done.");
+							select_shift_mode();
+						}
+					}
+				}
+
+				cycles_since_shift_ = integer_cycles;
+				if(integer_cycles) {
+					drives_[active_drive_]->run_for(cycles_since_shift_);
+				}
+			} else {
+				drives_[active_drive_]->run_for(cycles);
+			}
+		break;
+
+		case ShiftMode::CheckingWriteProtect:
+			if(integer_cycles < 8) {
+				shift_register_ = (shift_register_ >> integer_cycles) | (sense() & (0xff << (8 - integer_cycles)));
+			} else {
+				shift_register_ = sense();
+			}
+
+		/* Deliberate fallthrough. */
+		default:
+			if(drive_is_rotating_[active_drive_]) drives_[active_drive_]->run_for(cycles);
+		break;
+	}
+}
+
+void IWM::select_shift_mode() {
+	// Don't allow an ongoing write to be interrupted.
+	if(shift_mode_ == ShiftMode::Writing && drives_[active_drive_] && drives_[active_drive_]->is_writing()) return;
+
+	const auto old_shift_mode = shift_mode_;
+
+	switch(state_ & (Q6|Q7)) {
+		default:	shift_mode_ = ShiftMode::CheckingWriteProtect;		break;
+		case 0:		shift_mode_ = ShiftMode::Reading;					break;
+		case Q7:
+			// "The IWM is put into the write state by a transition from the write protect sense state to the
+			// write load state".
+			if(shift_mode_ == ShiftMode::CheckingWriteProtect) shift_mode_ = ShiftMode::Writing;
+		break;
+	}
+
+	// If writing mode just began, set the drive into write mode and cue up the first output byte.
+	if(drives_[active_drive_] && old_shift_mode != ShiftMode::Writing && shift_mode_ == ShiftMode::Writing) {
+		drives_[active_drive_]->begin_writing(Storage::Time(1, clock_rate_ / bit_length_.as_integral()), false);
+		shift_register_ = next_output_;
+		write_handshake_ |= 0x80 | 0x40;
+		output_bits_remaining_ = 8;
+		LOG("Seeding output with " << PADHEX(2) << shift_register_);
+	}
+}
+
+uint8_t IWM::sense() {
+	return drives_[active_drive_] ? (drives_[active_drive_]->read() ? 0xff : 0x00) : 0xff;
+}
+
+void IWM::process_event(const Storage::Disk::Drive::Event &event) {
+	if(shift_mode_ != ShiftMode::Reading) return;
+
+	switch(event.type) {
+		case Storage::Disk::Track::Event::IndexHole: return;
+		case Storage::Disk::Track::Event::FluxTransition:
+			propose_shift(1);
+		break;
+	}
+}
+
+void IWM::propose_shift(uint8_t bit) {
+	// TODO: synchronous mode.
+
+//	LOG("Shifting input");
+
+	// See above for text from the IWM patent, column 7, around line 35 onwards.
+	// The error_margin here implements the 'before' part of that contract.
+	//
+	// Basic effective logic: if at least 1 is fozund in the bit_length_ cycles centred
+	// on the current expected bit delivery time as implied by cycles_since_shift_,
+	// shift in a 1 and start a new window wherever the first found 1 was.
+	//
+	// If no 1s are found, shift in a 0 and don't alter expectations as to window placement.
+	const auto error_margin = Cycles(bit_length_.as_integral() >> 1);
+	if(bit && cycles_since_shift_ < error_margin) return;
+
+	shift_register_ = uint8_t((shift_register_ << 1) | bit);
+	if(shift_register_ & 0x80) {
+		data_register_ = shift_register_;
+		shift_register_ = 0;
+	}
+
+	if(bit)
+		cycles_since_shift_ = Cycles(0);
+	else
+		cycles_since_shift_ -= bit_length_;
+}
+
+void IWM::set_drive(int slot, IWMDrive *drive) {
+	drives_[slot] = drive;
+	drive->set_event_delegate(this);
+	drive->set_clocking_hint_observer(this);
+}
+
+void IWM::set_component_prefers_clocking(ClockingHint::Source *component, ClockingHint::Preference clocking) {
+	const bool is_rotating = clocking != ClockingHint::Preference::None;
+
+	if(component == static_cast<ClockingHint::Source *>(drives_[0])) {
+		drive_is_rotating_[0] = is_rotating;
+	} else {
+		drive_is_rotating_[1] = is_rotating;
+	}
+}
+
+void IWM::set_activity_observer(Activity::Observer *observer) {
+	if(drives_[0]) drives_[0]->set_activity_observer(observer, "Internal Floppy", true);
+	if(drives_[1]) drives_[1]->set_activity_observer(observer, "External Floppy", true);
+}

Components/DiskII/IWM.hpp

@@ -0,0 +1,124 @@
+//
+//  IWM.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 05/05/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef IWM_hpp
+#define IWM_hpp
+
+#include "../../Activity/Observer.hpp"
+
+#include "../../ClockReceiver/ClockReceiver.hpp"
+#include "../../ClockReceiver/ClockingHintSource.hpp"
+
+#include "../../Storage/Disk/Drive.hpp"
+
+#include <cstdint>
+
+namespace Apple {
+
+/*!
+	Defines the drive interface used by the IWM, derived from the external pinout as
+	per e.g. https://old.pinouts.ru/HD/MacExtDrive_pinout.shtml
+
+	These are subclassed of Storage::Disk::Drive, so accept any disk the emulator supports,
+	and provide the usual read/write interface for on-disk data.
+*/
+struct IWMDrive: public Storage::Disk::Drive {
+	IWMDrive(int input_clock_rate, int number_of_heads) : Storage::Disk::Drive(input_clock_rate, number_of_heads) {}
+
+	enum Line: int {
+		CA0		= 1 << 0,
+		CA1		= 1 << 1,
+		CA2		= 1 << 2,
+		LSTRB	= 1 << 3,
+		SEL		= 1 << 4,
+	};
+
+	virtual void set_enabled(bool) = 0;
+	virtual void set_control_lines(int) = 0;
+	virtual bool read() = 0;
+};
+
+class IWM:
+	public Storage::Disk::Drive::EventDelegate,
+	public ClockingHint::Observer {
+	public:
+		IWM(int clock_rate);
+
+		/// Sets the current external value of the data bus.
+		void write(int address, uint8_t value);
+
+		/*!
+			Submits an access to address @c address.
+
+			@returns The 8-bit value loaded to the data bus by the IWM.
+		*/
+		uint8_t read(int address);
+
+		/*!
+			Sets the current input of the IWM's SEL line.
+		*/
+		void set_select(bool enabled);
+
+		/// Advances the controller by @c cycles.
+		void run_for(const Cycles cycles);
+
+		/// Connects a drive to the IWM.
+		void set_drive(int slot, IWMDrive *drive);
+
+		/// Registers the currently-connected drives as @c Activity::Sources ;
+		/// the first will be declared 'Internal', the second 'External'.
+		void set_activity_observer(Activity::Observer *observer);
+
+	private:
+		// Storage::Disk::Drive::EventDelegate.
+		void process_event(const Storage::Disk::Drive::Event &event) final;
+
+		const int clock_rate_;
+
+		uint8_t data_register_ = 0;
+		uint8_t mode_ = 0;
+		bool read_write_ready_ = true;
+		bool write_overran_ = false;
+
+		int state_ = 0;
+
+		int active_drive_ = 0;
+		IWMDrive *drives_[2] = {nullptr, nullptr};
+		bool drive_is_rotating_[2] = {false, false};
+
+		void set_component_prefers_clocking(ClockingHint::Source *component, ClockingHint::Preference clocking) final;
+
+		Cycles cycles_until_disable_;
+		uint8_t write_handshake_ = 0x80;
+
+		void access(int address);
+
+		uint8_t shift_register_ = 0;
+		uint8_t next_output_ = 0;
+		int output_bits_remaining_ = 0;
+
+		void propose_shift(uint8_t bit);
+		Cycles cycles_since_shift_;
+		Cycles bit_length_ = Cycles(16);
+
+		void push_drive_state();
+
+		enum class ShiftMode {
+			Reading,
+			Writing,
+			CheckingWriteProtect
+		} shift_mode_;
+
+		uint8_t sense();
+		void select_shift_mode();
+};
+
+
+}
+
+#endif /* IWM_hpp */

Components/DiskII/MacintoshDoubleDensityDrive.cpp

@@ -0,0 +1,181 @@
+//
+//  MacintoshDoubleDensityDrive.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 10/07/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#include "MacintoshDoubleDensityDrive.hpp"
+
+/*
+	Sources used pervasively:
+
+	http://members.iinet.net.au/~kalandi/apple/AUG/1991/11%20NOV.DEC/DISK.STUFF.html
+	Apple Guide to the Macintosh Family Hardware
+	Inside Macintosh III
+*/
+
+using namespace Apple::Macintosh;
+
+DoubleDensityDrive::DoubleDensityDrive(int input_clock_rate, bool is_800k) :
+	IWMDrive(input_clock_rate, is_800k ? 2 : 1),	// Only 800kb drives are double sided.
+	is_800k_(is_800k) {
+	// Start with a valid rotation speed.
+	if(is_800k) {
+		Drive::set_rotation_speed(393.3807f);
+	}
+}
+
+// MARK: - Speed Selection
+
+void DoubleDensityDrive::did_step(Storage::Disk::HeadPosition to_position) {
+//	printf("At track %d\n", to_position.as_int());
+	// The 800kb drive automatically selects rotation speed as a function of
+	// head position; the 400kb drive doesn't do so.
+	if(is_800k_) {
+		/*
+			Numbers below cribbed from the Kryoflux forums; specifically:
+			https://forum.kryoflux.com/viewtopic.php?t=1090
+
+			They can almost be worked out algorithmically, since the point is to
+			produce an almost-constant value for speed*(number of sectors), and:
+
+			393.3807 * 12 = 4720.5684
+			429.1723 * 11 = 4720.895421
+			472.1435 * 10 = 4721.435
+			524.5672 * 9 = 4721.1048
+			590.1098 * 8 = 4720.8784
+
+			So 4721 / (number of sectors per track in zone) would give essentially
+			the same results.
+		*/
+		const int zone = to_position.as_int() >> 4;
+		switch(zone) {
+			case 0:		Drive::set_rotation_speed(393.3807f);	break;
+			case 1:		Drive::set_rotation_speed(429.1723f);	break;
+			case 2:		Drive::set_rotation_speed(472.1435f);	break;
+			case 3:		Drive::set_rotation_speed(524.5672f);	break;
+			default:	Drive::set_rotation_speed(590.1098f);	break;
+		}
+	}
+}
+
+void DoubleDensityDrive::set_rotation_speed(float revolutions_per_minute) {
+	if(!is_800k_) {
+		// Don't allow drive speeds to drop below 10 RPM, as a temporary sop
+		// to sanity.
+		Drive::set_rotation_speed(std::max(10.0f, revolutions_per_minute));
+	}
+}
+
+// MARK: - Control input/output.
+
+void DoubleDensityDrive::set_enabled(bool enabled) {
+	// Disabling a drive also stops its motor.
+	if(!enabled) set_motor_on(false);
+}
+
+void DoubleDensityDrive::set_control_lines(int lines) {
+	const auto old_state = control_state_;
+	control_state_ = lines;
+
+	// Catch low-to-high LSTRB transitions.
+	if((old_state ^ control_state_) & control_state_ & Line::LSTRB) {
+		switch(control_state_ & (Line::CA2 | Line::CA1 | Line::CA0 | Line::SEL)) {
+			default:
+			break;
+
+			case 0:						// Set step direction — CA2 set => step outward.
+			case Line::CA2:
+				step_direction_ = (control_state_ & Line::CA2) ? -1 : 1;
+			break;
+
+			case Line::CA1:				// Set drive motor — CA2 set => motor off.
+			case Line::CA1|Line::CA2:
+				set_motor_on(!(control_state_ & Line::CA2));
+			break;
+
+			case Line::CA0:				// Initiate a step.
+				step(Storage::Disk::HeadPosition(step_direction_));
+			break;
+
+			case Line::SEL|Line::CA2:	// Reset new disk flag.
+				has_new_disk_ = false;
+			break;
+
+			case Line::CA2 | Line::CA1 | Line::CA0:	// Eject the disk.
+				set_disk(nullptr);
+			break;
+		}
+	}
+}
+
+bool DoubleDensityDrive::read() {
+	switch(control_state_ & (CA2 | CA1 | CA0 | SEL)) {
+		default:
+		return false;
+
+		case 0:					// Head step direction.
+								// (0 = inward)
+		return step_direction_ <= 0;
+
+		case SEL:				// Disk in place.
+								// (0 = disk present)
+		return !has_disk();
+
+		case CA0:				// Disk head step completed.
+								// (0 = still stepping)
+		return true;	// TODO: stepping delay. But at the main Drive level.
+
+		case CA0|SEL:			// Disk locked.
+								// (0 = write protected)
+		return !get_is_read_only();
+
+		case CA1:				// Disk motor running.
+								// (0 = motor on)
+		return !get_motor_on();
+
+		case CA1|SEL:			// Head at track 0.
+								// (0 = at track 0)
+								// "This bit becomes valid beginning 12 msec after the step that places the head at track 0."
+		return !get_is_track_zero();
+
+		case CA1|CA0:			// Disk has been ejected.
+								// (0 = user has ejected disk)
+		return !has_new_disk_;
+
+		case CA1|CA0|SEL:		// Tachometer.
+								// (arbitrary)
+		return get_tachometer();
+
+		case CA2:				// Read data, lower head.
+			set_head(0);
+		return false;
+
+		case CA2|SEL:			// Read data, upper head.
+			set_head(1);
+		return false;
+
+		case CA2|CA1:			// Single- or double-sided drive.
+								// (0 = single sided)
+		return get_head_count() != 1;
+
+		case CA2|CA1|CA0:		// "Present/HD" (per the Mac Plus ROM)
+								// (0 = ??HD??)
+								//
+								// Alternative explanation: "Disk ready for reading?"
+								// (0 = ready)
+		return false;
+
+		case CA2|CA1|CA0|SEL:	// Drive installed.
+								// (0 = present, 1 = missing)
+								//
+								// TODO: why do I need to return this the wrong way around for the Mac Plus?
+		return true;
+	}
+}
+
+void DoubleDensityDrive::did_set_disk() {
+	has_new_disk_ = true;
+}

Components/DiskII/MacintoshDoubleDensityDrive.hpp

@@ -0,0 +1,53 @@
+//
+//  MacintoshDoubleDensityDrive.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 10/07/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef MacintoshDoubleDensityDrive_hpp
+#define MacintoshDoubleDensityDrive_hpp
+
+#include "IWM.hpp"
+
+namespace Apple {
+namespace Macintosh {
+
+class DoubleDensityDrive: public IWMDrive {
+	public:
+		DoubleDensityDrive(int input_clock_rate, bool is_800k);
+
+		/*!
+			@returns @c true if this is an 800kb drive; @c false otherwise.
+		*/
+		bool is_800k() {
+			return is_800k_;
+		}
+
+		/*!
+			Sets the current rotation speed of this drive only if it is a 400kb drive.
+			800kb drives select their own rotation speed based on head position,
+			and ignore this input.
+		*/
+		void set_rotation_speed(float revolutions_per_minute);
+
+	private:
+		void set_enabled(bool) final;
+		void set_control_lines(int) final;
+		bool read() final;
+
+		// To receive the proper notifications from Storage::Disk::Drive.
+		void did_step(Storage::Disk::HeadPosition to_position) final;
+		void did_set_disk() final;
+
+		const bool is_800k_;
+		bool has_new_disk_ = false;
+		int control_state_ = 0;
+		int step_direction_ = 1;
+};
+
+}
+}
+
+#endif /* MacintoshDoubleDensityDrive_hpp */

Components/SN76489/SN76489.cpp

@@ -48,7 +48,7 @@ void SN76489::set_sample_volume_range(std::int16_t range) {
 	evaluate_output_volume();
 }
 
-void SN76489::set_register(uint8_t value) {
+void SN76489::write(uint8_t value) {
 	task_queue_.defer([value, this] () {
 		if(value & 0x80) {
 			active_register_ = value;

Components/SN76489/SN76489.hpp

@@ -26,7 +26,7 @@ class SN76489: public Outputs::Speaker::SampleSource {
 		SN76489(Personality personality, Concurrency::DeferringAsyncTaskQueue &task_queue, int additional_divider = 1);
 
 		/// Writes a new value to the SN76489.
-		void set_register(uint8_t value);
+		void write(uint8_t value);
 
 		// As per SampleSource.
 		void get_samples(std::size_t number_of_samples, std::int16_t *target);

Components/Serial/Line.cpp

@@ -0,0 +1,140 @@
+//
+//  SerialPort.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 12/10/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#include "Line.hpp"
+
+using namespace Serial;
+
+void Line::set_writer_clock_rate(HalfCycles clock_rate) {
+	clock_rate_ = clock_rate;
+}
+
+void Line::advance_writer(HalfCycles cycles) {
+	if(cycles == HalfCycles(0)) return;
+
+	const auto integral_cycles = cycles.as_integral();
+	remaining_delays_ = std::max(remaining_delays_ - integral_cycles, Cycles::IntType(0));
+	if(events_.empty()) {
+		write_cycles_since_delegate_call_ += integral_cycles;
+		if(transmission_extra_) {
+			transmission_extra_ -= integral_cycles;
+			if(transmission_extra_ <= 0) {
+				transmission_extra_ = 0;
+				update_delegate(level_);
+			}
+		}
+	} else {
+		while(!events_.empty()) {
+			if(events_.front().delay <= integral_cycles) {
+				cycles -= events_.front().delay;
+				write_cycles_since_delegate_call_ += events_.front().delay;
+				const auto old_level = level_;
+
+				auto iterator = events_.begin() + 1;
+				while(iterator != events_.end() && iterator->type != Event::Delay) {
+					level_ = iterator->type == Event::SetHigh;
+					++iterator;
+				}
+				events_.erase(events_.begin(), iterator);
+
+				if(old_level != level_) {
+					update_delegate(old_level);
+				}
+
+				// Book enough extra time for the read delegate to be posted
+				// the final bit if one is attached.
+				if(events_.empty()) {
+					transmission_extra_ = minimum_write_cycles_for_read_delegate_bit();
+				}
+			} else {
+				events_.front().delay -= integral_cycles;
+				write_cycles_since_delegate_call_ += integral_cycles;
+				break;
+			}
+		}
+	}
+}
+
+void Line::write(bool level) {
+	if(!events_.empty()) {
+		events_.emplace_back();
+		events_.back().type = level ? Event::SetHigh : Event::SetLow;
+	} else {
+		level_ = level;
+		transmission_extra_ = minimum_write_cycles_for_read_delegate_bit();
+	}
+}
+
+void Line::write(HalfCycles cycles, int count, int levels) {
+	remaining_delays_ += count * cycles.as_integral();
+
+	auto event = events_.size();
+	events_.resize(events_.size() + size_t(count)*2);
+	while(count--) {
+		events_[event].type = Event::Delay;
+		events_[event].delay = int(cycles.as_integral());
+		events_[event+1].type = (levels&1) ? Event::SetHigh : Event::SetLow;
+		levels >>= 1;
+		event += 2;
+	}
+}
+
+void Line::reset_writing() {
+	remaining_delays_ = 0;
+	events_.clear();
+}
+
+bool Line::read() {
+	return level_;
+}
+
+void Line::set_read_delegate(ReadDelegate *delegate, Storage::Time bit_length) {
+	read_delegate_ = delegate;
+	read_delegate_bit_length_ = bit_length;
+	read_delegate_bit_length_.simplify();
+	write_cycles_since_delegate_call_ = 0;
+}
+
+void Line::update_delegate(bool level) {
+	// Exit early if there's no delegate, or if the delegate is waiting for
+	// zero and this isn't zero.
+	if(!read_delegate_) return;
+
+	const int cycles_to_forward = write_cycles_since_delegate_call_;
+	write_cycles_since_delegate_call_ = 0;
+	if(level && read_delegate_phase_ == ReadDelegatePhase::WaitingForZero) return;
+
+	// Deal with a transition out of waiting-for-zero mode by seeding time left
+	// in bit at half a bit.
+	if(read_delegate_phase_ == ReadDelegatePhase::WaitingForZero) {
+		time_left_in_bit_ = read_delegate_bit_length_;
+		time_left_in_bit_.clock_rate <<= 1;
+		read_delegate_phase_ = ReadDelegatePhase::Serialising;
+	}
+
+	// Forward as many bits as occur.
+	Storage::Time time_left(cycles_to_forward, int(clock_rate_.as_integral()));
+	const int bit = level ? 1 : 0;
+	int bits = 0;
+	while(time_left >= time_left_in_bit_) {
+		++bits;
+		if(!read_delegate_->serial_line_did_produce_bit(this, bit)) {
+			read_delegate_phase_ = ReadDelegatePhase::WaitingForZero;
+			if(bit) return;
+		}
+
+		time_left -= time_left_in_bit_;
+		time_left_in_bit_ = read_delegate_bit_length_;
+	}
+	time_left_in_bit_ -= time_left;
+}
+
+Cycles::IntType Line::minimum_write_cycles_for_read_delegate_bit() {
+	if(!read_delegate_) return 0;
+	return 1 + (read_delegate_bit_length_ * static_cast<unsigned int>(clock_rate_.as_integral())).get<int>();
+}

Components/Serial/Line.hpp

@@ -0,0 +1,112 @@
+//
+//  SerialPort.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 12/10/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef SerialPort_hpp
+#define SerialPort_hpp
+
+#include <vector>
+#include "../../Storage/Storage.hpp"
+#include "../../ClockReceiver/ClockReceiver.hpp"
+#include "../../ClockReceiver/ForceInline.hpp"
+
+namespace Serial {
+
+/*!
+	@c Line connects a single reader and a single writer, allowing timestamped events to be
+	published and consumed, potentially with a clock conversion in between. It allows line
+	levels to be written and read in larger collections.
+
+	It is assumed that the owner of the reader and writer will ensure that the reader will never
+	get ahead of the writer. If the writer posts events behind the reader they will simply be
+	given instanteous effect.
+*/
+class Line {
+	public:
+		void set_writer_clock_rate(HalfCycles clock_rate);
+
+		/// Advances the read position by @c cycles relative to the writer's
+		/// clock rate.
+		void advance_writer(HalfCycles cycles);
+
+		/// Sets the line to @c level.
+		void write(bool level);
+
+		/// Enqueues @c count level changes, the first occurring immediately
+		/// after the final event currently posted and each subsequent event
+		/// occurring @c cycles after the previous. An additional gap of @c cycles
+		/// is scheduled after the final output. The levels to output are
+		/// taken from @c levels which is read from lsb to msb. @c cycles is
+		/// relative to the writer's clock rate.
+		void write(HalfCycles cycles, int count, int levels);
+
+		/// @returns the number of cycles until currently enqueued write data is exhausted.
+		forceinline HalfCycles write_data_time_remaining() const {
+			return HalfCycles(remaining_delays_);
+		}
+
+		/// @returns the number of cycles left until it is guaranteed that a passive reader
+		/// has received all currently-enqueued bits.
+		forceinline HalfCycles transmission_data_time_remaining() const {
+			return HalfCycles(remaining_delays_ + transmission_extra_);
+		}
+
+		/// Eliminates all future write states, leaving the output at whatever it is now.
+		void reset_writing();
+
+		/// @returns The instantaneous level of this line.
+		bool read();
+
+		struct ReadDelegate {
+			virtual bool serial_line_did_produce_bit(Line *line, int bit) = 0;
+		};
+		/*!
+			Sets a read delegate, which will receive samples of the output level every
+			@c bit_lengths of a second apart subject to a state machine:
+
+				* initially no bits will be delivered;
+				* when a zero level is first detected, the line will wait half a bit's length, then start
+				sampling at single-bit intervals, passing each bit to the delegate while it returns @c true;
+				* as soon as the delegate returns @c false, the line will return to the initial state.
+		*/
+		void set_read_delegate(ReadDelegate *delegate, Storage::Time bit_length);
+
+	private:
+		struct Event {
+			enum Type {
+				Delay, SetHigh, SetLow
+			} type;
+			int delay;
+		};
+		std::vector<Event> events_;
+		HalfCycles::IntType remaining_delays_ = 0;
+		HalfCycles::IntType transmission_extra_ = 0;
+		bool level_ = true;
+		HalfCycles clock_rate_ = 0;
+
+		ReadDelegate *read_delegate_ = nullptr;
+		Storage::Time read_delegate_bit_length_, time_left_in_bit_;
+		int write_cycles_since_delegate_call_ = 0;
+		enum class ReadDelegatePhase {
+			WaitingForZero,
+			Serialising
+		} read_delegate_phase_ = ReadDelegatePhase::WaitingForZero;
+
+		void update_delegate(bool level);
+		HalfCycles::IntType minimum_write_cycles_for_read_delegate_bit();
+};
+
+/*!
+	Defines an RS-232-esque srial port.
+*/
+class Port {
+	public:
+};
+
+}
+
+#endif /* SerialPort_hpp */

Concurrency/AsyncTaskQueue.cpp

@@ -18,7 +18,7 @@ AsyncTaskQueue::AsyncTaskQueue()
 #ifdef __APPLE__
 	serial_dispatch_queue_ = dispatch_queue_create("com.thomasharte.clocksignal.asyntaskqueue", DISPATCH_QUEUE_SERIAL);
 #else
-	thread_.reset(new std::thread([this]() {
+	thread_ = std::make_unique<std::thread>([this]() {
 		while(!should_destruct_) {
 			std::function<void(void)> next_function;
 
@@ -39,7 +39,7 @@ AsyncTaskQueue::AsyncTaskQueue()
 				processing_condition_.wait(lock);
 			}
 		}
-	}));
+	});
 #endif
 }
 
@@ -70,8 +70,8 @@ void AsyncTaskQueue::flush() {
 #ifdef __APPLE__
 	dispatch_sync(serial_dispatch_queue_, ^{});
 #else
-	std::shared_ptr<std::mutex> flush_mutex(new std::mutex);
-	std::shared_ptr<std::condition_variable> flush_condition(new std::condition_variable);
+	auto flush_mutex = std::make_shared<std::mutex>();
+	auto flush_condition = std::make_shared<std::condition_variable>();
 	std::unique_lock<std::mutex> lock(*flush_mutex);
 	enqueue([=] () {
 		std::unique_lock<std::mutex> inner_lock(*flush_mutex);
@@ -88,7 +88,7 @@ DeferringAsyncTaskQueue::~DeferringAsyncTaskQueue() {
 
 void DeferringAsyncTaskQueue::defer(std::function<void(void)> function) {
 	if(!deferred_tasks_) {
-		deferred_tasks_.reset(new std::list<std::function<void(void)>>);
+		deferred_tasks_ = std::make_shared<std::list<std::function<void(void)>>>();
 	}
 	deferred_tasks_->push_back(function);
 }

Concurrency/BestEffortUpdater.cpp

@@ -12,59 +12,89 @@
 
 using namespace Concurrency;
 
-BestEffortUpdater::BestEffortUpdater() {
-	// ATOMIC_FLAG_INIT isn't necessarily safe to use, so establish default state by other means.
-	update_is_ongoing_.clear();
-}
+BestEffortUpdater::BestEffortUpdater() :
+	update_thread_([this]() {
+		this->update_loop();
+	}) {}
 
 BestEffortUpdater::~BestEffortUpdater() {
-	// Don't allow further deconstruction until the task queue is stopped.
+	// Sever the delegate now, as soon as possible, then wait for any
+	// pending tasks to finish.
+	set_delegate(nullptr);
 	flush();
+
+	// Wind up the update thread.
+	should_quit_ = true;
+	update();
+	update_thread_.join();
 }
 
-void BestEffortUpdater::update() {
-	// Perform an update only if one is not currently ongoing.
-	if(!update_is_ongoing_.test_and_set()) {
-		async_task_queue_.enqueue([this]() {
-			// Get time now using the highest-resolution clock provided by the implementation, and determine
-			// the duration since the last time this section was entered.
-			const std::chrono::time_point<std::chrono::high_resolution_clock> now = std::chrono::high_resolution_clock::now();
-			const auto elapsed = now - previous_time_point_;
-			previous_time_point_ = now;
+void BestEffortUpdater::update(int flags) {
+	// Bump the requested target time and set the update requested flag.
+	{
+		std::lock_guard<decltype(update_mutex_)> lock(update_mutex_);
+		has_skipped_ = update_requested_;
+		update_requested_ = true;
+		flags_ |= flags;
+		target_time_ = std::chrono::high_resolution_clock::now().time_since_epoch().count();
+	}
+	update_condition_.notify_one();
+}
 
-			if(has_previous_time_point_) {
-				// If the duration is valid, convert it to integer cycles, maintaining a rolling error and call the delegate
-				// if there is one. Proceed only if the number of cycles is positive, and cap it to the per-second maximum as
-				// it's possible this is an adjustable clock so be ready to swallow unexpected adjustments.
-				const int64_t integer_duration = std::chrono::duration_cast<std::chrono::nanoseconds>(elapsed).count();
-				if(integer_duration > 0) {
-					if(delegate_) {
-						const double duration = static_cast<double>(integer_duration) / 1e9;
-						delegate_->update(this, duration, has_skipped_);
-					}
-					has_skipped_ = false;
-				}
-			} else {
-				has_previous_time_point_ = true;
-			}
+void BestEffortUpdater::update_loop() {
+ 	while(true) {
+		std::unique_lock<decltype(update_mutex_)> lock(update_mutex_);
+		is_updating_ = false;
 
-			// Allow furthers updates to occur.
-			update_is_ongoing_.clear();
-		});
-	} else {
-		async_task_queue_.enqueue([this]() {
-			has_skipped_ = true;
+		// Wait to be signalled.
+		update_condition_.wait(lock, [this]() -> bool {
+			return update_requested_;
 		});
+
+		// Possibly this signalling really means 'quit'.
+		if(should_quit_) return;
+
+		// Note update started, crib the target time.
+		auto target_time = target_time_;
+		update_requested_ = false;
+
+		// If this was actually the first update request, silently swallow it.
+		if(!has_previous_time_point_) {
+			has_previous_time_point_ = true;
+			previous_time_point_ = target_time;
+			continue;
+		}
+
+		// Release the lock on requesting new updates.
+		is_updating_ = true;
+		const int flags = flags_;
+		flags_ = 0;
+		lock.unlock();
+
+		// Invoke the delegate, if supplied, in order to run.
+		const int64_t integer_duration = std::max(target_time - previous_time_point_, int64_t(0));
+		const auto delegate = delegate_.load();
+		if(delegate) {
+			// Cap running at 1/5th of a second, to avoid doing a huge amount of work after any
+			// brief system interruption.
+			const double duration = std::min(double(integer_duration) / 1e9, 0.2);
+			const double elapsed_duration = delegate->update(this, duration, has_skipped_, flags);
+
+			previous_time_point_ += int64_t(elapsed_duration * 1e9);
+			has_skipped_ = false;
+		}
 	}
 }
 
 void BestEffortUpdater::flush() {
-	async_task_queue_.flush();
+	// Spin lock; this is allowed to be slow.
+	while(true) {
+		std::lock_guard<decltype(update_mutex_)> lock(update_mutex_);
+		if(!is_updating_) return;
+	}
 }
 
 void BestEffortUpdater::set_delegate(Delegate *const delegate) {
-	async_task_queue_.enqueue([this, delegate]() {
-		delegate_ = delegate;
-	});
+	delegate_.store(delegate);
 }
 

Concurrency/BestEffortUpdater.hpp

@@ -11,8 +11,10 @@
 
 #include <atomic>
 #include <chrono>
+#include <condition_variable>
+#include <mutex>
+#include <thread>
 
-#include "AsyncTaskQueue.hpp"
 #include "../ClockReceiver/TimeTypes.hpp"
 
 namespace Concurrency {
@@ -31,7 +33,13 @@ class BestEffortUpdater {
 
 		/// A delegate receives timing cues.
 		struct Delegate {
-			virtual void update(BestEffortUpdater *updater, Time::Seconds duration, bool did_skip_previous_update) = 0;
+			/*!
+				Instructs the delegate to run for at least @c duration, providing hints as to whether multiple updates were requested before the previous had completed
+				(as @c did_skip_previous_update) and providing the union of any flags supplied to @c update.
+
+				@returns The amount of time actually run for.
+			*/
+			virtual Time::Seconds update(BestEffortUpdater *updater, Time::Seconds duration, bool did_skip_previous_update, int flags) = 0;
 		};
 
 		/// Sets the current delegate.
@@ -41,20 +49,32 @@ class BestEffortUpdater {
 			If the delegate is not currently in the process of an `update` call, calls it now to catch up to the current time.
 			The call is asynchronous; this method will return immediately.
 		*/
-		void update();
+		void update(int flags = 0);
 
-		/// Blocks until any ongoing update is complete.
+		/// Blocks until any ongoing update is complete; may spin.
 		void flush();
 
 	private:
-		std::atomic_flag update_is_ongoing_;
-		AsyncTaskQueue async_task_queue_;
+		std::atomic<bool> should_quit_;
+		std::atomic<bool> is_updating_;
 
-		std::chrono::time_point<std::chrono::high_resolution_clock> previous_time_point_;
+		int64_t target_time_;
+		int flags_ = 0;
+		bool update_requested_;
+		std::mutex update_mutex_;
+		std::condition_variable update_condition_;
+
+		decltype(target_time_) previous_time_point_;
 		bool has_previous_time_point_ = false;
-		bool has_skipped_ = false;
+		std::atomic<bool> has_skipped_ = false;
 
-		Delegate *delegate_ = nullptr;
+		std::atomic<Delegate *>delegate_ = nullptr;
+
+		void update_loop();
+
+		// This is deliberately at the bottom, to ensure it constructs after the various
+		// mutexs, conditions, etc, that it'll depend upon.
+		std::thread update_thread_;
 };
 
 }

Configurable/Configurable.cpp

@@ -19,7 +19,7 @@ ListSelection *ListSelection::list_selection() {
 }
 
 BooleanSelection *ListSelection::boolean_selection() {
-	return new BooleanSelection(value != "no" && value != "n");
+	return new BooleanSelection(value != "no" && value != "n" && value != "false" && value != "f");
 }
 
 BooleanSelection *BooleanSelection::boolean_selection() {

Configurable/StandardOptions.cpp

@@ -14,16 +14,16 @@ namespace {
 	Appends a Boolean selection of @c selection for option @c name to @c selection_set.
 */
 void append_bool(Configurable::SelectionSet &selection_set, const std::string &name, bool selection) {
-	selection_set[name] = std::unique_ptr<Configurable::Selection>(new Configurable::BooleanSelection(selection));
+	selection_set[name] = std::make_unique<Configurable::BooleanSelection>(selection);
 }
 
 /*!
 	Enquires for a Boolean selection for option @c name from @c selections_by_option, storing it to @c result if found.
 */
 bool get_bool(const Configurable::SelectionSet &selections_by_option, const std::string &name, bool &result) {
-	auto quickload = Configurable::selection<Configurable::BooleanSelection>(selections_by_option, "quickload");
-	if(!quickload) return false;
-	result = quickload->value;
+	auto selection = Configurable::selection<Configurable::BooleanSelection>(selections_by_option, name);
+	if(!selection) return false;
+	result = selection->value;
 	return true;
 }
 
@@ -33,14 +33,16 @@ bool get_bool(const Configurable::SelectionSet &selections_by_option, const std:
 std::vector<std::unique_ptr<Configurable::Option>> Configurable::standard_options(Configurable::StandardOptions mask) {
 	std::vector<std::unique_ptr<Configurable::Option>> options;
 	if(mask & QuickLoadTape)				options.emplace_back(new Configurable::BooleanOption("Load Tapes Quickly", "quickload"));
-	if(mask & (DisplayRGB | DisplayComposite | DisplaySVideo)) {
+	if(mask & (DisplayRGB | DisplayCompositeColour | DisplayCompositeMonochrome | DisplaySVideo)) {
 		std::vector<std::string> display_options;
-		if(mask & DisplayComposite)	display_options.emplace_back("composite");
-		if(mask & DisplaySVideo) 	display_options.emplace_back("svideo");
-		if(mask & DisplayRGB) 		display_options.emplace_back("rgb");
+		if(mask & DisplayCompositeColour)		display_options.emplace_back("composite");
+		if(mask & DisplayCompositeMonochrome)	display_options.emplace_back("composite-mono");
+		if(mask & DisplaySVideo)				display_options.emplace_back("svideo");
+		if(mask & DisplayRGB)					display_options.emplace_back("rgb");
 		options.emplace_back(new Configurable::ListOption("Display", "display", display_options));
 	}
 	if(mask & AutomaticTapeMotorControl)	options.emplace_back(new Configurable::BooleanOption("Automatic Tape Motor Control", "autotapemotor"));
+	if(mask & QuickBoot)					options.emplace_back(new Configurable::BooleanOption("Boot Quickly", "quickboot"));
 	return options;
 }
 
@@ -57,11 +59,16 @@ void Configurable::append_display_selection(Configurable::SelectionSet &selectio
 	std::string string_selection;
 	switch(selection) {
 		default:
-		case Display::RGB:			string_selection = "rgb";		break;
-		case Display::SVideo:		string_selection = "svideo";	break;
-		case Display::Composite:	string_selection = "composite";	break;
+		case Display::RGB:					string_selection = "rgb";				break;
+		case Display::SVideo:				string_selection = "svideo";			break;
+		case Display::CompositeMonochrome:	string_selection = "composite-mono";	break;
+		case Display::CompositeColour:		string_selection = "composite";			break;
 	}
-	selection_set["display"] = std::unique_ptr<Configurable::Selection>(new Configurable::ListSelection(string_selection));
+	selection_set["display"] = std::make_unique<Configurable::ListSelection>(string_selection);
+}
+
+void Configurable::append_quick_boot_selection(Configurable::SelectionSet &selection_set, bool selection) {
+	append_bool(selection_set, "quickboot", selection);
 }
 
 // MARK: - Selection parsers
@@ -85,9 +92,17 @@ bool Configurable::get_display(const Configurable::SelectionSet &selections_by_o
 			return true;
 		}
 		if(display->value == "composite") {
-			result = Configurable::Display::Composite;
+			result = Configurable::Display::CompositeColour;
+			return true;
+		}
+		if(display->value == "composite-mono") {
+			result = Configurable::Display::CompositeMonochrome;
 			return true;
 		}
 	}
 	return false;
 }
+
+bool Configurable::get_quick_boot(const Configurable::SelectionSet &selections_by_option, bool &result) {
+	return get_bool(selections_by_option, "quickboot", result);
+}