Thomas Harte
e7299c16f6
Merge branch 'master' into SeparateFetchClock
2023-08-01 14:48:21 -04:00
Thomas Harte
cdb86022a6
Merge pull request #1148 from TomHarte/NoEmulationStack
...
Use full 16-bit stack pointer for all 'new' instructions.
2023-07-31 20:41:10 -04:00
Thomas Harte
2262725010
Reveal 16-bit stack pointer when asked, regardless of mode.
2023-07-31 17:08:02 -04:00
Thomas Harte
e61a4eb5a9
Regularise PHD and PLD.
2023-07-30 16:36:29 -04:00
Thomas Harte
acd7f9f4cd
Fix stack usage of JSL.
2023-07-30 16:34:42 -04:00
Thomas Harte
9f1a657cc4
Fix stack usage of PEA.
2023-07-30 16:33:44 -04:00
Thomas Harte
e52d1866ab
Fix PEI stack usage.
2023-07-30 16:32:56 -04:00
Thomas Harte
a02b8222fa
Fix stack usage of PER.
2023-07-30 16:29:56 -04:00
Thomas Harte
3762ee1a63
Fix stack usage of PHD.
2023-07-30 16:29:15 -04:00
Thomas Harte
3ec61e8770
Fix stack usage of RTL.
2023-07-30 16:27:13 -04:00
Thomas Harte
2f7dd0b01a
Correct stack behaviour of PLD.
2023-07-30 16:26:29 -04:00
Thomas Harte
3a02c22072
Provide an always-16bit-address route to the stack.
2023-07-30 16:25:51 -04:00
Thomas Harte
6ae967de51
Merge pull request #1147 from TomHarte/ErrantDBR
...
Remove DBR reset upon COP/BRK/IRQ/NMI; fix (d, x) addressing.
2023-07-30 16:20:34 -04:00
Thomas Harte
5d45aa4a6a
Fix seed per test.
2023-07-28 13:58:01 -04:00
Thomas Harte
0f1468adfd
Correct wrapping behaviour for (d, x).
2023-07-28 13:39:21 -04:00
Thomas Harte
e9347168e6
Don't alter the data bank upon BRK, COP, IRQ, etc.
2023-07-28 10:53:02 -04:00
Thomas Harte
e2dcb0a8e2
Begin commutation of interrupts.
2023-07-28 10:34:15 -04:00
Thomas Harte
1797bab28f
Explain logic.
2023-07-23 14:26:02 -04:00
Thomas Harte
7f48cd6d9d
Fix fetch offset. Breaking interrupt placement.
2023-07-21 15:48:52 -04:00
Thomas Harte
8662f06ae5
Add documentation, to persuade myself.
2023-07-16 22:43:50 -04:00
Thomas Harte
3b67d48ebf
With origin being its own thing, simplify.
2023-07-16 21:23:49 -04:00
Thomas Harte
2ab16867cb
Require explicit origin.
2023-07-16 15:12:52 -04:00
Thomas Harte
3a93b8059a
Make faulty attempt to introduce skew into fetching.
2023-07-10 22:24:13 -04:00
Thomas Harte
3e09afbb59
Remove errant square bracket.
2023-06-21 11:57:09 -04:00
Thomas Harte
9703fed9f8
Explain constant.
2023-06-18 14:56:44 -04:00
Thomas Harte
f30637a773
Merge pull request #1144 from TomHarte/Base144
...
Enhance mechanisms for display-style dispatch.
2023-06-15 21:42:59 -04:00
Thomas Harte
1d8bc41724
Shift back to original name.
2023-06-13 15:25:51 -04:00
Thomas Harte
d36a88dd11
Collect up different dispatches.
2023-06-13 15:22:53 -04:00
Thomas Harte
de5ee8f0d0
Mildly extend test.
2023-06-13 13:26:39 -04:00
Thomas Harte
6261ac24b4
Reformat SubrangeDispatcher; test.
2023-06-13 12:46:21 -04:00
Thomas Harte
b00eac4a34
Get to building.
2023-06-12 23:16:45 -04:00
Thomas Harte
6e35d84a96
Merge branch 'Base144' of github.com:TomHarte/CLK into Base144
2023-06-12 17:39:16 -04:00
Thomas Harte
d028555361
Get code up on feet, fix most obvious transgressions.
2023-06-12 16:09:02 -04:00
Thomas Harte
1aa953dd4d
Consolidate RangeDispatcher under Dispatcher's umbrella.
2023-06-12 15:52:10 -04:00
Thomas Harte
77c67ab59d
Build max
into the sequencer.
2023-06-12 15:35:33 -04:00
Thomas Harte
05d2e78f80
Conversion can be a separate step.
2023-06-12 15:34:44 -04:00
Thomas Harte
837d8d29ca
Merge branch 'master' into Base144
2023-06-10 16:00:57 -04:00
Thomas Harte
8a831b1409
Import sketch for a potential range dispatcher.
2023-06-10 15:58:30 -04:00
Thomas Harte
c0547f6e14
Tidy up; forward construction arguments.
2023-06-10 15:58:13 -04:00
Thomas Harte
81e475f052
Merge pull request #1142 from aperezdc/gcc13-cstdint
...
Add missing <cstdint> includes for GCC 13
2023-06-01 17:43:18 +01:00
Thomas Harte
4e12d5a70a
Attempt to make switch sets even more obviously collapsible.
2023-05-30 16:43:22 +01:00
Thomas Harte
c630f86f33
Attempt to generalise out from the 9918's current sense of dispatching.
2023-05-29 22:56:36 +01:00
Adrian Perez de Castro
1de2631877
Add missing <cstdint> includes for GCC 13
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Sprinkle includes of the <cstdint> header as needed to make the
build succeed with GCC 13, this fixes both with SDL and Qt builds.
2023-05-25 23:06:13 +03:00
Thomas Harte
dd3fc43bd3
Merge pull request #1141 from TomHarte/ConvertFromGrauw
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Clean up further internal magic constants.
2023-05-19 19:52:40 -04:00
Thomas Harte
40d5bd4e58
Switch to purposive name.
2023-05-19 14:22:22 -04:00
Thomas Harte
c75efb7dac
Also allow for a potential Grauw conversion in Yamaha land.
2023-05-19 13:43:28 -04:00
Thomas Harte
d117a44069
Allow for potential Grauw offset in TMS and SMS.
2023-05-19 11:46:49 -04:00
Thomas Harte
dc425a03d3
Partially resolve.
2023-05-18 16:55:17 -04:00
Thomas Harte
ce8bd011d7
Add commentary, and TODOs.
2023-05-18 16:50:46 -04:00
Thomas Harte
c76048bff9
Formalise the idea of Grauw as a separate clock.
2023-05-18 16:37:48 -04:00
Thomas Harte
4cb7abe13d
Update old comment.
2023-05-18 16:28:05 -04:00
Thomas Harte
c445295411
Merge pull request #1140 from TomHarte/YamahaLineInterrupts
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Move Yamaha interrupts to end of line; clean source.
2023-05-16 16:46:56 -04:00
Thomas Harte
5c51bae605
Remove unused variable.
2023-05-16 16:46:36 -04:00
Thomas Harte
8578dfbf22
Eliminate various other errant spaces.
2023-05-16 16:40:09 -04:00
Thomas Harte
f821b60430
Remove stray space.
2023-05-16 16:16:10 -04:00
Thomas Harte
8ca0d9e13a
Add a hook for when I think mode latching should occur.
2023-05-16 16:14:37 -04:00
Thomas Harte
3014c957e7
Relocate Yamaha line interrupt.
2023-05-16 13:01:23 -04:00
Thomas Harte
747dc09a80
Merge pull request #1139 from TomHarte/OtherProjects
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Clean up SDL and Qt projects, Qt build warnings.
2023-05-15 10:18:16 -04:00
Thomas Harte
7f8f1d7e61
Avoid BASIC 2.1 requirement when running 1.1.
2023-05-15 10:17:27 -04:00
Thomas Harte
a1a7c0e253
Apply maybe_unused judiciously.
2023-05-15 10:17:04 -04:00
Thomas Harte
9342c6005f
Remove dead 68000 references.
2023-05-15 10:09:39 -04:00
Thomas Harte
14ac4da813
Accept version number.
2023-05-15 10:01:38 -04:00
Thomas Harte
b0e3bd85d6
Merge pull request #1138 from TomHarte/QtMSXUI
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Introduce Qt options for MSX model, MSX-MUSIC.
2023-05-15 09:54:25 -04:00
Thomas Harte
9b6be2571a
Introduce Qt options for MSX model, MSX-MUSIC.
2023-05-15 09:50:22 -04:00
Thomas Harte
4ede538d36
Merge pull request #1137 from TomHarte/MX2
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Add .MX2 as an MSX synonym of .ROM
2023-05-14 23:46:37 -04:00
Thomas Harte
8bf3d85e36
Add .MX2 as an MSX synonym of .ROM
2023-05-14 23:42:08 -04:00
Thomas Harte
ec9abbe6a7
Merge pull request #1136 from TomHarte/MSX-MUSIC
...
Add MSX-MUSIC (/FM-PAC) emulation.
2023-05-13 22:34:31 -04:00
Thomas Harte
22ac13d3f2
Set proper number of volumes.
2023-05-13 22:29:09 -04:00
Thomas Harte
413ab42b16
Add MSX-MUSIC option for macOS.
2023-05-13 22:25:50 -04:00
Thomas Harte
876fc6d1e0
Eliminate redundant line break.
2023-05-13 22:18:40 -04:00
Thomas Harte
b768e438b2
Enable MSX-MUSIC by default.
2023-05-13 22:17:09 -04:00
Thomas Harte
e1d671daf7
Avoid paying for an OPLL if not connected.
2023-05-13 22:16:42 -04:00
Thomas Harte
4989701de9
Install MSX-MUSIC ROM.
2023-05-12 23:50:43 -04:00
Thomas Harte
fed97b8d26
Add MSX-MUSIC entry.
2023-05-12 23:33:28 -04:00
Thomas Harte
e7888497b7
Add an OPLL.
2023-05-12 23:30:03 -04:00
Thomas Harte
0b53c73da8
Add additional consts.
2023-05-12 22:13:55 -04:00
Thomas Harte
a6ebfe2ce2
Add has_msx_music flag.
2023-05-12 22:09:15 -04:00
Thomas Harte
b89076cb72
Merge pull request #1135 from TomHarte/9918Cleanup
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Adds yet more clenliness
2023-05-12 21:32:33 -04:00
Thomas Harte
50343dec43
Eliminate all whitespace-only lines.
2023-05-12 14:16:39 -04:00
Thomas Harte
28c79b2885
Eliminate redundant [space][tab] pairs.
2023-05-12 14:14:45 -04:00
Thomas Harte
60bec3d4c0
Eliminate trailing whitespace, fix tabs.
2023-05-12 14:03:38 -04:00
Thomas Harte
56de9c418f
Improve comments.
2023-05-12 13:59:52 -04:00
Thomas Harte
5bcb5fb832
Also sever command-engine state.
2023-05-12 13:57:50 -04:00
Thomas Harte
abeb361441
Gift all generators to YamahaFetcher.
2023-05-12 13:54:07 -04:00
Thomas Harte
f9cc2013a8
Start to cleave off Yamaha fetch tables.
2023-05-12 13:49:53 -04:00
Thomas Harte
e7c40eead9
Have Fetch and Draw be overt about namespaces.
2023-05-12 13:46:35 -04:00
Thomas Harte
c29d80006e
Start to organise.
2023-05-12 13:33:02 -04:00
Thomas Harte
596661bfbe
Remove errant newline.
2023-05-12 13:25:11 -04:00
Thomas Harte
7e319374b6
Consolidate StandardTiming into LineLayout.
2023-05-11 23:49:12 -04:00
Thomas Harte
7f5d129b13
Merge pull request #1134 from TomHarte/WorkingTests
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Clean up various long-dangling issues.
2023-05-11 08:21:53 -05:00
Thomas Harte
f6acee18cc
Eliminate type-in-function-name from 6502-world.
2023-05-10 18:53:38 -05:00
Thomas Harte
3af30b1fec
Update documentation.
2023-05-10 18:46:46 -05:00
Thomas Harte
a8cc74f9fe
Further eliminate naming.
2023-05-10 18:46:21 -05:00
Thomas Harte
10cd2a36cf
Avoid type-in-function-name, Z80 edition.
2023-05-10 18:42:19 -05:00
Thomas Harte
ea50d5bda7
Eliminate dead bit reverser.
2023-05-10 17:14:39 -05:00
Thomas Harte
809cd7bca9
Remove the 68000's Mk2 suffix.
2023-05-10 17:13:01 -05:00
Thomas Harte
e56db3c4e5
Eliminate the old 68000 implementation.
2023-05-10 17:06:27 -05:00
Thomas Harte
2b56b7be0d
Simplify namespace syntax.
2023-05-10 16:02:18 -05:00
Thomas Harte
25a245e35c
Flailingly switch things until tests run.
2023-05-10 15:17:00 -05:00
Thomas Harte
882384b1f3
Disambiguate Storage.hpp.
2023-05-10 15:06:39 -05:00
Thomas Harte
5cc19f436f
Permit command-line parallel builds.
2023-05-10 15:02:07 -05:00
Thomas Harte
fd0eaa5788
Decline signing of all but release builds.
2023-05-10 15:01:02 -05:00
Thomas Harte
992a47c196
Add fallthrough annotations to Duff-esque loops.
2023-05-10 09:38:42 -05:00
Thomas Harte
8540e7a953
Add missing #include.
2023-05-10 09:37:21 -05:00
Thomas Harte
6b19bfeab2
No .cpp files remain in Components/9918
2023-05-09 17:40:14 -05:00
Thomas Harte
066e42145e
Merge branch 'master' of github.com:TomHarte/CLK
2023-05-08 21:14:14 -04:00
Thomas Harte
efe1425e8e
Accept new version number.
2023-05-08 21:14:03 -04:00
Thomas Harte
55e0742232
Merge pull request #1132 from TomHarte/MSX2Screenshot
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Mention MSX 2, include screenshot.
2023-05-08 10:14:53 -04:00
Thomas Harte
abf92cd09e
Platform name is conventionally included.
2023-05-08 10:14:40 -04:00
Thomas Harte
73a214913a
Withdraw failed div experiment.
2023-05-08 10:13:47 -04:00
Thomas Harte
5453840d8c
Attempt to equalise column widths.
2023-05-08 10:12:35 -04:00
Thomas Harte
77078e2b7a
Fix Chromatrons reference.
2023-05-08 10:10:22 -04:00
Thomas Harte
3f1ae986cb
Cut down on borders.
2023-05-08 10:08:33 -04:00
Thomas Harte
d39d2a88f8
Futher resort.
2023-05-08 10:02:29 -04:00
Thomas Harte
6556865615
Shuffle screenshot order.
2023-05-08 10:00:40 -04:00
Thomas Harte
44779e68ee
Mention MSX 2, include screenshot.
2023-05-08 09:58:35 -04:00
Thomas Harte
54f5bae59e
Merge pull request #1131 from TomHarte/MSXLineInterrupts
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Restrict disabled MSX line interrupt signalling.
2023-05-08 09:55:52 -04:00
Thomas Harte
e94b9f695a
Move interrupt away from buggy position.
...
Since I don't know where it's supposed to go anyway.
2023-05-08 09:50:05 -04:00
Thomas Harte
3797968870
Expose line interrupt status only when enabled.
2023-05-08 09:45:54 -04:00
Thomas Harte
9c079a6c50
Merge pull request #1130 from TomHarte/ImplicitPosition
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Unify numbered and named slots.
2023-04-30 17:30:59 -04:00
Thomas Harte
561e2b774e
Unify numbered and named slots.
2023-04-30 17:24:14 -04:00
Thomas Harte
0cb4fec504
Merge pull request #1129 from TomHarte/FarewellCodecvt
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Eliminate use of deprecated codecvt.
2023-04-30 17:21:43 -04:00
Thomas Harte
ec81cdd388
Eliminate codecvt.
2023-04-30 17:17:40 -04:00
Thomas Harte
8f0dc9d9a2
Eliminate use of deprecated codecvt.
2023-04-30 16:55:55 -04:00
Thomas Harte
4ebc3344cb
Merge pull request #1128 from TomHarte/SMSFetch
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Fix base for Master System fetching.
2023-04-30 16:48:41 -04:00
Thomas Harte
6552d962ab
Fix base for Master System fetching.
2023-04-30 16:43:03 -04:00
Thomas Harte
5f151c07ea
Merge pull request #1127 from TomHarte/MapperReadback
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Permit MSX RAM mapper readback.
2023-04-29 23:54:35 -04:00
Thomas Harte
1f4d526ea5
Permit MSX RAM mapper readback.
2023-04-29 23:48:22 -04:00
Thomas Harte
19d03dd4fd
Merge pull request #1117 from TomHarte/MSX2
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Flesh out the MSX 2.
2023-04-27 10:00:16 -04:00
Thomas Harte
6c0feeedb4
Update Master System horizontal counter.
2023-04-26 22:49:46 -04:00
Thomas Harte
b5d9586362
Clean up some dangling timing changes.
2023-04-25 23:16:21 -04:00
Thomas Harte
8cd38094fc
Merge pull request #1126 from TomHarte/NewLineLayout
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Definitively switch 9918 to counting cycle 0 as start-of-sync.
2023-04-25 11:26:28 -04:00
Thomas Harte
e49e98d309
Support horizontal offsets.
2023-04-24 22:43:11 -04:00
Thomas Harte
1b4df01a28
Fix missing right blank.
2023-04-24 22:23:09 -04:00
Thomas Harte
dbddcd109c
Add mention of text mode.
2023-04-23 22:38:42 -04:00
Thomas Harte
efa7d659bc
Subsume right erase.
2023-04-23 22:21:22 -04:00
Thomas Harte
5daec050dd
Adopt proper pixel-content placement.
2023-04-23 22:18:36 -04:00
Thomas Harte
f5c8eba843
Reduce duplication.
2023-04-23 22:02:41 -04:00
Thomas Harte
e5b0e666cc
Realign fetching.
2023-04-23 21:16:04 -04:00
Thomas Harte
96896f838c
Adjust layout inner loop.
2023-04-23 12:17:55 -04:00
Thomas Harte
f22aa6eb36
Simplify all namespace usages.:wq
2023-04-23 12:08:07 -04:00
Thomas Harte
6d092e0633
Restore missing semicolon.
2023-04-23 12:06:07 -04:00
Thomas Harte
6651a9c323
Use established test.
2023-04-23 12:01:33 -04:00
Thomas Harte
d40bc58e8b
Merge branch 'master' into MSX2
2023-04-23 11:58:34 -04:00
Thomas Harte
4b53082774
Merge pull request #1125 from TomHarte/CheckoutV3
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Update checkout action.
2023-04-23 11:58:08 -04:00
Thomas Harte
8a5b7e9f47
Update checkout action.
2023-04-23 11:38:04 -04:00
Thomas Harte
12bcc2dee7
Make reasonable guesses at colour burst placement.
2023-04-22 23:11:01 -04:00
Thomas Harte
d587d80616
Transcribe Grauw's line timings.
2023-04-22 22:58:23 -04:00
Thomas Harte
0070a271f8
Merge branch 'master' into MSX2
2023-04-16 21:36:14 -04:00
Thomas Harte
d641a9c2b1
Merge pull request #1124 from TomHarte/65816Branches
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65816: Fix test (and commentary) for shortened emulated branches.
2023-04-15 23:39:12 -04:00
Thomas Harte
ed2d4ebb0c
Fix test (and commentary) for shortened emulated branches.
2023-04-15 23:30:30 -04:00
Thomas Harte
32597b4e95
Merge branch 'master' into MSX2
2023-04-14 23:26:19 -04:00
Thomas Harte
9f198f6392
Merge pull request #1123 from TomHarte/StackRelative65816
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65816: Fix perceived S in emulated stack-relative mode.
2023-04-14 23:26:00 -04:00
Thomas Harte
107cb18df4
Fix perceives S in emulated stack-relative mode.
2023-04-14 00:04:44 -04:00
Thomas Harte
e66c015b43
Eliminate regress
for now.
2023-04-13 23:30:52 -04:00
Thomas Harte
9d99cc6115
Fix external slot placement.
2023-04-12 22:35:01 -04:00
Thomas Harte
383770515e
Avoid null dereference.
2023-04-10 23:13:36 -04:00
Thomas Harte
024b7960cb
Overtly link line and sprite buffers.
2023-04-10 23:03:39 -04:00
Thomas Harte
e0a5d9f31c
Reorient sequencers around HSYNC.
2023-04-08 15:28:49 -04:00
Thomas Harte
224c79c492
Move state.
2023-04-06 00:05:19 -04:00
Thomas Harte
278e7ba9b0
Take ownership of test choice.
2023-04-05 23:33:42 -04:00
Thomas Harte
20c1c6fdcd
Add sanity check on sprite fetches versus draws.
2023-04-03 22:46:49 -04:00
Thomas Harte
514022204e
Attempt to avoid lingering sprite elements.
2023-04-02 22:45:02 -04:00
Thomas Harte
564ee1a5cb
Fix sprites on first line of display.
2023-03-30 23:45:19 -04:00
Thomas Harte
f3c2c0ffa9
Synchronise fetch and draw sprite buffer usage.
2023-03-30 19:11:00 -04:00
Thomas Harte
931d2373a4
Attempt to make outer loop sole owner of line/sprite buffer selection.
2023-03-30 00:20:03 -04:00
Thomas Harte
de3cd9c286
Simplify namespace declaration.
2023-03-25 23:22:34 -04:00
Thomas Harte
655638656f
Elide the two fills; fix address masking.
2023-03-21 20:05:34 -04:00
Thomas Harte
7d63a50f3e
Add MSX 2 to macOS UI.
2023-03-21 20:05:10 -04:00
Thomas Harte
2bf2abf4b2
Be more overt about masking.
2023-03-19 23:00:41 -04:00
Thomas Harte
235d54bb67
Attempt but retreat from proper treatment of width.
2023-03-18 23:13:06 -04:00
Thomas Harte
e66a92d6cb
Fill in and use some parts of mode description.
2023-03-18 23:07:33 -04:00
Thomas Harte
a6251f436a
Provide commands with [unpopulated] mode parameters.
2023-03-18 13:39:47 -04:00
Thomas Harte
6d49b2e66b
Merge branch 'master' into MSX2
2023-03-17 21:25:51 -04:00
Thomas Harte
363fd0f781
Add 6809 to Xcode project.
2023-03-17 21:25:31 -04:00
Thomas Harte
345e519e6a
Merge pull request #1122 from TomHarte/6809
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Add experimental 6809 opcode decoder.
2023-03-17 21:25:08 -04:00
Thomas Harte
315e0b4545
Add experimental 6809 opcode decoder.
...
Just a pleasant distraction, for now.
2023-03-17 21:20:35 -04:00
Thomas Harte
4a5b2fd9ba
Eliminate logged TODOs that I don't intend to action soon.
2023-03-16 22:00:47 -04:00
Thomas Harte
a5a36cb08e
Add missing status storage; capture mode 2 sprite collision locations.
2023-03-15 23:06:32 -04:00
Thomas Harte
aa4582956f
Add TODO.
2023-03-15 22:37:47 -04:00
Thomas Harte
c9543d0b36
Merge branch 'MSX2' of github.com:TomHarte/CLK into MSX2
2023-03-14 22:28:01 -04:00
Thomas Harte
d36c8df0c9
Eliminate redundant init
.
2023-03-14 22:27:46 -04:00
Thomas Harte
f26dee16bf
Update comment.
2023-03-13 23:21:19 -04:00
Thomas Harte
131784d007
Generalise PointSet to read or write.
2023-03-13 22:51:01 -04:00
Thomas Harte
e703fa9cf8
Fetch colours in TMS character mode.
2023-03-12 23:33:29 -04:00
Thomas Harte
201a7c17ae
Avoid VDP race condition.
2023-03-12 23:20:48 -04:00
Thomas Harte
e0125e0177
Add MSX 1 diversion.
2023-03-12 23:14:24 -04:00
Thomas Harte
cc04349618
Reestablish relationship between fetch and output.
2023-03-11 22:24:11 -05:00
Thomas Harte
d46f869276
Minor style improvement.
2023-03-10 21:14:52 -05:00
Thomas Harte
9836a108da
Avoid VDP access races.
2023-03-10 21:04:55 -05:00
Thomas Harte
da944fde92
Eliminate data-type assumption.
2023-03-10 21:04:35 -05:00
Thomas Harte
c9124f13cd
Add suggested brackets.
2023-03-09 22:25:09 -05:00
Thomas Harte
ca7d34ad04
Fix ambiguous using
.
2023-03-09 22:24:53 -05:00
Thomas Harte
2913368a06
Attempt YMMM.
2023-03-08 23:12:02 -05:00
Thomas Harte
82659e7924
Unify existing moves.
2023-03-08 22:36:06 -05:00
Thomas Harte
f3a84021ed
Merge branch 'MSX2' of github.com:TomHarte/CLK into MSX2
2023-03-08 18:28:17 -05:00
Thomas Harte
555d883227
Yamaha fetches don't require an outer switch.
2023-03-08 18:28:13 -05:00
Thomas Harte
020d9604c6
Better judge when to rotate addresses.
2023-03-08 18:27:59 -05:00
Thomas Harte
6845008fd4
Place end-of-frame interrupt appropriately.
2023-03-07 22:12:06 -05:00
Thomas Harte
cc7b209e1a
Adjust visible Y9938 area; clamp scrolled y; use proper mode 2 terminator.
2023-03-07 18:19:08 -05:00
Thomas Harte
e8404bdcc0
TODO is done, probably.
2023-03-06 22:57:53 -05:00
Thomas Harte
f8eb2199c2
Fix relative offset.
2023-03-06 22:49:21 -05:00
Thomas Harte
a13905acf9
Attempt to incorporate scroll offset into line interrupt.
2023-03-06 21:41:43 -05:00
Thomas Harte
5471979f8d
Eliminate stale TODOs.
2023-03-05 21:34:10 -05:00
Thomas Harte
5b8a5755f0
Use correct mode-7 sprite palette.
2023-03-05 21:29:04 -05:00
Thomas Harte
caaba836ba
Correct GR7 rasterisation and 6/7 collection.
2023-03-05 13:43:53 -05:00
Thomas Harte
8fc043247c
Fix column addressing in modes 6 and 7.
2023-03-04 21:39:00 -05:00
Thomas Harte
e58a488add
Rotate command-engine addresses in modes 6 and 7.
2023-03-03 23:06:52 -05:00
Thomas Harte
0ea1da10d6
Attempt to generalise moving from CPU.
2023-03-03 21:40:48 -05:00
Thomas Harte
3381e6b5aa
Switch to Duff's device.
2023-03-02 22:16:18 -05:00
Thomas Harte
4c1973adc8
Fill in missing rasterisers.
2023-03-01 23:19:33 -05:00
Thomas Harte
318cfab67d
Attempt ongoing state for vertical on/off.
2023-02-28 22:28:14 -05:00
Thomas Harte
1ef34b1f18
Clarify meaning of STOP.
2023-02-26 14:28:24 -05:00
Thomas Harte
12bd71cfe1
Allow that the next interrupt line might be in the next frame.
2023-02-26 14:23:38 -05:00
Thomas Harte
c7128f4206
Reduce logging.
2023-02-26 14:01:23 -05:00
Thomas Harte
95fd5a52ba
Use redirected palette in bitmap modes.
2023-02-26 13:59:17 -05:00
Thomas Harte
bfa167fcdf
Make attempt at the TP background-colour bit.
2023-02-26 13:42:59 -05:00
Thomas Harte
b948761f30
Detect mode 2 collisions, albeit without proper reporting.
2023-02-25 10:42:44 -06:00
Thomas Harte
dd65074bbf
Add named getters, resolving composition bug.
2023-02-25 10:32:47 -06:00
Thomas Harte
9debed25e8
Fix meaning of 'origin'.
2023-02-25 08:53:00 -06:00
Thomas Harte
1bdf9a50e6
Take a shot at Mode 2 sprite output.
2023-02-25 08:48:16 -06:00
Thomas Harte
2592dfd78f
Pile on the TODOs.
2023-02-21 22:33:47 -05:00
Thomas Harte
ef5d05db53
Scale down new-mode coordinates; add note to self.
2023-02-21 22:28:39 -05:00
Thomas Harte
6a2cda7074
Pull out and partially generalise sprite output.
...
This also provides the intended route to supporting Mode 2.
2023-02-21 22:00:00 -05:00
Thomas Harte
62d381065e
Change 9938 identification number.
2023-02-21 19:35:11 -05:00
Thomas Harte
091c1b0f45
Correct sprite attribute and colour table addresses.
2023-02-21 19:34:26 -05:00
Thomas Harte
a28b5bdeea
Only on the Sega are line interrupts disabled by a read of S#0.
2023-02-20 23:43:23 -05:00
Thomas Harte
2e45422b03
Make a further attempt at sprite colour.
2023-02-20 22:39:34 -05:00
Thomas Harte
3606f5befe
Add expansion RAM to command engine, as far as it goes.
2023-02-20 22:32:36 -05:00
Thomas Harte
44ac948bb2
Add expansion RAM, albeit not yet into the command engine.
2023-02-20 22:27:30 -05:00
Thomas Harte
4bac782121
One final (?) time with colour.
2023-02-19 22:15:59 -05:00
Thomas Harte
318109b7d5
Try again with colour.
2023-02-19 22:14:18 -05:00
Thomas Harte
6990ba9242
Fetch colour from before attribute table.
2023-02-19 22:10:22 -05:00
Thomas Harte
54be424159
Include sprite index in SpriteY event.
2023-02-19 22:04:38 -05:00
Thomas Harte
8d900cf636
Attempt a full collection of Mode 2 sprite properties.
2023-02-19 21:52:10 -05:00
Thomas Harte
6db939f48f
Create a dedicated sprite fetcher.
2023-02-19 21:37:24 -05:00
Thomas Harte
5eae11434a
Sprite mode 2: select sprites, fetch locations and names.
2023-02-18 22:56:05 -05:00
Thomas Harte
7aa8728b39
Reimagine G3 for sprite mode 2.
2023-02-18 21:50:12 -05:00
Thomas Harte
270c5dfe85
Eliminate data_block_
entirely.
2023-02-18 21:41:22 -05:00
Thomas Harte
d6e4f12fdc
Merge DataBlock and Pattern.
2023-02-18 21:34:09 -05:00
Thomas Harte
4e3e4806b9
Eliminate assert; events have overtaken this.
2023-02-17 23:01:42 -05:00
Thomas Harte
ebc596820e
Obtain the background graphics, at least, for G3.
2023-02-17 22:47:15 -05:00
Thomas Harte
b62e899039
Avoid need for shortcuts.
2023-02-17 22:34:52 -05:00
Thomas Harte
a123ef151c
Eliminate further magic ORs.
2023-02-17 22:31:21 -05:00
Thomas Harte
5b31db700b
Deduplicate 40-column text fetching.
2023-02-17 22:23:10 -05:00
Thomas Harte
8af0a2313c
Formally distinguish fetchers and sequencing.
2023-02-17 22:20:38 -05:00
Thomas Harte
88eaa4ff02
[Mostly] avoid magic address constants; avoid duplication of TMS fetching logic.
2023-02-17 21:59:39 -05:00
Thomas Harte
c140f370fe
Attempt to copy and paste my way to working type-1 sprites.
2023-02-16 22:46:19 -05:00
Thomas Harte
023da1970a
Label all character events with IDs.
2023-02-16 22:21:24 -05:00
Thomas Harte
211e145230
Make room for an ID field on Event.
2023-02-16 22:10:16 -05:00
Thomas Harte
bbccc5d6d6
Route other holdover TMS modes through the Yamaha logic.
2023-02-16 22:07:18 -05:00
Thomas Harte
dbfc9a14aa
Introduce SMS fetcher, eliminating all macros.
2023-02-16 22:01:20 -05:00
Thomas Harte
9630a1bc39
Use a fetcher for character modes.
2023-02-16 13:15:18 -05:00
Thomas Harte
3847c9c281
Add missing underscore.
2023-02-15 21:22:51 -05:00
Thomas Harte
3f2a5929a3
Consolidate text output and support blinking; add sprites-enabled flag.
2023-02-15 20:18:56 -05:00
Thomas Harte
9b71f42375
Collect colours.
2023-02-14 21:18:10 -05:00
Thomas Harte
9c43776392
Fix 80-column address generation.
2023-02-14 21:14:35 -05:00
Thomas Harte
35a0a1447e
Further clarify different usages of storage.
2023-02-14 20:23:17 -05:00
Thomas Harte
bf0ed2813c
Make faulty attempt at 80-column text.
2023-02-14 20:13:51 -05:00
Thomas Harte
1edf747f9f
Avoid flushes for video output changes.
2023-02-14 20:13:34 -05:00
Thomas Harte
f38cf91ea7
Add attempt to detect improper usage.
2023-02-14 20:13:16 -05:00
Thomas Harte
5c7367b262
Route Yamaha 40-column text mode appropriately.
2023-02-13 22:24:39 -05:00
Thomas Harte
c1457cc5e0
Attempt text mode data collection.
2023-02-13 22:20:47 -05:00
Thomas Harte
169d7a7418
Fix[/revert]: the fetch pointer should be _ahead_.
2023-02-13 21:10:14 -05:00
Thomas Harte
5143960970
Add notes to self on how to collect text.
2023-02-13 21:09:31 -05:00
Thomas Harte
40894964bc
Move VerticalState
to live with ScreenMode and FetchMode.
2023-02-13 09:54:29 -05:00
Thomas Harte
927e61484f
Map all events lists appropriately.
2023-02-12 23:02:51 -05:00
Thomas Harte
dce04e7219
Add a generator for character modes.
2023-02-12 22:54:08 -05:00
Thomas Harte
f5814b4c75
Add text-mode events list.
2023-02-12 22:45:11 -05:00
Thomas Harte
815a75d9b6
Extend generator to handle sprite collection.
2023-02-12 22:28:34 -05:00
Thomas Harte
4ad84e5047
Use generator for no-sprite events list.
2023-02-12 22:12:23 -05:00
Thomas Harte
8665dca7f0
Permit generator-based event-table generation.
2023-02-12 21:58:50 -05:00
Thomas Harte
41d57e03a6
Split out LineBuffer and Storage to make 9918Base more manageable.
2023-02-12 12:58:46 -05:00
Thomas Harte
914a9e0c84
Yamaha: don't touch address at all unless a RAM access.
2023-02-11 22:43:29 -05:00
Thomas Harte
8768ee1504
Merge branch 'MSX2' of github.com:TomHarte/CLK into MSX2
2023-02-11 22:40:03 -05:00
Thomas Harte
8e6c36bb15
Yamaha: don't part-modify address.
2023-02-11 10:35:42 -05:00
Thomas Harte
c6401f0444
Add TODO.
2023-02-07 22:28:18 -05:00
Thomas Harte
3c3efe3e22
Don't be so fussy.
2023-02-06 22:16:42 -05:00
Thomas Harte
7028bdd05d
Limit to 14 bits in old modes.
2023-02-06 22:16:31 -05:00
Thomas Harte
7cb51c021b
Observation: offset is needed only ephemerally.
2023-02-06 21:45:35 -05:00
Thomas Harte
a3df106f92
Reset write phase only upon traditional register accesses.
2023-02-06 20:32:24 -05:00
Thomas Harte
b538407386
Introduce separate state for palette entries.
2023-02-06 19:12:02 -05:00
Thomas Harte
c04d292c8e
Make this more obviously correct, albeit arbitrarily.
...
Comparing just a single bit would do.
2023-02-05 22:53:08 -05:00
Thomas Harte
f9c88fd598
Fix memory mask; mildly improve commentary.
2023-02-05 22:51:16 -05:00
Thomas Harte
7fcb1b29dd
Keep source within rectangle.
...
This gives something vaguely recognisable, sort of, for the test program I'm using.
2023-02-04 21:37:08 -05:00
Thomas Harte
6786e3e78c
Initialise to zero, for completeness.
2023-02-04 21:32:31 -05:00
Thomas Harte
67755c3811
Attempt [H/L]MMM.
2023-02-04 21:29:44 -05:00
Thomas Harte
c6372295c5
Complete ReadSourcePixel & ReadSourceByte paths.
2023-02-04 21:23:41 -05:00
Thomas Harte
a2786e6266
Invest Colour with its own logic, including potential emptiness.
2023-02-04 21:14:20 -05:00
Thomas Harte
a892523c09
Advance to the next breaking point.
2023-02-04 11:43:06 -05:00
Thomas Harte
ab595f5e8d
Merge branch 'MSX2' of github.com:TomHarte/CLK into MSX2
2023-02-04 11:02:10 -05:00
Thomas Harte
38950fe241
Sketch out remaining necessary @c AccessTypes.
2023-02-04 11:02:02 -05:00
Thomas Harte
46d009f27b
Add logical fill.
2023-02-04 10:31:41 -05:00
Thomas Harte
34722bae89
Start pivoting to a more natural expression of TMS patterns.
2023-02-03 23:06:27 -05:00
Thomas Harte
d41081c59f
Fix sections.
2023-02-02 21:55:00 -05:00
Thomas Harte
ec227ce021
Generalise rectangular operations.
2023-02-02 21:49:05 -05:00
Thomas Harte
83f6d1cda3
Prepare for source/destination operations.
2023-02-02 21:16:24 -05:00
Thomas Harte
6d315b4660
Switch to specifying number of bits, to reduce potential error.
2023-02-02 12:12:11 -05:00
Thomas Harte
debdad350d
Don't allow a disabled screen to interfere with Yamaha addressing.
2023-02-02 12:03:33 -05:00
Thomas Harte
0d4dc214fb
Merge branch 'MSX2' of github.com:TomHarte/CLK into MSX2
2023-02-02 11:38:45 -05:00
Thomas Harte
5d4c49c913
Attempt to enable high-speed fill.
2023-02-01 22:57:33 -05:00
Thomas Harte
8f5c7fcabc
Merge branch 'MSX2' of github.com:TomHarte/CLK into MSX2
2023-02-01 22:25:12 -05:00
Thomas Harte
115acf835e
Vertical state is actually tristate.
2023-02-01 22:25:00 -05:00
Thomas Harte
c0fec8db15
Clean up macro.
2023-02-01 15:05:21 -05:00
Thomas Harte
f0e70f18fd
Fix seeding of output_pointer_.
2023-02-01 14:59:42 -05:00
Thomas Harte
9d2841bf6a
Reenable full ram pointer capture. Thanks @PatrickvL !
2023-02-01 14:55:33 -05:00
Thomas Harte
ce6dd188a4
Double up on alignas
.
2023-02-01 14:31:40 -05:00
Thomas Harte
4cc34fd557
Resolve GCC complaint.
2023-02-01 14:28:19 -05:00
Thomas Harte
3636383b1f
Silence abstract/non-virtual-destructor warning.
2023-02-01 14:20:11 -05:00
Thomas Harte
1264600bab
Shorten long lines.
2023-02-01 14:18:36 -05:00
Thomas Harte
002d27d9c2
Resolve various type conversion errors, and reduce duplication.
2023-02-01 14:17:49 -05:00
Thomas Harte
90e8ce3253
Fix lines.
...
TODO: determine whether I really need `location` as distinct from `.destination`.
2023-01-31 21:33:57 -05:00
Thomas Harte
a315384e30
Provide context for byte-by-byte commands.
2023-01-31 21:29:55 -05:00
Thomas Harte
c5c722ae56
Generalise axis steps; begin HMMV.
2023-01-31 13:35:39 -05:00
Thomas Harte
872b9e5021
Predict Yamaha horizontal retrace interrupts.
2023-01-30 21:33:47 -05:00
Thomas Harte
492a170b20
Implement much of Yamaha line interrupts.
2023-01-30 21:24:53 -05:00
Thomas Harte
30a2b1611f
Merge branch 'MSX2' of github.com:TomHarte/CLK into MSX2
2023-01-30 21:06:23 -05:00
Thomas Harte
29af5542f8
Make an effort at doing _something_ for G4.
2023-01-30 21:06:04 -05:00
Thomas Harte
bc4c54800e
Type out just a little of status register 1.
2023-01-30 20:20:33 -05:00
Thomas Harte
4c93d01fe2
Reduce logging.
2023-01-29 21:30:57 -05:00
Thomas Harte
8f20cb93e9
Note missed status accesses.
2023-01-29 21:20:50 -05:00
Thomas Harte
73e79b14ea
Use Yamaha palette pervasively.
2023-01-29 21:17:00 -05:00
Thomas Harte
3142f5c21d
Be overt about what replaces LineMode.
2023-01-29 21:04:15 -05:00
Thomas Harte
6d7f189ce7
Attempt the full panoply of logical pixel modes, across all graphics modes.
2023-01-29 18:28:49 -05:00
Thomas Harte
a91a5b8d07
Refer to actual field.
2023-01-29 18:02:09 -05:00
Thomas Harte
4cdcd3ac7d
Retain logical operation, take colour combination outside the loop.
2023-01-29 13:29:19 -05:00
Thomas Harte
0576451102
Be overt about colour direction.
2023-01-29 13:22:56 -05:00
Thomas Harte
3f12a28f4f
Locate first pixel correctly.
2023-01-28 22:50:04 -05:00
Thomas Harte
41ba883fb6
Honour direction, start transfer immediately.
2023-01-28 22:47:27 -05:00
Thomas Harte
1e646eb57b
Improve transfer flag for LMMC.
2023-01-28 21:45:05 -05:00
Thomas Harte
2d6afe1013
Reduce repetition, tidy slightly.
2023-01-28 21:43:14 -05:00
Thomas Harte
d3c446d91b
Take a shot at LMMC.
2023-01-28 21:30:45 -05:00
Thomas Harte
975ead5d01
Edge towards not assuming graphics mode. Much more to do here.
2023-01-28 13:54:26 -05:00
Thomas Harte
c6cda7c401
Switch to absolute placement of deferred events; properly serialise commands.
2023-01-28 11:55:12 -05:00
Thomas Harte
7e69e33ec2
Use paletted Yamaha border colour.
2023-01-27 22:42:02 -05:00
Thomas Harte
95e00dd958
Take slightly wrong-headed steps towards proper command timing.
2023-01-27 22:20:36 -05:00
Thomas Harte
8a673a697b
Further adapt internal terminology.
2023-01-27 12:30:09 -05:00
Thomas Harte
75ad4cdb67
Fix line semantics.
2023-01-27 11:57:40 -05:00
Thomas Harte
d42b6df570
Retain extra pattern name address bits.
2023-01-27 06:44:11 -05:00
Thomas Harte
81b00c6d97
Add notes.
2023-01-26 22:25:10 -05:00
Thomas Harte
1e5f751bc0
Require STOP in order to stop.
2023-01-26 22:08:36 -05:00
Thomas Harte
9a65fffe16
That's PSET, not POINT.
2023-01-26 22:02:40 -05:00
Thomas Harte
515fa22bfe
Implement point.
2023-01-26 21:52:41 -05:00
Thomas Harte
66ac089cc2
Deallocate.
2023-01-26 21:49:32 -05:00
Thomas Harte
5d5098acb2
Hack in vertical scrolling.
2023-01-26 21:38:51 -05:00
Thomas Harte
1bf8406e7e
Correct deserialisation order.
2023-01-26 21:34:56 -05:00
Thomas Harte
75acbd2d6c
A quick hack shows some part of the MSX logo.
2023-01-26 21:31:49 -05:00
Thomas Harte
baa6f9b3cd
Implements the Command
side of the line command.
2023-01-26 21:17:11 -05:00
Thomas Harte
1c6a0ad3f7
Clean up repetition.
2023-01-26 19:51:56 -05:00
Thomas Harte
fbfa26ad5e
Minor steps towards implementing Line
.
2023-01-26 12:55:08 -05:00
Thomas Harte
b12fd00145
Generate an appropriate instance for line drawing.
2023-01-26 12:09:06 -05:00
Thomas Harte
0c8815d6a0
Retain command-engine context.
2023-01-26 11:59:27 -05:00
Thomas Harte
700470915a
Add pixel serialisation for Yamaha graphics mode 5.
2023-01-24 23:07:29 -05:00
Thomas Harte
f8b42d4107
While being lazy with types, implement 4/5/6/7 fetching.
2023-01-24 13:15:00 -05:00
Thomas Harte
63bd0f918d
Be overt about buffer target and vertical position.
2023-01-24 12:46:09 -05:00
Thomas Harte
445b34933a
Edge further towards actual fetching.
2023-01-23 23:19:04 -05:00
Thomas Harte
6b85ee9607
Months seem to start at 1; also fix seeded year for MSX.
2023-01-23 22:52:26 -05:00
Thomas Harte
bbd8b011ba
Remove temporarily-faulty check.
2023-01-23 22:52:03 -05:00
Thomas Harte
15fbf4cb7f
Ensure Yamaha-style refresh is used in all modes.
2023-01-23 22:39:34 -05:00
Thomas Harte
7293f9dc10
Remove extraneous brackets, add comment to self.
2023-01-23 22:25:56 -05:00
Thomas Harte
8567c934b1
Ensure Yamaha refresh program is used.
2023-01-22 22:11:01 -05:00
Thomas Harte
2744a9b6b0
Tidy up.
2023-01-22 22:02:39 -05:00
Thomas Harte
91047e5b3a
Start attempting to use table-based Yamaha fetch.
2023-01-22 22:00:28 -05:00
Thomas Harte
c6dd7d4726
Transcribe no-sprite event list.
2023-01-22 20:19:21 -05:00
Thomas Harte
b7d80f5ed1
Copy in some notes, expand line buffer.
2023-01-21 23:04:48 -05:00
Thomas Harte
a5765abbad
Route into the Yamaha fetcher.
...
Albeit that it doesn't yet fetch.
2023-01-21 22:47:16 -05:00
Thomas Harte
696ec12516
Add address rotation for applicable modes.
2023-01-21 22:33:26 -05:00
Thomas Harte
c9734df65c
Implement extended colour, sprite and RAM pointers.
2023-01-21 20:45:23 -05:00
Thomas Harte
13e490e7d7
Log selected screen mode.
2023-01-21 14:48:55 -05:00
Thomas Harte
cefcc1d443
Expand Yamaha graphics mode recognition.
2023-01-21 14:35:26 -05:00
Thomas Harte
d1f929e6f7
Just do a multiply and divide. Easy.
2023-01-21 14:19:52 -05:00
Thomas Harte
c9643c4145
Log memory control meaningfully.
2023-01-21 14:13:02 -05:00
Thomas Harte
e289e6e757
Catch and map Yamaha palette entries.
...
It's one less thing in the uncaptured log.
2023-01-21 14:12:46 -05:00
Thomas Harte
a726c9d97a
Enable indirect register writes.
2023-01-20 23:14:57 -05:00
Thomas Harte
c77e7c268f
1 = disable, 0 = enable.
2023-01-20 23:08:41 -05:00
Thomas Harte
9c57bfd58d
Attempt to log dropped indirect writes.
2023-01-20 23:07:14 -05:00
Thomas Harte
4efda108c6
Transcribe the Yamaha 9938 register meanings.
2023-01-20 23:00:33 -05:00
Thomas Harte
191cf4829b
Attempt real blank reporting.
2023-01-20 22:29:49 -05:00
Thomas Harte
9b7a925816
Give clearer names to the two pointers.
2023-01-20 20:29:15 -05:00
Thomas Harte
392b0acb58
Pull everything out of master_system_
struct.
...
Now that it's inherently collected in the relevant `Storage`.
2023-01-19 15:09:16 -05:00
Thomas Harte
4b7606894e
Move Master System state, and start simplifying.
2023-01-19 14:09:31 -05:00
Thomas Harte
1fb94d15ab
No need for this->
ugliness in Base
methods.
2023-01-19 12:32:42 -05:00
Thomas Harte
348c42bdea
Start trying to bluff my way through extended status.
2023-01-18 22:23:19 -05:00
Thomas Harte
e450e53c4e
Temporarily copy and paste my way to further logging.
2023-01-18 14:59:30 -05:00
Thomas Harte
355ee7fbc7
Adjust factoring of read and write per expanded V9938 scope.
2023-01-18 12:36:57 -05:00
Thomas Harte
339086d597
The Yamaha chips have more ports.
2023-01-17 22:29:17 -05:00
Thomas Harte
f0b1c34db2
Merge pull request #1116 from TomHarte/RP5C01
...
More fully implement the RP-5C01.
2023-01-17 22:25:17 -05:00
Thomas Harte
7b25fe5f61
Make read
consistent.
2023-01-17 21:18:56 -05:00
Thomas Harte
194b5bc36a
Attempt to deal with hours correctly.
2023-01-17 21:12:00 -05:00
Thomas Harte
0951c50e40
Further explain.
2023-01-17 20:14:32 -05:00
Thomas Harte
9588c9bee2
Merge branch 'RP5C01' of github.com:TomHarte/CLK into RP5C01
2023-01-17 18:53:30 -05:00
Thomas Harte
6f973fc605
Attempt some use of NumericCoder.
2023-01-17 18:53:26 -05:00
Thomas Harte
eb51ed9ae8
Shift ownership of initial values.
2023-01-17 17:36:15 -05:00
Thomas Harte
83cf4497dd
Split encode and decode for clearer naming.
2023-01-17 17:33:52 -05:00
Thomas Harte
f6e601daff
Introduce a template for numeric coding.
2023-01-17 13:26:11 -05:00
Thomas Harte
bb6ceafe0e
Implement the easy writes.
2023-01-16 22:31:03 -05:00
Thomas Harte
55e73cb812
Implement most of reading.
2023-01-16 22:25:20 -05:00
Thomas Harte
f0db676a10
Be consistent in use of C parts.
2023-01-16 20:29:32 -05:00
Thomas Harte
32b29bd63b
Transcribe all missing registers.
2023-01-16 20:26:27 -05:00
Thomas Harte
bfe94eb268
Seed date and time with current.
2023-01-16 20:11:42 -05:00
Thomas Harte
20ec192129
Merge pull request #1114 from TomHarte/SecondarySlots
...
Add support for secondary MSX slots.
2023-01-16 20:01:21 -05:00
Thomas Harte
055e9cdf8d
Differentiate unmapped and mapped-for-handler.
2023-01-16 19:52:40 -05:00
Thomas Harte
a5b9bdc18c
Eliminate speculative apply_mapping
.
2023-01-16 11:53:04 -05:00
Thomas Harte
eb51ff5cdf
Add RAM paging.
2023-01-16 11:52:08 -05:00
Thomas Harte
1769c24531
Avoid ambiguous naming.
2023-01-16 11:43:43 -05:00
Thomas Harte
1a58ddaa67
Increase notes for future self.
2023-01-15 23:12:36 -05:00
Thomas Harte
183cb519e7
Give autonomy to secondary slots.
2023-01-15 22:51:17 -05:00
Thomas Harte
68361913ee
Substitute VDP for the MSX 2.
2023-01-14 22:05:59 -05:00
Thomas Harte
ced002125e
Make a basic attempt at RAM.
2023-01-14 14:58:12 -05:00
Thomas Harte
1e17fc71ab
Add an RP-5C01 to the MSX 2.
2023-01-14 14:52:07 -05:00
Thomas Harte
f57c2a961f
Add to further project files.
2023-01-14 14:20:29 -05:00
Thomas Harte
48a4355592
Start sketching out an RP5C01.
2023-01-14 14:17:28 -05:00
Thomas Harte
3bc38d35c9
Fix include order.
2023-01-14 14:16:56 -05:00
Thomas Harte
4d67360702
Merge branch 'master' into SecondarySlots
2023-01-13 22:23:54 -05:00
Thomas Harte
18def0c97d
Correct extension ROM visibility.
2023-01-13 22:22:58 -05:00
Thomas Harte
84cb7df1be
Merge pull request #1115 from TomHarte/DynamicCull
...
Restore repeated lookup of timed machine under macOS.
2023-01-13 22:08:29 -05:00
Thomas Harte
97d93ad55c
Restore repeated lookup of timed machine.
...
This restores culling of abandoned parallel machines during dynamic analysis.
2023-01-13 22:02:56 -05:00
Thomas Harte
5f85074caa
Restore repeated lookup of timed machine.
...
This restores culling of abandoned parallel machines during dynamic analysis.
2023-01-13 22:02:15 -05:00
Thomas Harte
f0a4d1d8ec
Wire up did-page notifications.
2023-01-13 21:54:59 -05:00
Thomas Harte
fb0241cf6e
Be overt about alignment.
2023-01-13 14:30:17 -05:00
Thomas Harte
50b5122969
For an MSX 2, the extension ROM is obligatory.
2023-01-13 14:18:39 -05:00
Thomas Harte
9f450b3ccb
Expose the extension ROM to an MSX 2.
2023-01-13 14:16:12 -05:00
Thomas Harte
4190d25698
Ensure RAM is properly sized and available.
2023-01-13 14:07:54 -05:00
Thomas Harte
befc81743a
Fix base RAM mapping.
2023-01-13 09:31:56 -05:00
Thomas Harte
23ff3fc366
Ensure all routes go somewhere.
2023-01-13 08:05:12 -05:00
Thomas Harte
78ce439b9b
Add missing header; correct type.
2023-01-12 23:08:01 -05:00
Thomas Harte
ce440d52b3
Standardise name.
2023-01-12 23:02:24 -05:00
Thomas Harte
2e7e5ea12b
Fleshes out most of a cleaner memory slot layout.
2023-01-12 23:01:11 -05:00
Thomas Harte
0d8c014099
Secondary slot selections are per primary slot.
2023-01-11 13:15:00 -05:00
Thomas Harte
fee82d3baa
Fix typo.
2023-01-11 13:14:42 -05:00
Thomas Harte
76ad465030
Also seek the extension ROM for the MSX 2.
2023-01-11 12:56:09 -05:00
Thomas Harte
483ee8a74f
Add a catch for the secondary paging register.
2023-01-10 22:24:40 -05:00
Thomas Harte
520ae7f2b2
Pick generic BIOS based on machine type.
2023-01-10 22:15:01 -05:00
Thomas Harte
ae5b81c0ab
Add MSX 2 to the ROM catalogue.
2023-01-10 18:17:17 -05:00
Thomas Harte
6bd261b222
Add storage for secondary paging.
2023-01-10 18:07:31 -05:00
Thomas Harte
53bb17c848
Use model as a compile-time MSX configurator.
2023-01-10 14:55:57 -05:00
Thomas Harte
6e0f260478
Add a model field.
2023-01-10 14:52:09 -05:00
Thomas Harte
19e333d117
Merge branch 'master' into SecondarySlots
2023-01-10 14:40:49 -05:00
Thomas Harte
3352feb21b
Merge pull request #1113 from TomHarte/VDPs
...
TMS9918 &c: Eliminate hard-coded assumption of 16kb.
2023-01-10 14:40:38 -05:00
Thomas Harte
73549eb38c
Document quite a bit more, to refresh my memory.
2023-01-10 14:40:03 -05:00
Thomas Harte
dbff7592f5
Merge pull request #1112 from TomHarte/VDPs
...
Clean up TMS9918-related code.
2023-01-10 13:40:47 -05:00
Thomas Harte
4d96122884
Eliminate hard-coded assumption of 16kb.
...
Clearly I'll have to do something else to support 128k+, probably move the ram pointer?
2023-01-10 12:38:19 -05:00
Thomas Harte
9085ba4081
Update SMS VDP tests.
2023-01-09 22:58:12 -05:00
Thomas Harte
f1f16d1f9a
Clarify and simplify half_cycles_before_internal_cycles.
2023-01-09 22:55:46 -05:00
Thomas Harte
fd14829992
Avoid hand-writing all the various conversions.
2023-01-09 22:34:56 -05:00
Thomas Harte
c0fe88a5bb
Apply clock conversion to existing usages of do_external_slot.
2023-01-09 13:54:49 -05:00
Thomas Harte
4d9d684618
Add TODO on dangling hard-coded conversion.
2023-01-08 21:44:25 -05:00
Thomas Harte
a0a835cf10
Export memory size into traits.
2023-01-08 21:37:20 -05:00
Thomas Harte
ef67205ce8
Set pixel count per mode.
2023-01-08 21:31:00 -05:00
Thomas Harte
794adf470b
Break assumption that cycles = pixels; fix pixel clocking.
2023-01-08 21:25:22 -05:00
Thomas Harte
8cc20844a9
Clock convert for draw_ calls.
2023-01-08 17:31:08 -05:00
Thomas Harte
b522d65c50
Fix border lengths.
2023-01-08 17:04:19 -05:00
Thomas Harte
cb19c2ffb0
Honour internal-clocked timing constants.
2023-01-08 14:10:06 -05:00
Thomas Harte
5f6ddf8557
Avoid expressing the same thing at different clock rates.
2023-01-08 13:58:12 -05:00
Thomas Harte
72e0bfecc1
Edge towards clock-independent line composition.
2023-01-07 14:57:32 -05:00
Thomas Harte
cdf547ac82
Decline to provide synthetic text mode timing on the Mega Drive.
2023-01-07 14:37:06 -05:00
Thomas Harte
dd5b4b484a
Avoid double responsibility for state.
2023-01-07 14:34:33 -05:00
Thomas Harte
56831e02fc
Expand fixed timing constants.
2023-01-07 13:10:51 -05:00
Thomas Harte
5d2d3944ef
Make VRAM access delay a timing property.
2023-01-07 12:48:43 -05:00
Thomas Harte
f9e21df701
Avoid further hard-coded 342s.
2023-01-07 09:13:34 -05:00
Thomas Harte
bb436204f6
Merge branch 'VDPs' of github.com:TomHarte/CLK into VDPs
2023-01-07 09:10:50 -05:00
Thomas Harte
de45536b5c
Elucidate a magic constant, add an extra constexpr.
2023-01-07 09:10:41 -05:00
Thomas Harte
ebc1264c2c
Create a common home for timing information.
2023-01-06 22:39:46 -05:00
Thomas Harte
4875148617
Fill in Mega Drive numbers.
2023-01-05 14:22:51 -05:00
Thomas Harte
7a82b76911
Ensure visibility of memset.
2023-01-05 13:21:03 -05:00
Thomas Harte
27d37f71ec
Generalise and better factor bit reversal and TMS drawing.
2023-01-05 13:18:10 -05:00
Thomas Harte
c4a5a9763e
Minor indentation improvement.
2023-01-02 15:04:50 -05:00
Thomas Harte
a9f97ac871
Fix nothing-to-do test.
2023-01-02 15:04:08 -05:00
Thomas Harte
475440dc70
Update ClockConverter for potential alternative clocks.
2023-01-02 14:59:36 -05:00
Thomas Harte
dc3f8f5e42
These are the three fetchers to implement.
...
They'll look fairly different from the TMS and SMS fetchers, I think, owing to the greater irregularity that comes with the smarter RAM accesses. I might need to play around for a while.
2023-01-01 22:44:06 -05:00
Thomas Harte
459ef39b08
constexpr
the TMS palette.
2023-01-01 22:34:07 -05:00
Thomas Harte
27812fd0e2
Separate fetchers into their own header.
2023-01-01 22:26:50 -05:00
Thomas Harte
38eb4d36de
Better explain cumulative nature of @c to_internal.
2023-01-01 22:18:39 -05:00
Thomas Harte
2bd20a0cf8
Add further exposition.
2023-01-01 22:17:21 -05:00
Thomas Harte
da61909ec5
Explain the purpose here.
2023-01-01 21:20:30 -05:00
Thomas Harte
5729ece7bb
Incompletely transitions towards more flexible clock ratios.
2023-01-01 14:20:45 -05:00
Thomas Harte
151f60958e
Relocate the 9918 implementation file.
2023-01-01 14:01:19 -05:00
Thomas Harte
180045ada6
Convert vram_access_delay
into a free-standing function.
2023-01-01 13:51:52 -05:00
Thomas Harte
11542e7a7f
Improve const correctness, simplify inheritance.
2023-01-01 13:49:11 -05:00
Thomas Harte
71598250ea
Improve commentary.
2023-01-01 13:41:51 -05:00
Thomas Harte
e8aab1fd2a
Restore proper VDP selection.
2022-12-31 21:54:14 -05:00
Thomas Harte
ffb0b2ce0b
Eliminate runtime duplication of personality.
2022-12-31 21:50:57 -05:00
Thomas Harte
b7c315058f
Also template Base
.
2022-12-31 21:47:05 -05:00
Thomas Harte
7d6eac2895
Template the TMS on its personality.
...
Template parameter currently unused, but preparatory to other improvements.
2022-12-31 15:08:33 -05:00
Thomas Harte
d79aac3081
Shuffle the personality enum into the 'public' header.
2022-12-31 15:01:11 -05:00
Thomas Harte
8d5547dc9e
Minor further style improvements.
...
... as I refamiliarise myself.
2022-12-29 22:09:14 -05:00
Thomas Harte
5d89293c92
Improve const
ness, primarily of reverse_table
.
2022-12-29 11:29:19 -05:00
Thomas Harte
5ba97da6cd
Avoid macro.
2022-12-29 11:28:47 -05:00
Thomas Harte
37f07f349e
Merge branch 'master' into VDPs
2022-12-27 22:50:53 -05:00
Thomas Harte
711f7b2d75
C++17 makes this a single step.
2022-12-27 22:50:12 -05:00
Thomas Harte
dca8c51384
Prefer to avoid a macro.
2022-12-27 22:36:27 -05:00
Thomas Harte
462b7dcbfa
Add Mega Drive VRAM size.
2022-12-27 22:28:43 -05:00
Thomas Harte
2ab4b351ca
Extend enum.
2022-12-27 22:20:47 -05:00
Thomas Harte
4eedec50fb
Merge pull request #1111 from TomHarte/LessDynamic
...
Add note to future self.
2022-12-27 20:24:28 -05:00
Thomas Harte
ee22a98c17
Add note to future self.
2022-12-27 20:23:25 -05:00
Thomas Harte
99ced5476f
Add quick clock-rate notes.
2022-12-26 22:56:45 -05:00
Thomas Harte
cdbd821913
Merge pull request #1109 from TomHarte/68020Addressing
...
Support 68020+ long extensions.
2022-12-19 11:16:35 -05:00
Thomas Harte
8808014a85
Add AddressingMode::ExtensionWord
to the executor.
2022-12-19 11:07:58 -05:00
Thomas Harte
6832cbeb31
Attempt fully to tie together 68020+ addressing.
2022-12-19 10:38:51 -05:00
Thomas Harte
08b3c42a5c
Edge further towards supporting full extension words.
2022-12-10 16:22:16 -05:00
Thomas Harte
95c526d957
Start arrangements for full extension words.
2022-11-30 16:21:35 -05:00
Thomas Harte
3f3c9f7491
Update version number.
2022-11-25 15:45:44 -05:00
Thomas Harte
6aa8400996
Merge pull request #1106 from TomHarte/JoystickModifiers
...
Ensure no dangling modifiers upon shortcut keyboard switch.
2022-11-24 16:05:10 -05:00
Thomas Harte
8ccb803b08
Ensure no dangling modifiers upon shortcut keyboard switch.
2022-11-24 15:33:30 -05:00
Thomas Harte
7ce8326c8c
Merge pull request #1105 from TomHarte/AppleIIActivity
...
Add an Apple II SCSI activity indicator.
2022-11-17 11:11:28 -05:00
Thomas Harte
28b4f51cb3
Add a SCSI activity indicator.
2022-11-16 11:31:10 -05:00
Thomas Harte
2fe6253ca8
Merge pull request #1104 from TomHarte/HDV
...
Add support for Apple II .HDV files.
2022-11-15 16:11:49 -05:00
Thomas Harte
e6ae35638b
Add HDV to Info.plist.
2022-11-15 15:20:12 -05:00
Thomas Harte
812234f695
Route HDV files appropriately.
2022-11-15 15:10:04 -05:00
Thomas Harte
b921e893a2
Redirect relevant 2MG images to HDV.
2022-11-15 15:06:24 -05:00
Thomas Harte
9b235a8f64
Create a specific container for HDV files.
2022-11-15 13:18:54 -05:00
Thomas Harte
c8a82933bc
Merge pull request #1099 from TomHarte/68020
...
Expand 68k decoder to the 68020.
2022-11-14 16:08:52 -05:00
Thomas Harte
5813e2b6c6
Round out the list of operand flags.
2022-11-14 15:58:58 -05:00
Thomas Harte
005f38dbff
Merge branch 'master' into 68020
2022-11-11 20:35:35 -05:00
Thomas Harte
b77fb50e89
Merge pull request #1103 from TomHarte/snprintf
...
Remove usage of `sprintf`.
2022-11-11 20:35:22 -05:00
Thomas Harte
ae8f0d339e
Remove usage of sprintf
.
2022-11-11 20:29:59 -05:00
Thomas Harte
ccadf69630
Add test of operand_flags
and operand_size
; add entries for missing 68000 and 68010 instructions.
2022-10-31 15:15:05 -04:00
Thomas Harte
bbd2cd47ea
Decode [MUL/DIV][U/S].l.
2022-10-30 11:32:36 -04:00
Thomas Harte
63ad2e8263
Decode EXTB.l.
2022-10-30 11:20:43 -04:00
Thomas Harte
23e4a47f8b
Accept CHK.l and LINK.l decodings.
2022-10-30 11:16:32 -04:00
Thomas Harte
255d2f3486
Attempt LINK.l and CHK.l.
2022-10-29 21:42:53 -04:00
Thomas Harte
6ad1d74ddd
Parse and record duality of CHK2/CMP2.
2022-10-29 21:32:48 -04:00
Thomas Harte
12ca79e645
Decode CAS2.
2022-10-28 14:02:49 -04:00
Thomas Harte
85df54ee7d
Decode CAS.
2022-10-28 13:57:00 -04:00
Thomas Harte
2b220659dd
Incorporate PACK and UNPK.
2022-10-28 13:37:30 -04:00
Thomas Harte
8a8c044976
Support up to 15 extension words on a Preinstruction; use that to describe PACK/UNPK.
...
TODO: reconcile when to use that field versus the ExtensionWord operand. Probably only when operands are full?
2022-10-28 13:36:40 -04:00
Thomas Harte
e79388fc02
Codify RTM, TST, TRAPcc, Bcc, BF*.
2022-10-28 13:17:35 -04:00
Thomas Harte
f6a72dc2b4
Switch BFEXTU and BFFFO.
2022-10-27 12:13:13 -04:00
Thomas Harte
041eb79bf8
Move 68010 up into the verified area.
2022-10-27 10:52:26 -04:00
Thomas Harte
7d82b2ad12
Fix PACK operation code.
2022-10-27 10:52:07 -04:00
Thomas Harte
c2b8cbfefc
Add text conversions.
2022-10-27 10:12:52 -04:00
Thomas Harte
53140c016e
Disable bitcodes for operations that aren't otherwise yet present.
2022-10-27 10:09:16 -04:00
Thomas Harte
adbd23eaea
Having verified manually, lock in 68010 instruction set.
2022-10-27 09:55:02 -04:00
Thomas Harte
3f80df1feb
Additional TST modes become available on the 68020.
2022-10-27 09:49:20 -04:00
Thomas Harte
cabf1a052c
Fill in operand sizes and flags for the 68010 extensions.
2022-10-27 09:39:00 -04:00
Thomas Harte
8ff9f27b91
Decode MOVES.
2022-10-26 13:34:01 -04:00
Thomas Harte
ae2419e283
Decode MOVEC.
2022-10-26 12:50:15 -04:00
Thomas Harte
c1f0eed0a3
Decode MOVE from CCR.
2022-10-26 12:39:40 -04:00
Thomas Harte
4e5a80e23a
Fix model tests.
2022-10-25 22:36:00 -04:00
Thomas Harte
46fee9c53a
Add BKPT and RTD.
2022-10-25 22:35:44 -04:00
Thomas Harte
8ddf20b36a
Provide cleaner output.
2022-10-25 22:33:25 -04:00
Thomas Harte
7ba6c78d14
MOVE from CCR, MOVEC and MOVES are on the 68010.
2022-10-25 21:27:23 -04:00
Thomas Harte
fd20323c25
Refactor to permit newer-chip testing.
2022-10-25 21:27:01 -04:00
Thomas Harte
83b9fc3318
Declare TRAPcc operand size.
2022-10-25 12:20:40 -04:00
Thomas Harte
1ceabb30b0
Fully decode TRAPcc.
2022-10-25 12:19:03 -04:00
Thomas Harte
f8cb3ca8b5
Resolve transient GCC warning.
2022-10-25 10:20:06 -04:00
Thomas Harte
d8a11eaba7
Avoid explicit specialisation in non-namespace scope.
2022-10-25 10:13:12 -04:00
Thomas Harte
ab37b00356
Add model constraint to DIVS.l.
2022-10-25 10:04:36 -04:00
Thomas Harte
b4fcf92a62
Output extension words as if immediates.
2022-10-25 09:58:01 -04:00
Thomas Harte
38c531fd5a
Accept that a uint8_t isn't always going to be large enough; split decoding by minimum processor.
2022-10-25 09:50:19 -04:00
Thomas Harte
8c670d2105
Add decodes for TRAPcc and PACK, discovering it's three operand (sort of).
2022-10-23 11:46:47 -04:00
Thomas Harte
9a56d053f8
Introduce/extend 68k enums to cover 68020 instruction set.
2022-10-22 15:20:30 -04:00
Thomas Harte
79224d9383
Merge pull request #1098 from TomHarte/XcodeVersioning
...
Xcode: use built-in install build trigger for version script.
2022-10-21 15:29:54 -04:00
Thomas Harte
7c328edd4a
Use built-in install build trigger.
2022-10-21 15:28:50 -04:00
Thomas Harte
cb0e259339
Start the process of decoding 68020 operations.
2022-10-21 15:28:29 -04:00
Thomas Harte
9be9e1ab0c
Use built-in install build trigger.
2022-10-21 15:28:11 -04:00
Thomas Harte
149c940a29
Merge pull request #1097 from TomHarte/Templates
...
Tidy up 68000, primarily switching from macros to templates.
2022-10-19 22:31:28 -04:00
Thomas Harte
ec728ad573
Fix ADD/SUBX carry.
2022-10-19 22:17:51 -04:00
Thomas Harte
df7f94f362
Include MacintoshVolume in test build.
2022-10-19 14:41:08 -04:00
Thomas Harte
bc9ddacb8d
Improve commentary.
2022-10-19 14:40:29 -04:00
Thomas Harte
979bf42541
Fix ASL overflow test.
2022-10-18 22:43:17 -04:00
Thomas Harte
d09473b66f
Move common negative and zero logic into Status.
2022-10-18 14:51:51 -04:00
Thomas Harte
b31b4a5d10
Reformulate NOT in terms of EOR, and clean up elsewhere.
2022-10-18 12:17:55 -04:00
Thomas Harte
5560a0ed39
Fix overflow test for ASL.
2022-10-18 11:47:36 -04:00
Thomas Harte
a1ae7c28b2
Add various insurances against undefined behaviour.
2022-10-18 11:30:40 -04:00
Thomas Harte
a364499d17
Revert inadvertent commits.
2022-10-17 23:15:45 -04:00
Thomas Harte
fb2b7969a2
Add TODO to self on undefined behaviour.
2022-10-17 23:14:14 -04:00
Thomas Harte
abb19e6670
Populate carry whenever count != 0, regardless of modulo.
2022-10-17 22:57:21 -04:00
Thomas Harte
555250dbd9
Don't trample on X before use.
2022-10-17 22:19:35 -04:00
Thomas Harte
8148397f62
Fill in comments, eliminate u/s_extend16 macros.
2022-10-17 15:37:13 -04:00
Thomas Harte
f095bba1ca
Eliminate bitwise macros.
2022-10-17 15:21:54 -04:00
Thomas Harte
ee3a3df0b5
Eliminate SBCD macro.
2022-10-17 15:12:38 -04:00
Thomas Harte
aff1caed15
Clean up formatting.
2022-10-17 15:05:23 -04:00
Thomas Harte
da03cd58c1
Add overt casting.
2022-10-17 15:04:28 -04:00
Thomas Harte
ce98ca4bdd
Pull RO[L/R][X]m out of their macro stupor.
2022-10-17 11:27:04 -04:00
Thomas Harte
cc55f0586d
Clean up ASL/ASR/LSL/LSRm.
2022-10-17 11:18:10 -04:00
Thomas Harte
47e8f3c0f1
Collapse [A/L]S[L/R].[bwl] into a template.
2022-10-16 22:21:20 -04:00
Thomas Harte
d5ceb934d2
Fix overflow flags, avoid bigger-word usage.
2022-10-16 21:52:00 -04:00
Thomas Harte
17c1e51231
Commute ROL/ROR to templates.
2022-10-16 12:19:09 -04:00
Thomas Harte
fee072b404
Commute ROXL and ROXR into a template.
2022-10-16 12:06:28 -04:00
Thomas Harte
0a9c392371
Remove unused bit_count
.
2022-10-13 15:01:06 -04:00
Thomas Harte
06dbb7167b
Unify TST.
2022-10-11 21:31:14 -04:00
Thomas Harte
eff9a09b9f
Collapse MOVE and NEG[X] similarities.
2022-10-11 21:27:18 -04:00
Thomas Harte
1f19141746
Eliminate BiggerInt
.
2022-10-11 16:19:47 -04:00
Thomas Harte
28093196b9
Convert DIVU/DIVS logic to a template.
2022-10-11 16:16:53 -04:00
Thomas Harte
eb206a08d9
Templatise MULU/MULS.
2022-10-11 16:02:20 -04:00
Thomas Harte
b2f005da1b
Collapse SR/CCR bitwise operations into a template.
2022-10-11 15:53:11 -04:00
Thomas Harte
8305a3b46a
Consolidate compare logic.
2022-10-11 12:57:02 -04:00
Thomas Harte
f3f23f90a3
Consolidate repetition in CLR.
2022-10-11 11:22:34 -04:00
Thomas Harte
77bc60bf86
Consolidate BCLR, BCHG and BSET into a macro.
2022-10-11 10:47:55 -04:00
Thomas Harte
ec5d57fefe
Eliminate 64-bit work.
2022-10-11 10:33:28 -04:00
Thomas Harte
58396f0c52
Perform a prima facie conversion of ADD/SUB[/X] from macros to templates.
2022-10-10 22:21:13 -04:00
Thomas Harte
c0377f074f
Merge pull request #1095 from TomHarte/XcodeUpdate
...
macOS: enable dead code stripping; allow Xcode 14 to tag.
2022-09-16 22:05:16 -04:00
Thomas Harte
4d3221fc55
Enable dead code stripping; allow Xcode 14 to tag.
2022-09-16 19:53:36 -04:00
Thomas Harte
59388230a6
Record new macOS version number.
2022-09-16 16:14:59 -04:00
Thomas Harte
1ba4363802
Merge pull request #1094 from TomHarte/AppleIIDecoding
...
Resolve off-by-one error in Apple II sector decoding.
2022-09-16 16:04:00 -04:00
Thomas Harte
d17fadbe0b
Avoid off-by-one error in sector decoding.
...
Specific issue: retaining the 256 bytes up to _and including_ the checksum, rather than excluding.
2022-09-16 15:47:38 -04:00
Thomas Harte
9cba56237d
Upgrade to constexpr
.
2022-09-16 15:46:09 -04:00
Thomas Harte
ea9411b21c
Breakup line, for easier debugging.
2022-09-16 15:43:23 -04:00
Thomas Harte
38e85a340a
Merge pull request #1085 from TomHarte/AppleIISCSI
...
Support SCSI drives on the Apple II
2022-09-15 16:52:45 -04:00
Thomas Harte
fea8fecf11
Continue DMA requests if writing, even after a phase mismatch.
2022-09-15 16:46:22 -04:00
Thomas Harte
c4091a4cdb
Fix address mapping, implement write.
2022-09-15 16:39:19 -04:00
Thomas Harte
d826532031
Read proper file contents.
2022-09-15 16:34:20 -04:00
Thomas Harte
beca7a01c2
Treat a phase mismatch as ending DMA.
2022-09-15 16:34:06 -04:00
Thomas Harte
2d8e260671
Take a shot at the phase mismatch IRQ.
2022-09-15 16:24:06 -04:00
Thomas Harte
04f5d29ed9
Improve logging, factor out phase_matches per TODO comment.
2022-09-15 16:14:14 -04:00
Thomas Harte
5ed60f9153
Mark get_state
as const
.
2022-09-15 16:13:54 -04:00
Thomas Harte
2f78a1c7af
Add SCSI controller inclusion logic.
2022-09-15 12:17:50 -04:00
Thomas Harte
dc35ec8fa0
Merge branch 'master' into AppleIISCSI
2022-09-15 12:05:58 -04:00
Thomas Harte
7e3dbbbf0a
Merge pull request #1093 from TomHarte/IIgsFill
...
Apple IIgs: better spell out shadowing logic.
2022-09-13 16:45:49 -04:00
Thomas Harte
0f017302ce
Fix tests.
2022-09-13 16:33:44 -04:00
Thomas Harte
36c3cb1f70
Deal with pre-ROM03 case, now that it's easy.
2022-09-13 16:31:06 -04:00
Thomas Harte
6773a321c1
Switch to portable direct bitwise logic.
2022-09-13 16:02:49 -04:00
Thomas Harte
ffdf44ad4f
Switch to overt use of std::fill.
2022-09-13 15:39:17 -04:00
Thomas Harte
cb7f1e42ff
Merge pull request #1091 from TomHarte/65816DxDy
...
Fix 65816 direct, [x/y] addressing when E=1, DL != 0.
2022-09-09 16:57:10 -04:00
Thomas Harte
84a6c89a92
Merge pull request #1092 from TomHarte/68kWarning
...
Avoid returning without value in release builds.
2022-09-09 16:54:46 -04:00
Thomas Harte
451b730c8e
Avoid returning without value in release builds.
2022-09-09 16:48:12 -04:00
Thomas Harte
98d3da62b5
Apply E mode wrap for d,x and d,y only when DL = 0.
2022-09-09 16:02:35 -04:00
Thomas Harte
45dc99fb9d
Further improve exposition.
2022-09-09 15:48:25 -04:00
Thomas Harte
2edbbfbe37
Merge pull request #1090 from TomHarte/68000Tests
...
Add 68000 regression test generator.
2022-09-08 20:10:56 -04:00
Thomas Harte
dad1d7744e
Disable test generation.
2022-09-08 16:41:10 -04:00
Thomas Harte
de8ce3380c
Record only 8 bits for byte accesses.
2022-09-06 20:49:45 -04:00
Thomas Harte
b848b1389a
Include gaps in captured transactions, better collect final RAM state.
2022-09-06 15:08:35 -04:00
Thomas Harte
2c44ddfa95
Better bucket, and attempt to cover exceptions.
2022-09-06 11:26:38 -04:00
Thomas Harte
72b6ab4389
Provide a route to operation that factors in addressing mode.
2022-09-06 11:26:16 -04:00
Thomas Harte
1a7509e860
Properly announce ::SameAddress.
2022-09-05 22:26:45 -04:00
Thomas Harte
0fe94b2e6d
Capture ::SameAddress versus ::NewAddress, for TAS recognition.
2022-09-05 22:26:30 -04:00
Thomas Harte
93c1f7fc90
Include prefetch in 68000 state.
2022-09-05 22:00:04 -04:00
Thomas Harte
b6da1019bd
Bucket tests by operation, aim for ~1,000,000 total.
2022-09-05 21:52:48 -04:00
Thomas Harte
effe8c102d
Provide a direct to_string
on Operation
.
2022-09-05 21:52:20 -04:00
Thomas Harte
cee3f78059
Attempt to output only relevant RAM.
2022-09-03 15:45:06 -04:00
Thomas Harte
68f810883d
Begin process of creating on-disk tests.
2022-09-02 16:52:27 -04:00
Thomas Harte
cbfd8e18e8
Eliminate repetitive magic constants.
2022-09-02 15:54:16 -04:00
Thomas Harte
8dc1aca67c
Add TODO shout-outs.
2022-08-31 21:20:08 -04:00
Thomas Harte
acc82546c4
Further avoid use of null pointer.
2022-08-31 16:03:01 -04:00
Thomas Harte
df29a50738
Attempt to support the DMA interface.
2022-08-31 15:33:48 -04:00
Thomas Harte
d460f40b13
Improve comment.
...
Status: this now seems to be blocked at unimplemented 5380 functionality.
2022-08-30 16:44:03 -04:00
Thomas Harte
7996fe6dab
'Clock' the SCSI bus (i.e. make it aware of passing time).
2022-08-30 16:40:25 -04:00
Thomas Harte
f50ce7f137
Upgrade to an Enhanced IIe if hard drives are present.
2022-08-30 16:33:43 -04:00
Thomas Harte
6fa4e379d2
Make a hacky and blunt offer of drive data.
2022-08-30 16:07:44 -04:00
Thomas Harte
3c954e76ed
Extend to allow vending of only portions of files.
2022-08-30 15:51:29 -04:00
Thomas Harte
cd7671e8fa
Merge branch 'master' into AppleIISCSI
2022-08-29 11:47:48 -04:00
Thomas Harte
54ca168db5
Merge pull request #1089 from TomHarte/MetalPadding
...
Incorporate new additional padding.
2022-08-29 11:47:29 -04:00
Thomas Harte
330d852686
Adopt same format as the master.
2022-08-29 11:46:53 -04:00
Thomas Harte
303ea496f1
Incorporate new additional padding.
2022-08-29 11:45:11 -04:00
Thomas Harte
e7b213604e
Add comments.
2022-08-29 11:40:18 -04:00
Thomas Harte
c3007bffc9
Merge pull request #1088 from icecream95/vertex-align
...
Align Scan to be a multiple of four bytes
2022-08-29 11:29:45 -04:00
Icecream95
0499dbd4cf
Align Scan to be a multiple of four bytes
...
Some GPUs (e.g. r600) require the stride of vertex attributes to be a
multiple of four bytes, add two bytes of padding to the Scan struct to
meet this alignment requirement and reduce driver CPU overhead.
2022-08-29 16:32:25 +12:00
Thomas Harte
20d685ec5c
Permit a mass-storage device to be returned, in theory.
2022-08-26 16:38:10 -04:00
Thomas Harte
4df2a29a1f
Add storage to the bus.
2022-08-24 15:23:50 -04:00
Thomas Harte
722e3a141d
Fix types, introduce Apple II mapper.
2022-08-24 12:00:03 -04:00
Thomas Harte
91e9248ecc
Allow VolumeProviders to opt out of drivers completely.
2022-08-23 20:56:27 -04:00
Thomas Harte
22a3f4de2c
Merge branch 'master' into AppleIISCSI
2022-08-23 20:00:02 -04:00
Thomas Harte
d57464a02a
Merge pull request #1087 from TomHarte/RestoreCopyrightSymbol
...
macOS: tweak info box copyright text to include symbol and newline.
2022-08-23 19:59:39 -04:00
Thomas Harte
1346bf6fff
Add include for strlen
.
2022-08-23 19:58:48 -04:00
Thomas Harte
4ff2e7f546
Tweak info box copyright text: include symbol and newline.
2022-08-23 19:45:03 -04:00
Thomas Harte
cf356c59aa
Switch the Macintosh mapper to use Apple::PartitionMap.
2022-08-23 19:39:47 -04:00
Thomas Harte
1555b51d99
Begin a stumbling effort to generalise my implementation of the Apple Partition Map.
2022-08-23 16:46:47 -04:00
Thomas Harte
64c5b84b8b
Acknowledge that HFS is assumed.
2022-08-23 16:19:19 -04:00
Thomas Harte
017f55390a
Better represent on-disk structure.
2022-08-23 16:19:04 -04:00
Thomas Harte
6010c971a1
Provide a volume to the SCSI card if one is received.
2022-08-23 15:11:56 -04:00
Thomas Harte
ea4bf5f31a
Provide card's SCSI ID.
2022-08-23 15:05:36 -04:00
Thomas Harte
f4c242d5e9
Attempt to offer centralised C8 region decoding.
2022-08-23 14:50:44 -04:00
Thomas Harte
0595773355
Invents a new virtual select line for extended handling card ROM areas.
2022-08-23 14:41:45 -04:00
Thomas Harte
f89ca84902
Add missing include.
2022-08-22 21:44:33 -04:00
Thomas Harte
e9771ce540
Merge branch 'master' into AppleIISCSI
2022-08-22 21:43:39 -04:00
Thomas Harte
02f65cb7db
Commit new macOS version number.
2022-08-22 21:39:45 -04:00
Thomas Harte
246bd5a6ac
Merge branch 'master' into AppleIISCSI
2022-08-22 17:09:57 -04:00
Thomas Harte
1a68df6765
Merge pull request #1086 from TomHarte/AmigaCrash
...
Resolve crash of machines that require the ROM requester under macOS.
2022-08-22 17:07:59 -04:00
Thomas Harte
1b197d0bb2
Resolve crash of machines that require the ROM requester.
2022-08-22 17:02:09 -04:00
Thomas Harte
3c2d01451a
Remove dead comment.
2022-08-22 17:01:52 -04:00
Thomas Harte
4c38fa8ad3
Resolve crash of machines that require the ROM requester.
2022-08-22 17:01:41 -04:00
Thomas Harte
c2c81162a1
Sketch out some of the easy stuff.
2022-08-22 16:48:51 -04:00
Thomas Harte
3d234147a6
Add in collected specs.
2022-08-22 10:22:19 -04:00
Thomas Harte
38a509bc20
Merge pull request #1082 from TomHarte/BlitterBugSearch
...
Partially enable serialised blitter.
2022-08-22 10:08:44 -04:00
Thomas Harte
f30f13f0bc
Add overt include.
2022-08-22 10:03:24 -04:00
Thomas Harte
8e7f53751d
Add Apple II SCSI ROM to the catalogue.
2022-08-21 22:03:52 -04:00
Thomas Harte
bfc77f1606
Add workaround that further isolates whatever bug Spindizzy reveals.
2022-08-19 16:38:42 -04:00
Thomas Harte
a6b8285d9c
Factor out the blitter sequencer.
2022-08-19 16:38:15 -04:00
Thomas Harte
a675dd8c24
Merge branch 'master' into BlitterBugSearch
2022-08-19 16:18:23 -04:00
Thomas Harte
7d13768d51
Merge pull request #1083 from TomHarte/OptimisationFlags
...
Accept whatever Apple thinks is an appropriate optimisation level.
2022-08-19 16:17:55 -04:00
Thomas Harte
ce46ec4d3e
Clean up, marginally.
2022-08-19 16:12:39 -04:00
Thomas Harte
1ffd65b7af
Remove stray tab.
2022-08-19 16:12:20 -04:00
Thomas Harte
43c6db3610
Remove various other redundancies.
2022-08-19 16:12:05 -04:00
Thomas Harte
175314cd16
Accept whatever Apple thinks is an appropriate optimisation level.
2022-08-19 15:58:14 -04:00
Thomas Harte
837acdcf60
Experimentally decline immediate blits.
2022-08-16 21:51:13 -04:00
Thomas Harte
7289192130
Fix refresh slots: they're taken, not open.
2022-08-16 21:51:02 -04:00
Thomas Harte
e84e94ef61
Merge pull request #1078 from TomHarte/SerialisedBlitter
...
Moves towards proper serialisation of the Amiga Blitter.
2022-08-15 11:16:20 -04:00
Thomas Harte
bb54ac14b8
Prove that new output errors are [probably] external to the Blitter.
2022-08-15 11:10:17 -04:00
Thomas Harte
dcd66b93fd
Merge branch 'SerialisedBlitter' of github.com:TomHarte/CLK into SerialisedBlitter
2022-08-15 10:54:43 -04:00
Thomas Harte
856e3d97bf
Merge branch 'master' into SerialisedBlitter
2022-08-15 10:54:36 -04:00
Thomas Harte
c6aa83e5f2
Merge branch 'master' into SerialisedBlitter
2022-08-14 11:23:29 -04:00
Thomas Harte
1b19f93965
Merge pull request #1081 from TomHarte/STFAT12
...
Overtly treat .ST images as FAT12.
2022-08-13 10:20:08 -04:00
Thomas Harte
c7373a5d3e
Overtly treat .ST images as FAT12.
2022-08-13 10:09:34 -04:00
Thomas Harte
fb83603133
Merge pull request #1080 from TomHarte/AtariSTRAM
...
Provide 1mb and 4mb options for Atari ST memory size.
2022-08-10 21:39:52 -04:00
Thomas Harte
94231ca3e3
Put word-sizing responsibility on the caller.
2022-08-10 16:41:45 -04:00
Thomas Harte
e2a8b26b57
Display properly from greater RAM sizes.
2022-08-10 16:36:11 -04:00
Thomas Harte
b6f45d9a90
Fix struct/class confusion.
2022-08-10 15:40:46 -04:00
Thomas Harte
69f92963f9
Add Atari ST RAM size to Qt UI.
2022-08-10 15:39:55 -04:00
Thomas Harte
6b001e3106
Add ST RAM size selection to the macOS UI.
2022-08-10 14:58:19 -04:00
Thomas Harte
6d1c954623
Make ST RAM size selectable, default to 1MB.
2022-08-10 12:00:06 -04:00
Thomas Harte
bdb35b6191
Add an easier hook for debugging.
2022-08-08 21:00:28 -04:00
Thomas Harte
892580c183
Clarify test.
2022-08-08 15:57:36 -04:00
Thomas Harte
4c90a4ec93
Remove 'Faulty peek' JSON breakages.
2022-08-08 15:22:18 -04:00
Thomas Harte
f58f7102f7
Provide more context when JSON decoding fails.
2022-08-08 15:18:03 -04:00
Thomas Harte
adf3405e6b
Be overt about performance side effect.
2022-08-08 15:17:04 -04:00
Thomas Harte
8d34d9a06a
Add missing paramter.
2022-08-08 11:01:07 -04:00
Thomas Harte
0d540fd211
Merge branch 'SerialisedBlitter' of github.com:TomHarte/CLK into SerialisedBlitter
2022-08-08 10:59:50 -04:00
Thomas Harte
025c79ca65
Factor out GZip shenanigans.
2022-08-08 10:52:55 -04:00
Thomas Harte
868d179132
Compress all Blitter logs.
2022-08-07 21:55:33 -04:00
Thomas Harte
cfccfd48e5
Allow for GZipped tests.
2022-08-07 21:53:19 -04:00
Thomas Harte
2f3dfdcc67
Add Spindizzy test.
2022-08-07 21:27:11 -04:00
Thomas Harte
d4b7d73fc4
Further reduces lines to one access per slot, max.
2022-08-07 19:19:00 -04:00
Thomas Harte
867769f6e7
Reduces line drawing to two accesses per slot.
...
Still a fiction, but a better one.
2022-08-07 19:15:03 -04:00
Thomas Harte
7f423e39ed
Resolve type warning.
2022-08-07 19:03:56 -04:00
Thomas Harte
e6505dc985
Recognise that some of these traces don't capture all bus transactions.
2022-08-07 19:03:14 -04:00
Thomas Harte
bcdb2d135d
Remove partially-captured head.
2022-08-06 22:35:18 -04:00
Thomas Harte
c5d1cffad2
Include bus activity.
2022-08-06 22:21:02 -04:00
Thomas Harte
54b4a0771d
Provide better exposition.
2022-08-06 21:52:26 -04:00
Thomas Harte
85f75ab1f3
Introduce Addams Family test case.
2022-08-06 21:47:36 -04:00
Thomas Harte
668332f6c7
Any one failure will do.
2022-08-06 14:59:13 -04:00
Thomas Harte
021ddb3565
Ensure pipeline is fully flushed before registers are accessed.
2022-08-06 14:55:31 -04:00
Thomas Harte
6981bc8a82
Add yet more context.
2022-08-06 14:47:24 -04:00
Thomas Harte
7030646671
Avoid infinite loop.
2022-08-06 14:42:09 -04:00
Thomas Harte
3781b5eb0e
Provide further context.
2022-08-06 14:40:12 -04:00
Thomas Harte
e897cd99f9
Fix transcription of write.
2022-08-06 10:11:26 -04:00
Thomas Harte
cc9b6bbc61
Stop after a first mismatch.
2022-08-06 10:10:19 -04:00
Thomas Harte
318cea4ccd
Attempt a full bus-transaction comparison.
2022-08-06 10:06:49 -04:00
Thomas Harte
45892f3584
Add optional transaction records to the Blitter.
2022-08-06 09:51:20 -04:00
Thomas Harte
612413cb1c
Remove redundant state.
2022-08-04 10:06:14 -04:00
Thomas Harte
511ec5a736
Apply modulos at end of final line.
...
Possibly I need to rethink the sequence logic?
2022-07-30 21:35:26 -04:00
Thomas Harte
4fb9dec381
Fix use of bool.
2022-07-30 21:02:44 -04:00
Thomas Harte
82476bdabe
Avoid 'complete' repetition.
2022-07-30 21:02:04 -04:00
Thomas Harte
58ee8e2460
Minor tidy-up. No fixes.
2022-07-30 21:00:50 -04:00
Thomas Harte
94a90b7a89
Attempt a real slot-by-slot blit.
2022-07-30 20:34:37 -04:00
Thomas Harte
5d992758f8
Ensure blitter with all flags disabled terminates.
2022-07-30 20:13:37 -04:00
Thomas Harte
27b8c29096
Apply modulos at end of line, not beginning.
2022-07-30 10:27:53 -04:00
Thomas Harte
93d2a612ee
Add an explicit flush-pipeline step; some tests now pass.
2022-07-29 16:33:46 -04:00
Thomas Harte
03d4960a03
Begin a full-synchronous usage of the sequencer, at least exposing poor handling of the pipeline.
2022-07-29 16:15:18 -04:00
Thomas Harte
1ac0a4e924
Provide a loop count directly from the sequencer.
...
This avoids the caller having to take a guess at iterations.
2022-07-29 12:14:59 -04:00
Thomas Harte
d85d70a133
Add documentation, formal begin function.
2022-07-26 22:01:43 -04:00
Thomas Harte
76979c8059
Add missing tests.
2022-07-26 21:47:02 -04:00
Thomas Harte
86246e4f45
Introduce partial Blitter sequencer test.
2022-07-26 21:28:12 -04:00
Thomas Harte
2c95dea4db
Introduce putative blitter sequencer.
2022-07-26 17:05:05 -04:00
Thomas Harte
804c12034c
Apply blitter priority bit.
2022-07-26 16:07:26 -04:00
Thomas Harte
ce7f57f251
Switch to regular integer types for flags.
2022-07-26 09:22:05 -04:00
Thomas Harte
af7c56d313
Merge pull request #1077 from TomHarte/BroaderChroma
...
macOS: Use softer-edged luminance.
2022-07-25 13:24:42 -04:00
Thomas Harte
3e4044c7a0
Use softer-edged luminance.
2022-07-25 13:24:08 -04:00
Thomas Harte
88a22fdbf8
Merge pull request #1076 from TomHarte/DatedVersioning
...
Ensure macOS releases contain an updated version number.
2022-07-25 13:18:17 -04:00
Thomas Harte
146e739390
$ACTION seems to be the thing outside of Xcode Cloud.
2022-07-25 13:16:28 -04:00
Thomas Harte
f204162986
Use valid version numbers, only for archive builds.
2022-07-25 10:33:15 -04:00
Thomas Harte
8679854c91
Update copyright year, use valid version numbers.
2022-07-25 10:21:25 -04:00
Thomas Harte
0383d0333e
Add build date (i.e. version) into Info.plist.
2022-07-25 10:15:48 -04:00
Thomas Harte
eb0b6e9df9
Merge pull request #1075 from TomHarte/PlayfieldMasking
...
Add comments, fix playfield sprite masking.
2022-07-22 21:20:50 -04:00
Thomas Harte
426eb0f79b
Add comments, fix playfield sprite masking.
2022-07-22 17:01:38 -04:00
Thomas Harte
0b2d92048d
Merge pull request #1074 from TomHarte/SpriteContinuity
...
Reinstate assumption of no Amiga sprite fetches in vertical blank.
2022-07-21 08:48:17 -04:00
Thomas Harte
6beca141d5
Reinstate assumption of no sprites in vertical blank.
2022-07-21 08:41:50 -04:00
Thomas Harte
b67790df7d
Merge pull request #1073 from TomHarte/AmigaSprites
...
Improve Amiga sprite emulation.
2022-07-20 13:53:50 -04:00
Thomas Harte
f29d305597
Add missing #include.
2022-07-19 21:40:16 -04:00
Thomas Harte
89abf7faeb
Take a guess at reintroducing a special case for end-of-blank.
2022-07-19 21:25:34 -04:00
Thomas Harte
57186c3c14
Don't limit sprite fetch area; add further commentary.
2022-07-19 16:37:13 -04:00
Thomas Harte
feee6afe0f
Improve documentation.
2022-07-19 16:19:19 -04:00
Thomas Harte
cb42ee3ade
Eliminate DMAState
; it sounds like VSTOP solves this problem.
2022-07-19 16:11:29 -04:00
Thomas Harte
830704b4a9
Clarify and slightly improve state machine.
...
No more using the visible flag to permit a DMA control fetch.
2022-07-19 15:39:57 -04:00
Thomas Harte
0c6d7e07ee
Merge pull request #1072 from TomHarte/BetterAppDelegate
...
Eliminate purposeless AppDelegate instance storage.
2022-07-18 10:15:25 -04:00
Thomas Harte
b28a3ebb4d
Eliminate purposeless instance storage.
2022-07-18 09:35:38 -04:00
Thomas Harte
6579c12053
Merge pull request #1071 from TomHarte/EverSharper
...
macOS: Accept and embrace limits of composite sharpening.
2022-07-18 09:25:30 -04:00
Thomas Harte
28a7dc194c
Increase saturation.
2022-07-17 22:01:30 -04:00
Thomas Harte
a943a0b59a
Make sharpening slightly more aggressive.
2022-07-17 19:22:09 -04:00
Thomas Harte
80bc530d17
Merge pull request #1070 from TomHarte/ConcurrencyProjectFiles
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Remove concurrency/*.cpp from various project files.
2022-07-17 14:46:27 -04:00
Thomas Harte
68480530fe
Remove refernce to .cpp Concurrency files from Qt.
2022-07-17 14:39:15 -04:00
Thomas Harte
eadfa71b49
Remove refernce to .cpp Concurrency files from SDL.
2022-07-17 14:38:42 -04:00
Thomas Harte
9c43470c43
Merge pull request #1069 from TomHarte/AsyncTaskQueueRename
...
Switch name back to emphasise _async_.
2022-07-16 14:50:59 -04:00
Thomas Harte
8f2e94a1d8
Switch name back to emphasise _async_.
2022-07-16 14:41:04 -04:00
Thomas Harte
52c3e0592a
Merge pull request #1068 from TomHarte/HAM
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HAM: correct red/blue confusion.
2022-07-15 16:51:09 -04:00
Thomas Harte
637161157c
Switch to slightly more sensical 'none' type.
2022-07-15 16:29:29 -04:00
Thomas Harte
76d5e53094
Fix red/blue confusion.
2022-07-15 16:24:07 -04:00
Thomas Harte
b6f40fdcc7
Merge pull request #1067 from TomHarte/MachineLeak
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macOS: Avoid likely leak of machines.
2022-07-15 15:36:21 -04:00
Thomas Harte
3de1e762b7
Avoid retain cycles.
2022-07-15 15:22:12 -04:00
Thomas Harte
ee7ef81054
Avoid potential attempt to free enqueued buffers at dealloc.
2022-07-15 15:21:58 -04:00
Thomas Harte
bae47fca20
Free buffers before disposing of queue.
2022-07-15 15:13:21 -04:00
Thomas Harte
41af76bed8
Fix variable name.
2022-07-15 15:13:03 -04:00
Thomas Harte
a7515fe156
Merge pull request #1066 from TomHarte/AudioAssert
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macOS: Fix stereo buffering, various audio asserts.
2022-07-15 14:44:55 -04:00
Thomas Harte
60f997a52c
Fix stereo buffering, various audio asserts.
2022-07-14 21:59:40 -04:00
Thomas Harte
f465fe65f4
Merge pull request #1061 from TomHarte/MacintoshPixels
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Microtweak: simplify Macintosh pixel serialisation.
2022-07-14 18:54:10 -04:00
Thomas Harte
3d6ce6c13f
Merge pull request #1065 from TomHarte/QueueShakeup
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Consolidate/simplify queue classes.
2022-07-14 18:53:59 -04:00
Thomas Harte
bf03bda314
Generalise AsyncTaskQueue, DeferringAsyncTaskQueue and AsyncUpdater into a single template.
2022-07-14 16:39:26 -04:00
Thomas Harte
126838e7c7
Thanks to std::swap
and move semantics, there's no need for indirection here.
2022-07-14 15:52:31 -04:00
Thomas Harte
8310b40812
Merge pull request #1064 from TomHarte/FewerAudioAllocations
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macOS: perform audio buffer allocations ahead of time.
2022-07-14 14:58:51 -04:00
Thomas Harte
9133e25a7b
Allocate buffers once, ahead of time, and reuse.
2022-07-14 14:44:10 -04:00
Thomas Harte
ddfc2e4ca4
Provide sample length ahead of time.
2022-07-14 14:34:11 -04:00
Thomas Harte
5aa129fbd3
Merge pull request #1063 from TomHarte/EventDriven
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Switch macOS to an event-driven emulation.
2022-07-14 11:37:20 -04:00
Thomas Harte
18f01bcd48
Switch back to std::list as a kneejerk fix for AsyncTaskQueue
.
2022-07-13 22:26:59 -04:00
Thomas Harte
4c031bd335
Don't use kAudioQueueProperty_IsRunning
as it seems not to be trustworthy.
2022-07-13 22:22:19 -04:00
Thomas Harte
79f8cab5e2
Attempt to reduce memory allocations.
2022-07-13 21:41:04 -04:00
Thomas Harte
92efad4970
Switch to std::vector.
2022-07-13 21:36:01 -04:00
Thomas Harte
6a509c1280
Improve comments, marginally reduce dynamic_cast
ing.
2022-07-13 18:36:40 -04:00
Thomas Harte
dcb68c16fe
Eliminate AudioQueueBufferMaxLength
.
2022-07-13 15:24:43 -04:00
Thomas Harte
75f3f1a77f
Avoid the whole thread hop for a zero-length run_for.
2022-07-13 15:05:34 -04:00
Thomas Harte
10108303e7
Eliminate AudioQueueStop
, which is very slow, use AudioQueueStart
only as required.
2022-07-13 15:04:58 -04:00
Thomas Harte
b7ad94c676
Attempt to get a bit more rigorous in diagnosing queue stoppages.
2022-07-12 21:43:33 -04:00
Thomas Harte
1c537a877e
Remove unnecessary lock.
2022-07-12 16:22:19 -04:00
Thomas Harte
0270997acd
Add insurance against calls before setup.
2022-07-12 16:03:09 -04:00
Thomas Harte
4b9d92929a
Tweak logic.
2022-07-12 16:02:30 -04:00
Thomas Harte
5b69324ee9
Tidy up comments.
2022-07-12 15:58:16 -04:00
Thomas Harte
cce449ba8f
Merge branch 'master' into EventDriven
2022-07-12 15:06:52 -04:00
Thomas Harte
df15d60b9e
Switch to AudioQueueNewOutputWithDispatchQueue
, reducing runloop contention.
2022-07-12 15:03:35 -04:00
Thomas Harte
a0e01d4c34
Add overt flushes to the SDL target.
2022-07-12 11:03:58 -04:00
Thomas Harte
59da143e6a
Add overt flushes to the SDL target.
2022-07-12 10:57:22 -04:00
Thomas Harte
4ddbf095f3
Fully banish flush
from the processors.
2022-07-12 10:49:53 -04:00
Thomas Harte
4e9ae65459
Reintroduce sync matching.
2022-07-12 09:56:13 -04:00
Thomas Harte
d16dc3a5d7
Move limit up to 20fps.
2022-07-12 07:45:07 -04:00
Thomas Harte
a1544f3033
Do a better job of keeping the queue populated.
2022-07-11 20:50:02 -04:00
Thomas Harte
f2fb9cf596
Avoid unnecessary queue jump.
2022-07-10 21:35:05 -04:00
Thomas Harte
6dabdaca45
Switch to int
; attempt to do a better job of initial audio filling.
2022-07-09 13:33:46 -04:00
Thomas Harte
51ed3f2ed0
Reduce modal-related thread hopping.
2022-07-09 13:03:45 -04:00
Thomas Harte
b097b1296b
Adopt granular flushing widely.
2022-07-08 16:04:32 -04:00
Thomas Harte
b03d91d5dd
Permit granular specification of what to flush.
2022-07-08 15:38:29 -04:00
Thomas Harte
cf5c6c2144
Merge pull request #1062 from TomHarte/6502BRK
...
Correct 6502 for switched BRK presumption.
2022-07-08 11:24:23 -04:00
Thomas Harte
3a2d27a636
Correct for switched BRK presumption.
2022-07-08 11:15:48 -04:00
Thomas Harte
5c3084c37c
Fix construction order.
2022-07-07 20:09:37 -04:00
Thomas Harte
07ce0f0133
Attempt safe shutdown.
2022-07-07 16:56:10 -04:00
Thomas Harte
96189bde4b
Loop the Master System into the experiment.
2022-07-07 16:46:08 -04:00
Thomas Harte
fc0dc4e5e2
Amiga only, temporarily: attempt to reduce audio maintenance costs.
2022-07-07 16:41:49 -04:00
Thomas Harte
3e2a6ef3f4
Hacks up an [unsafe] return to something best-effort-updater-esque.
...
For profiling, mainly.
2022-07-07 16:35:45 -04:00
Thomas Harte
01a309909b
Elide actions when running behind.
2022-07-07 11:10:54 -04:00
Thomas Harte
7886c2df7a
Start experimenting with a more event-based approach to timing.
2022-07-07 10:48:42 -04:00
Thomas Harte
18735ee571
Merge pull request #1060 from TomHarte/QtErrors
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Resolve invalid use of `constexpr` in IPF.cpp.
2022-07-05 17:09:05 -04:00
Thomas Harte
1ce07e2ee8
This reads the file, so it can't be constexpr
.
2022-07-05 17:01:38 -04:00
Thomas Harte
7cbee172b2
Merge pull request #1041 from TomHarte/InST
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Switch the Atari ST to the newer 68000.
2022-06-30 17:15:04 -04:00
Thomas Harte
fca974723f
Merge pull request #1045 from TomHarte/InAmiga
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Switch the Amiga to the newer 68000.
2022-06-30 17:14:54 -04:00
Thomas Harte
6a2d4ae11d
Merge branch 'master' into InAmiga
2022-06-30 10:12:32 -04:00
Thomas Harte
6da634b79f
Merge branch 'master' into InST
2022-06-30 10:12:23 -04:00
Thomas Harte
c85ca09236
Merge pull request #1058 from TomHarte/ContinuousLabels
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Further compact list of potential switch targets.
2022-06-30 10:12:12 -04:00
Thomas Harte
a5b7ef5498
Further compact list of potential switch targets.
2022-06-30 08:31:51 -04:00
Thomas Harte
970087eefb
Merge pull request #1057 from TomHarte/ContinuousLabels
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68000: Eliminate large gap in `case` values.
2022-06-29 21:48:44 -04:00
Thomas Harte
11305c2e6b
Eliminate large gap in case
values.
2022-06-29 21:40:48 -04:00
Thomas Harte
5da16023d8
Merge pull request #1056 from TomHarte/Warnings
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Switch to an alternative form of avoiding unused goto warnings.
2022-06-29 21:19:34 -04:00
Thomas Harte
b1d8a45339
Just disable the diagnostic.
2022-06-29 21:13:00 -04:00
Thomas Harte
c133f80c73
Try a compiler-specific attribute.
2022-06-29 19:20:44 -04:00
Thomas Harte
58b04cdfa4
Switch to an alternative form of avoiding unused goto warnings.
2022-06-29 19:08:41 -04:00
Thomas Harte
1e149d0add
Merge pull request #1055 from TomHarte/IIgsMemoryMap
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Introduce further IIgs memory map tests.
2022-06-29 15:19:31 -04:00
Thomas Harte
f7e75da4bd
Disable [temporarily?] outdated shadowing tests.
2022-06-29 15:14:51 -04:00
Thomas Harte
c2938a4f63
Avoid potential classic macro error with address
.
2022-06-29 15:09:52 -04:00
Thomas Harte
825136b168
Fix installation of LCW test value; thereby permit all tests.
2022-06-29 15:04:21 -04:00
Thomas Harte
5a9eb58d33
Fix test generator: IO state can be cleared.
2022-06-29 14:57:14 -04:00
Thomas Harte
beb4993548
Remove card pages from the equation.
2022-06-29 14:51:50 -04:00
Thomas Harte
48e8bfbb0e
Introduce failing is-IO test.
2022-06-29 14:44:17 -04:00
Thomas Harte
5dfbc58959
Fix test generator's concept of hires2 shadowing.
2022-06-29 14:41:56 -04:00
Thomas Harte
924de35cf3
Go all in on support for physical shadowing.
2022-06-29 14:39:56 -04:00
Thomas Harte
7cf9e08948
Map shadowing by logical address, not physical.
...
Disclaimer: although this better matches the tests, I've yet to verify.
2022-06-29 06:10:15 -04:00
Thomas Harte
60d3519993
Clarify, attempt to implement as internally documented.
2022-06-28 22:32:31 -04:00
Thomas Harte
c6b4570424
Fix Markdown code marking.
2022-06-28 17:12:38 -04:00
Thomas Harte
f5d56cc473
Add first pass at testing shadowing.
2022-06-28 17:12:25 -04:00
Thomas Harte
4e52572b03
Omit language card write tests.
2022-06-28 16:57:09 -04:00
Thomas Harte
6abc317986
Avoid permitting writes in the Cx00 region after uninhibiting the language card.
2022-06-28 16:35:47 -04:00
Thomas Harte
22c0b588c4
Tidy up slightly, without fixing failure.
2022-06-28 16:32:35 -04:00
Thomas Harte
6c9fc0ac75
Introduce [failing] write area tests.
2022-06-28 16:28:00 -04:00
Thomas Harte
ef322dc705
Reformulate to allow addition of write tests, momentarily.
2022-06-28 16:22:41 -04:00
Thomas Harte
94fcc90886
Use auxiliary switches to control language card area when card is inhibited.
2022-06-28 12:46:31 -04:00
Thomas Harte
d0df156b05
Merge branch 'IIgsMemoryMap' of github.com:TomHarte/CLK into IIgsMemoryMap
2022-06-28 11:26:13 -04:00
Thomas Harte
7aeaa4a485
Tweak paging semantics, to allow simple multiple dependencies.
2022-06-27 21:38:45 -04:00
Thomas Harte
823c7765f8
Avoid manual index counting.
2022-06-27 11:16:05 -04:00
Thomas Harte
5cb0aebdf4
For the sake of poor Xcode, stop after a single failure.
2022-06-27 11:10:51 -04:00
Thomas Harte
ef40a81be2
Remove temporary hack.
2022-06-27 08:00:29 -04:00
Thomas Harte
21842052cf
Alternative zero page should affect bank 0's language card area when the card is disabled.
2022-06-27 07:56:45 -04:00
Thomas Harte
686dccb48d
Correct comparison.
2022-06-26 21:49:58 -04:00
Thomas Harte
1f7700edac
Ensure proper register hits.
2022-06-26 21:20:57 -04:00
Thomas Harte
5adc656066
Make some attempt to use the JSON tests.
2022-06-25 21:41:37 -04:00
Thomas Harte
e0ec3c986d
Ensure appropriate data bus size.
2022-06-25 21:07:29 -04:00
Thomas Harte
827b137c86
Merge pull request #1054 from TomHarte/JeekTest
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Add an automatic bus size selector.
2022-06-25 16:47:15 -04:00
Thomas Harte
9cf64ea643
Import generated tests.
2022-06-25 16:46:57 -04:00
Thomas Harte
fc1952bf42
Add an automatic bus size selector.
...
This fixes the Jeek test.
2022-06-25 16:28:06 -04:00
Thomas Harte
9888f079fa
Merge pull request #1053 from TomHarte/65816Tests
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Add 65816 test generator; correct disagreements with other emulations.
2022-06-24 21:28:24 -04:00
Thomas Harte
f2c2027a8c
Disable test generation for commit.
2022-06-24 16:50:23 -04:00
Thomas Harte
4467eb1c41
Ensure relevant throwaway stack reads use the previous stack address.
...
TODO: can CycleFetchPreviousThrowaway be used more widely?
2022-06-24 14:00:03 -04:00
Thomas Harte
ef5ac1442f
Don't invent an address for STP and WAI.
2022-06-24 13:05:32 -04:00
Thomas Harte
1c1ce625a7
Vector reads signal VDA.
2022-06-24 10:37:39 -04:00
Thomas Harte
a442077eac
Allow repetition for MVN and MVP only.
2022-06-24 10:34:43 -04:00
Thomas Harte
6c638712f3
Attempt to capture MVP and MVN in their entirety.
2022-06-24 07:39:58 -04:00
Thomas Harte
069a057a94
Resolve assumption of arithmetic shifts.
2022-06-24 07:26:07 -04:00
Thomas Harte
4ed3b21bf3
Decimal SBC tweak: negative partial results don't cause carry.
2022-06-23 21:58:09 -04:00
Thomas Harte
2e7afb13c7
Exit gracefully upon a STP or WAI.
2022-06-23 21:03:40 -04:00
Thomas Harte
a23b0f5122
Map STA (d), y
to correct calculator.
2022-06-23 20:57:47 -04:00
Thomas Harte
da552abf75
Fix BIT overflow flag.
2022-06-23 15:24:51 -04:00
Thomas Harte
380b5141fb
Be overt about conversion wanted here.
2022-06-23 13:03:26 -04:00
Thomas Harte
66775b2c4e
Always consume a second cycle in 16-bit mode.
2022-06-23 12:46:51 -04:00
Thomas Harte
2c12a7d968
Make absolutely sure there's no address bit 24.
2022-06-23 12:12:02 -04:00
Thomas Harte
5a97c09238
Flip internal presumption on the BRK flag.
2022-06-23 11:23:00 -04:00
Thomas Harte
3112376943
Don't include DBR in direct indexed indirect.
2022-06-23 11:03:37 -04:00
Thomas Harte
65140b341d
Simplify slightly, per new S reporting rule.
2022-06-22 16:43:00 -04:00
Thomas Harte
ecfd17a259
Report a 1 in the stack pointer high byte when in emulation mode.
...
It has one internally, it just wasn't previously exposed via this method.
2022-06-22 15:55:34 -04:00
Thomas Harte
a72dd96dc6
Page boundary crossing is free outside of emulation mode.
2022-06-22 15:31:30 -04:00
Thomas Harte
944e5ebbfa
Take another run at IO addresses.
2022-06-22 15:28:11 -04:00
Thomas Harte
76767110b7
Fix overflow for 8-bit calculations; essentially a revert for ADC.
2022-06-22 15:18:47 -04:00
Thomas Harte
2f684ee66d
Use null for values that were never loaded.
2022-06-21 21:47:18 -04:00
Thomas Harte
7dcfa9eb65
65816: improve decimal calculations, posted IO addresses, read/write during redundant read-modify-write cycle.
2022-06-21 14:33:06 -04:00
Thomas Harte
ec98736bd7
Ensure IO cycles don't produce an address of (PC+1).
2022-06-21 11:41:05 -04:00
Thomas Harte
ab0c290489
Use 'x' instead of 'i'.
2022-06-19 06:58:23 -04:00
Thomas Harte
15ac2c3e5a
Output to files, at volume, with extended bus flags.
2022-06-18 22:00:50 -04:00
Thomas Harte
0c24a27ba6
Completely prints tests.
2022-06-18 21:32:50 -04:00
Thomas Harte
eb82e06fab
Add randomised initial state, fix PC.
2022-06-18 19:21:56 -04:00
Thomas Harte
f8e6954739
Ensure complete runs of each tested opcode.
2022-06-18 16:26:40 -04:00
Thomas Harte
586ef4810b
Add restart_operation_fetch
, to aid with testing.
2022-06-18 16:25:57 -04:00
Thomas Harte
b62f484d93
Start scaffolding a 65816 test generator.
2022-06-18 13:28:15 -04:00
Thomas Harte
07b600ccaf
Merge branch 'master' into InST
2022-06-17 12:10:47 -04:00
Thomas Harte
907dc75e5b
Merge branch 'master' into InAmiga
2022-06-17 12:10:40 -04:00
Thomas Harte
ea0d2971eb
Merge pull request #1052 from TomHarte/StraightforwardMicrocycle
...
Clean up Microcycle helpers.
2022-06-17 12:10:22 -04:00
Thomas Harte
a0bc332fe6
Taking a second parse, prefer non-lookup-table solutions.
2022-06-17 11:55:38 -04:00
Thomas Harte
b0ab5b7b62
Simplify Microcycle helpers.
2022-06-16 21:34:24 -04:00
Thomas Harte
a3fc8dbf42
Merge branch 'master' into InAmiga
2022-06-16 16:37:49 -04:00
Thomas Harte
37516e6f6b
Merge pull request #1051 from TomHarte/STOPReturn
...
Fix return address following a STOP.
2022-06-16 15:15:50 -04:00
Thomas Harte
9fde7c0f89
Merge branch 'STOPReturn' into InST
2022-06-16 15:11:06 -04:00
Thomas Harte
dc8103ea82
Fix return address following a STOP.
2022-06-16 15:10:35 -04:00
Thomas Harte
e248092014
Fix return address following a STOP.
2022-06-16 15:10:19 -04:00
Thomas Harte
f343635cab
Merge branch 'master' into InAmiga
2022-06-16 13:37:37 -04:00
Thomas Harte
60daf9678f
Merge pull request #1050 from TomHarte/ByteLengthWarning
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Resolve release-build byte length warning
2022-06-16 11:16:37 -04:00
Thomas Harte
5d5bd6791b
Merge branch 'master' into InMacintosh
2022-06-16 11:01:18 -04:00
Thomas Harte
fe748507f0
Merge branch 'master' into InAmiga
2022-06-15 21:23:30 -04:00
Thomas Harte
cb7230e7b7
Merge branch 'master' into InST
2022-06-15 21:23:18 -04:00
Thomas Harte
cb162b6755
Merge pull request #1049 from TomHarte/68000Mk2Bus
...
Correct 68000 mark 2 Microcycle helper methods.
2022-06-15 21:22:49 -04:00
Thomas Harte
7d00b50e13
Fix upper/lower_data_select; simplify value8_low.
2022-06-15 21:11:31 -04:00
Thomas Harte
12b058867e
Correct very minor typo.
2022-06-15 19:34:54 -04:00
Thomas Harte
8ff09a1923
Fix value8_high
.
2022-06-15 19:34:49 -04:00
Thomas Harte
62fa0991ed
Disallow copying, add some basic asserts.
2022-06-15 19:34:43 -04:00
Thomas Harte
52a8566e7f
Correct very minor typo.
2022-06-15 17:06:56 -04:00
Thomas Harte
3bfcf252a8
Fix value8_high
.
2022-06-15 17:06:40 -04:00
Thomas Harte
f4ae58b1e5
Disallow copying, add some basic asserts.
2022-06-15 12:59:03 -04:00
Thomas Harte
12277d9305
Merge branch 'master' into InST
2022-06-15 11:07:43 -04:00
Thomas Harte
c9d3f4492d
Merge branch 'master' into InAmiga
2022-06-15 11:07:31 -04:00
Thomas Harte
f23c5cc6df
Merge pull request #1048 from TomHarte/STOPMk2
...
68000mk2: apply STOP status.
2022-06-15 11:07:14 -04:00
Thomas Harte
24823233ff
Add spurious interrupt support.
2022-06-15 11:00:27 -04:00
Thomas Harte
bd056973ba
Don't allow STOP state to block execution.
2022-06-15 10:56:45 -04:00
Thomas Harte
5420fd5aa3
Fix: new status word is still in prefetch.
2022-06-15 10:54:34 -04:00
Thomas Harte
44cdb4726e
Fix: new status word is still in prefetch.
2022-06-15 10:54:14 -04:00
Thomas Harte
698cc182ae
Merge branch 'STOPMk2' into InAmiga
2022-06-15 10:50:19 -04:00
Thomas Harte
93615f6647
Apply new status before entering STOP loop.
2022-06-15 10:50:03 -04:00
Thomas Harte
fba709f46d
Merge branch 'InST' of github.com:TomHarte/CLK into InST
2022-06-15 08:12:45 -04:00
Thomas Harte
bb34aaa0c7
Merge branch 'master' into InST
2022-06-15 08:12:35 -04:00
Thomas Harte
5661c3317a
Merge branch 'master' into InAmiga
2022-06-15 08:12:19 -04:00
Thomas Harte
733ffc0eee
Merge pull request #1047 from TomHarte/OldVsNew
...
Introduce randomised old vs new 68000 tests.
2022-06-15 08:11:54 -04:00
Thomas Harte
6cc41d6dda
Restore 1000 test count.
2022-06-14 22:02:53 -04:00
Thomas Harte
d91f8a264e
Flip presumption, reenabling most tests.
2022-06-14 21:57:14 -04:00
Thomas Harte
0ace9634ce
Fix MOVEA.
2022-06-14 21:56:48 -04:00
Thomas Harte
48d51759cd
At huge copy-and-paste cost, fix MOVE.l.
2022-06-14 21:22:28 -04:00
Thomas Harte
bfd0b683bf
Extend MOVE.b fix to cover MOVE.w.
2022-06-14 17:04:11 -04:00
Thomas Harte
61e0f60e94
Add specialised MOVE.b to correct bus sequencing.
...
This is a bit of a trial balloon; .w and .l to come.
2022-06-13 21:49:00 -04:00
Thomas Harte
7fa715e37a
Provide more thorough documentation.
2022-06-13 15:27:23 -04:00
Thomas Harte
e066546c13
Resolve PEA timing errors.
2022-06-13 14:08:42 -04:00
Thomas Harte
7dc66128c2
Fix strobe output.
2022-06-13 10:49:47 -04:00
Thomas Harte
e484e4c9d7
Expand test to make sure that correct data strobes are active.
2022-06-13 10:39:06 -04:00
Thomas Harte
4a75691005
Avoid double conditional for CalcEffectiveAddressIdleFor8bitDisplacementAndPreDec.
2022-06-13 10:27:22 -04:00
Thomas Harte
8ada73b283
Use the outer switch for addressing mode dispatch, saving a lot of syntax.
2022-06-13 08:57:49 -04:00
Thomas Harte
f316cbcf94
The old implementation was correct.
2022-06-11 21:15:08 -04:00
Thomas Harte
2a9a05785c
Bus and address error don't affect interrupt level.
2022-06-11 21:10:24 -04:00
Thomas Harte
0a6b2b7d32
Verify newer CMPA.l, RTE, TRAP[V] and CHK.
2022-06-11 11:17:18 -04:00
Thomas Harte
c3345dd839
Fix MOVEM timing.
2022-06-10 21:52:07 -04:00
Thomas Harte
917b7fbf80
Notarise won't fix status of CLR, NEGX, NEG, NOT.
2022-06-10 16:50:38 -04:00
Thomas Harte
97715e7ccc
Expand test set to include those with timing discrepancies.
2022-06-10 16:34:05 -04:00
Thomas Harte
43c0dea1bd
With the difference in RESET times now factored out, test timing too.
2022-06-10 16:12:54 -04:00
Thomas Harte
2e4652209b
Remove entire RESET sequence, move to testing PEA.
2022-06-10 15:57:54 -04:00
Thomas Harte
aec4bf9d45
Correct TAS timing.
2022-06-10 15:57:35 -04:00
Thomas Harte
e2d811a7a0
Notarise digressions that appear to be correct, remove now-working RTE/RTR.
2022-06-09 21:48:15 -04:00
Thomas Harte
f8643a62e6
Change RTE and RTR read order.
2022-06-09 21:47:28 -04:00
Thomas Harte
dd5c903fd6
DIVS also appears sometimes to differ.
2022-06-09 20:19:39 -04:00
Thomas Harte
2e1675066d
Reinstate address error non-testing.
2022-06-09 16:59:06 -04:00
Thomas Harte
be84ce657b
Add an optional testing whitelist.
2022-06-09 16:18:04 -04:00
Thomas Harte
64053d697f
Take improved guess at address error stacking order.
2022-06-09 16:17:09 -04:00
Thomas Harte
a59ad06438
Print out summary of failure.
2022-06-09 13:13:33 -04:00
Thomas Harte
5af03d74ec
Add note to self about first diagnosis.
2022-06-09 12:21:39 -04:00
Thomas Harte
ba2803c807
Include all bus activity after the split.
2022-06-09 11:30:22 -04:00
Thomas Harte
fdcbf617d8
Avoid STOP.
2022-06-09 08:42:31 -04:00
Thomas Harte
cc7a4f7f91
Fix test build.
2022-06-08 21:15:11 -04:00
Thomas Harte
2e42bda0a3
Permit instructions that end in an address error to differ in transactions.
2022-06-08 16:15:33 -04:00
Thomas Harte
da8e6737c6
Fix standard exception stack write order.
2022-06-08 16:15:11 -04:00
Thomas Harte
670201fcc2
Reset time debt upon 'reset'.
2022-06-08 16:03:16 -04:00
Thomas Harte
168dc12e27
Avoid spurious mismatches.
2022-06-08 16:03:02 -04:00
Thomas Harte
fd1955e15b
Attempt to randomise and test register contents.
2022-06-08 15:12:47 -04:00
Thomas Harte
ab35016aae
Clear any time debt upon phoney reset.
2022-06-08 15:12:32 -04:00
Thomas Harte
f4f93f4836
Test a single, whole instruction; record read/write.
2022-06-08 14:53:04 -04:00
Thomas Harte
6efb9b24e0
Ensure that a phoney reset gets the proper vector.
2022-06-08 14:44:15 -04:00
Thomas Harte
dd0a7533ab
Randomise all parts of memory other than the opcode.
2022-06-08 14:43:51 -04:00
Thomas Harte
079c3fd263
Abort address error-causing exceptions before they begin.
2022-06-08 14:43:31 -04:00
Thomas Harte
8cbf929671
Don't duplicate work that the RESET program already does.
2022-06-08 11:42:56 -04:00
Thomas Harte
50130b7004
Minor layout tweak.
2022-06-08 11:42:42 -04:00
Thomas Harte
ab52c5cef2
Pass first all-zeroes test, establishing that processors aren't being fully reset.
2022-06-08 10:56:54 -04:00
Thomas Harte
c7fa93a5bc
Attempt human-legible explanation of differences encountered.
2022-06-08 10:51:05 -04:00
Thomas Harte
400b73b5a2
Allow capture to be limited; retain timestamps.
2022-06-08 09:49:27 -04:00
Thomas Harte
788b026cf5
Log and attempt to compare some activity. Sort of.
2022-06-07 16:56:05 -04:00
Thomas Harte
9009645cea
Add 'reset' functions.
2022-06-07 16:55:39 -04:00
Thomas Harte
c4ae5d4c8d
Establishes at least that both 68000s can run.
2022-06-06 21:47:10 -04:00
Thomas Harte
ca8dd61045
Start sketching out an old vs new 68000 test.
2022-06-06 21:19:57 -04:00
Thomas Harte
ac037bcffd
Merge branch 'master' into InAmiga
2022-06-06 16:17:40 -04:00
Thomas Harte
d429dec2e5
Merge branch 'master' into InST
2022-06-06 16:17:33 -04:00
Thomas Harte
d779bc3784
Merge pull request #1046 from TomHarte/StatusChanges
...
Ensure RTE triggers a stack pointer change if needed.
2022-06-06 16:16:52 -04:00
Thomas Harte
a4baa33e2f
Ensure RTE triggers a stack pointer change if needed.
2022-06-06 16:08:50 -04:00
Thomas Harte
56aa182fb6
Fix debug builds.
2022-06-06 15:26:15 -04:00
Thomas Harte
9818c7e78c
Switch the Amiga to the newer 68000.
2022-06-06 11:10:56 -04:00
Thomas Harte
5495f30329
Microtweak: simplify Macintosh pixel serialisation.
2022-06-06 08:34:58 -04:00
Thomas Harte
6aa599a17c
Future-proof perform_bus_operation
.
2022-06-06 08:20:16 -04:00
Thomas Harte
57858b2fa5
Merge branch 'master' into InST
2022-06-05 20:59:48 -04:00
Thomas Harte
d4c1e92b1c
Merge pull request #1044 from TomHarte/MacintoshAudio
...
Add missing `flush`.
2022-06-05 09:20:08 -04:00
Thomas Harte
403eda7024
Add missing flush
.
2022-06-05 09:08:36 -04:00
Thomas Harte
1671827d24
Add flush
.
2022-06-05 09:07:43 -04:00
Thomas Harte
578c3e21a5
Merge branch 'master' into InST
2022-06-04 21:32:10 -04:00
Thomas Harte
87ef0d9ab3
Merge pull request #1042 from TomHarte/68000Interrupt
...
Fix interrupt acknowledge cycle: signals and data size.
2022-06-04 21:31:03 -04:00
Thomas Harte
cfafbfd141
Fix interrupt acknowledge cycle: signals and data size.
2022-06-04 21:23:57 -04:00
Thomas Harte
9289a6c1bb
Fix interrupt acknowledge cycle: signals and data size.
2022-06-04 15:20:38 -04:00
Thomas Harte
4a740fbd14
Switch Atari ST to using the new 68000.
2022-06-04 08:43:43 -04:00
Thomas Harte
7eb00c131f
Merge pull request #1036 from TomHarte/InMacintosh
...
Switch the Macintosh to the newer 68000.
2022-06-03 20:22:27 -04:00
Thomas Harte
5ae461eb0b
Avoid warning during optimised builds.
2022-06-03 15:43:27 -04:00
Thomas Harte
542126194a
Capture interrupt input at the end of an access cycle, not the beginning.
...
All still a guess.
2022-06-03 15:39:53 -04:00
Thomas Harte
a61f7e38b6
Very minor: avoid division and modulus when unnecessary.
2022-06-03 15:39:29 -04:00
Thomas Harte
3d059cb751
Make use of Microcycle helpers where relevant.
...
None of these existed when the Macintosh was first added to this emulator.
2022-06-03 15:33:31 -04:00
Thomas Harte
74e96b881c
Merge branch 'master' into InMacintosh
2022-06-03 11:20:46 -04:00
Thomas Harte
9848fa9a4d
Merge pull request #1040 from TomHarte/68000RESET
...
Fix decoding of 68000 RESET.
2022-06-03 11:20:27 -04:00
Thomas Harte
c24a7a8b58
Merge branch '68000RESET' into InMacintosh
2022-06-03 11:17:06 -04:00
Thomas Harte
71e38a6781
Fix decoding of RESET.
2022-06-03 11:15:50 -04:00
Thomas Harte
7b3cf6e747
Add missing instruction: RESET.
2022-06-03 11:15:39 -04:00
Thomas Harte
676e4a6112
Merge branch 'master' into InMacintosh
2022-06-03 10:31:07 -04:00
Thomas Harte
fd66a9b396
Merge pull request #1033 from TomHarte/68000Mk2
...
Implement a bus binding for the discrete 68000 decoder and performer.
2022-06-03 10:30:44 -04:00
Thomas Harte
640b04e59e
Test only well-defined flags.
...
Albeit that timing is still off.
2022-06-03 10:18:46 -04:00
Thomas Harte
1625796cfe
Test only well-defined flags.
...
Albeit that timing is still off.
2022-06-03 10:17:55 -04:00
Thomas Harte
93749cd650
Merge branch '68000Mk2' into InMacintosh
2022-06-03 08:38:58 -04:00
Thomas Harte
02b6ea6c46
Factor out would-accept-interrupt test, per uncertainty re: level 7.
2022-06-03 08:31:56 -04:00
Thomas Harte
6fcaf3571e
Fix bus/address error exception frame: order and contents.
2022-06-03 08:27:49 -04:00
Thomas Harte
10b9b13673
Disable divide-by-zero PC test in lieu of better documentation.
2022-06-03 08:27:20 -04:00
Thomas Harte
6cb559f65e
Merge branch '68000Mk2' of github.com:TomHarte/CLK into 68000Mk2
2022-06-02 21:43:28 -04:00
Thomas Harte
c3b436fe96
Use int64_t
as an intermediary to avoid x86 exception on INT_MIN/-1.
2022-06-02 21:39:52 -04:00
Thomas Harte
aaac777651
Merge branch 'master' into 68000Mk2
2022-06-02 17:08:41 -04:00
Thomas Harte
103de74063
Merge pull request #1039 from TomHarte/UniqueAsync
...
Switch DeferringAsyncTaskQueue to `unique_ptr`.
2022-06-02 17:06:59 -04:00
Thomas Harte
7f33a5ca0c
Simplify: (i) repetitive type for TaskList
; (ii) unnecessary unique_ptr
.
2022-06-02 17:02:36 -04:00
Thomas Harte
e389dcb912
Further simplify syntax.
2022-06-02 16:52:03 -04:00
Thomas Harte
9d278d80f1
Remove redundant reset
.
2022-06-02 16:50:59 -04:00
Thomas Harte
e994910ff6
Switch to unique_ptr
.
2022-06-02 16:46:41 -04:00
Thomas Harte
e7b3705060
Merge pull request #1007 from TomHarte/IPFFileFormat
...
Adds partial support for the IPF file format.
2022-06-02 12:58:47 -04:00
Thomas Harte
f17502fe81
Merge branch 'master' into 68000Mk2
2022-06-02 12:57:34 -04:00
Thomas Harte
8e7df5c1b1
Merge branch 'master' into InMacintosh
2022-06-02 12:57:24 -04:00
Thomas Harte
8ba1b4e0cf
Merge pull request #1037 from TomHarte/SaferShutdown
...
Reduce potential surprise in DeferringAsyncTaskQueue::flush.
2022-06-02 12:56:51 -04:00
Thomas Harte
93679f8d48
Reduce potential surprise in DeferringAsyncTaskQueue::flush.
2022-06-02 12:50:45 -04:00
Thomas Harte
a292483344
Merge branch '68000Mk2' into InMacintosh
2022-06-02 12:30:54 -04:00
Thomas Harte
90d720ca28
Don't test undocumented flags.
2022-06-02 12:30:39 -04:00
Thomas Harte
f8e933438e
Add missing tail cost.
2022-06-02 12:26:25 -04:00
Thomas Harte
6dd89eb0d7
Adjust my expectation as to length.
2022-06-02 12:11:54 -04:00
Thomas Harte
2bd20446bb
Merge branch '68000Mk2' of github.com:TomHarte/CLK into 68000Mk2
2022-06-02 05:39:32 -04:00
Thomas Harte
659e4f6987
Include fixed cost of rolls. Which includes providing slightly more information to did_shift
.
2022-06-01 20:30:51 -04:00
Thomas Harte
cd5f3c90c2
Ensure proper resumption after a forced exit in will_perform
.
2022-06-01 15:27:09 -04:00
Thomas Harte
91a6911a51
Correct ADDA/SUBA timing.
2022-06-01 15:03:03 -04:00
Thomas Harte
0857dd0ae5
Include fixed base cost in MULU and MULS.
2022-06-01 14:05:23 -04:00
Thomas Harte
8c242fa2dd
Merge branch '68000Mk2' into InMacintosh
2022-06-01 10:48:38 -04:00
Thomas Harte
5a4f117a12
Merge branch '68000Mk2' of github.com:TomHarte/CLK into 68000Mk2
2022-06-01 10:48:14 -04:00
Thomas Harte
62ed1ca2fd
Fix MOVE CCR permissions.
2022-06-01 09:22:47 -04:00
Thomas Harte
d1298c8863
Correct MOVE timing without breaking PEA, LEA, etc.
2022-06-01 09:06:08 -04:00
Thomas Harte
75e85b80aa
Factor out the common stuff of exception state.
2022-06-01 08:20:33 -04:00
Thomas Harte
73815ba1dd
No need for this hoop jumping here.
2022-06-01 08:20:06 -04:00
Thomas Harte
e1abf431cb
Don't test undefined flags.
2022-05-30 16:23:51 -04:00
Thomas Harte
8e0fa3bb5f
DIV # with a divide by zero should be 44 cycles.
2022-05-29 21:22:45 -04:00
Thomas Harte
8ffaf1a8e4
Ensure did_divu/s are performed even upon divide by zero.
2022-05-29 21:18:19 -04:00
Thomas Harte
7788a109b0
Tweak more overtly to avoid divide by zero.
2022-05-29 20:51:50 -04:00
Thomas Harte
9eea471e72
Resolve infinite recursion.
2022-05-29 20:39:22 -04:00
Thomas Harte
3ef53315a2
Don't try to append operands to 'None'.
2022-05-29 15:28:16 -04:00
Thomas Harte
2a40e419fc
Fix CHK tests: timing and expected flags.
2022-05-29 15:26:56 -04:00
Thomas Harte
d6f72d9862
Avoid runtime checking of instruction supervisor requirements.
2022-05-29 14:56:44 -04:00
Thomas Harte
3da720c789
Make requires_supervisor
explicitly compile-time usable.
2022-05-29 14:55:24 -04:00
Thomas Harte
dbf7909b85
Fix timing of CMPM.
2022-05-29 14:49:42 -04:00
Thomas Harte
57aa8d2f17
Correct timing of ADDQ.
2022-05-29 14:34:06 -04:00
Thomas Harte
a318a49c72
Merge branch '68000Mk2' into InMacintosh
2022-05-28 15:01:58 -04:00
Thomas Harte
35e73b77f4
Fix interrupt stack frame.
2022-05-27 21:55:17 -04:00
Thomas Harte
698d1a7111
Fix interrupt stack frame.
2022-05-27 21:54:23 -04:00
Thomas Harte
1365fca161
Avoid phoney write modifies.
2022-05-27 21:42:55 -04:00
Thomas Harte
d17d77714f
Remove outdated TODO.
2022-05-27 15:40:06 -04:00
Thomas Harte
e8dd8215ba
Tweak per empirical results.
2022-05-27 15:39:02 -04:00
Thomas Harte
e11990e453
Make an attempt at DIVS timing.
2022-05-27 15:38:54 -04:00
Thomas Harte
165ebe8ae3
Add time calculation for MULU and MULS.
2022-05-27 15:38:14 -04:00
Thomas Harte
e746637bee
Fill in dynamic cost of shifts.
2022-05-27 15:38:08 -04:00
Thomas Harte
0e6370d467
Tweak per empirical results.
2022-05-27 15:37:40 -04:00
Thomas Harte
512cd333e5
Make an attempt at DIVS timing.
2022-05-27 14:56:04 -04:00
Thomas Harte
f599a78cad
Add time calculation for MULU and MULS.
2022-05-27 14:41:42 -04:00
Thomas Harte
7601dab464
Fill in timing calculation for DIVU.
2022-05-27 14:30:03 -04:00
Thomas Harte
a8623eab4a
Fill in dynamic cost of shifts.
2022-05-27 11:12:10 -04:00
Thomas Harte
c367ddff1b
Merge branch '68000Mk2' into InMacintosh
2022-05-27 10:34:11 -04:00
Thomas Harte
67b340fa5e
Fix interrupt request address.
2022-05-27 10:33:36 -04:00
Thomas Harte
c97245e626
Fix CalcEA timing; make MOVEfromSR a read-modify-write.
2022-05-27 10:32:28 -04:00
Thomas Harte
79e2c17f93
Fix interrupt request address.
2022-05-26 20:20:28 -04:00
Thomas Harte
5937737bb7
Merge branch '68000Mk2' into InMacintosh
2022-05-26 19:37:44 -04:00
Thomas Harte
5f030edea4
Simplify transaction.
2022-05-26 19:37:30 -04:00
Thomas Harte
88e33353a1
Fix instruction and time counting, and initial state.
2022-05-26 09:17:37 -04:00
Thomas Harte
f3c0c62c79
Switch register-setting interface.
2022-05-26 07:52:14 -04:00
Thomas Harte
866787c5d3
Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence.
2022-05-25 20:22:38 -04:00
Thomas Harte
367ad8079a
Add a call to set register state with population of the prefetch.
2022-05-25 20:22:05 -04:00
Thomas Harte
64491525b4
Work further to guess at caller's intention for set_state.
...
Probably I should just eliminate the initial reset, somehow.
2022-05-25 17:01:18 -04:00
Thomas Harte
68b184885f
Reapply only the status.
2022-05-25 16:54:25 -04:00
Thomas Harte
06f3c716f5
Make better effort to establish initial state.
2022-05-25 16:47:41 -04:00
Thomas Harte
22714b8c7f
Capture state at instruction end, for potential inspection.
2022-05-25 16:32:26 -04:00
Thomas Harte
80c1bedffb
Eliminate false prefetch for BSR.
2022-05-25 16:32:02 -04:00
Thomas Harte
56ad6d24ee
Fix ANDI/ORI/EORI to CCR/SR timing.
2022-05-25 16:20:26 -04:00
Thomas Harte
4ad0e04c23
Fix macro for n
being an expression.
2022-05-25 16:05:45 -04:00
Thomas Harte
f9d1c554b7
Fix for the actual number of cycles in a standard reset.
2022-05-25 16:05:28 -04:00
Thomas Harte
ee58301a46
Add RaiseException
macro.
2022-05-25 15:45:09 -04:00
Thomas Harte
f2a7660390
Merge branch 'master' into 68000Mk2
2022-05-25 15:40:10 -04:00
Thomas Harte
d4c7ce2d6f
Merge pull request #1035 from TomHarte/68000TestIssues
...
Add details on gaps in coverage.
2022-05-25 15:39:42 -04:00
Thomas Harte
4961e39fb6
Mention DIVU/DIVS flags.
2022-05-25 15:39:00 -04:00
Thomas Harte
0bedf608c0
Add details on gaps in coverage.
2022-05-25 15:36:27 -04:00
Thomas Harte
1ab831f571
Add the option to log a list of all untested instructions.
2022-05-25 13:17:01 -04:00
Thomas Harte
b90f1a48ce
Merge branch '68000Mk2' into InMacintosh
2022-05-25 13:02:44 -04:00
Thomas Harte
72425fc2e1
Fix bus data size of MOVE.b xx, -(An).
2022-05-25 13:00:36 -04:00
Thomas Harte
a5f2dfbc0c
Initialise registers to 0 for better testability.
...
TODO: is this the real initial state?
2022-05-25 11:47:42 -04:00
Thomas Harte
5db6a937cb
Have TRAP and TRAPV push the next instruction address to the stack.
2022-05-25 11:47:21 -04:00
Thomas Harte
9709b9b1b1
Standard exceptions don't raise the interrupt level.
2022-05-25 11:37:39 -04:00
Thomas Harte
2c6b9b4c9d
Switch comparative trace tests to 68000 Mk2.
2022-05-25 11:32:00 -04:00
Thomas Harte
463fbb07f9
Adapt remaining 68000 tests to use Mk2.
2022-05-25 10:55:17 -04:00
Thomas Harte
b6e473a515
Adapt remaining 68000 tests to use Mk2.
2022-05-25 10:55:03 -04:00
Thomas Harte
24f7b5806c
Merge branch '68000Mk2' into InMacintosh
2022-05-25 08:15:41 -04:00
Thomas Harte
5872e0ea4a
Resolve MOVE.l xx, -(An) write target.
2022-05-25 08:15:18 -04:00
Thomas Harte
04d2d6012a
Merge branch '68000Mk2' into InMacintosh
2022-05-24 16:08:56 -04:00
Thomas Harte
f43d27541b
Avoid attempt to establish operand flags for undefined opcodes.
2022-05-24 15:53:12 -04:00
Thomas Harte
c8d3d980ba
Avoid attempt to establish operand flags for undefined opcodes.
2022-05-24 15:52:53 -04:00
Thomas Harte
f93bf06b99
Merge branch '68000Mk2' into InMacintosh
2022-05-24 15:51:22 -04:00
Thomas Harte
0f7cb2fa5a
Attempt to honour the trace flag.
2022-05-24 15:47:47 -04:00
Thomas Harte
01e93ba916
Make an attempt at bus/address error.
2022-05-24 15:42:50 -04:00
Thomas Harte
780954f27b
Add TRAP, TRAPV.
2022-05-24 15:14:46 -04:00
Thomas Harte
19d69bdbb5
Add TRAP, TRAPV.
2022-05-24 15:14:20 -04:00
Thomas Harte
27fac7af86
Merge branch '68000Mk2' into InMacintosh
2022-05-24 12:48:54 -04:00
Thomas Harte
6f048de973
Pull unrecognised instruction handling into the usual switch table.
2022-05-24 12:42:34 -04:00
Thomas Harte
a611a745e7
Switch the Macintosh to 68000 mk2.
2022-05-24 12:35:36 -04:00
Thomas Harte
0dfaa7d9cf
Interrupt fixes: supply proper address, raise level, fetch from vector.
2022-05-24 12:16:06 -04:00
Thomas Harte
eab720f6ea
Ensure proper transition from unrecognised instructions.
2022-05-24 12:16:00 -04:00
Thomas Harte
8ad1d6b813
Interrupt fixes: supply proper address, raise level, fetch from vector.
2022-05-24 12:15:35 -04:00
Thomas Harte
be684d66fd
Ensure proper transition from unrecognised instructions.
2022-05-24 11:36:11 -04:00
Thomas Harte
a7e8aef9d3
Add MOVEA, be slightly more careful about next_operand_.
2022-05-24 11:30:09 -04:00
Thomas Harte
4b07c41df9
Ensure alignment of storage.
2022-05-24 11:29:28 -04:00
Thomas Harte
df54f1f1b7
Update TODO.
2022-05-24 11:06:05 -04:00
Thomas Harte
9e3c2b68d7
Eliminate potential future implicit conversion warnings.
2022-05-24 11:05:24 -04:00
Thomas Harte
3349bcaaed
Attempt interrupt support.
2022-05-24 10:53:59 -04:00
Thomas Harte
3a4fb81242
Add a dummy STOP state.
2022-05-24 10:25:40 -04:00
Thomas Harte
1df3ad0671
Ensure TAS responds to VPA, BERR.
2022-05-24 09:17:58 -04:00
Thomas Harte
523cdd859b
Add bus and address error, and VPA checks.
2022-05-24 09:08:31 -04:00
Thomas Harte
b037c76da6
Add public interface for everything except HALT and BUS REQ/etc.
...
... neither of which are used by machines I currently implement.
2022-05-23 20:55:01 -04:00
Thomas Harte
9cac4ca317
Add MOVE to/from USP.
2022-05-23 20:42:41 -04:00
Thomas Harte
34e5f39571
Ensure that running exactly up to a boundary gives the bus handler the next microcycle to contemplate.
2022-05-23 15:11:33 -04:00
Thomas Harte
e0a279344c
Codify the existence of special cases, implement NOP and RESET.
2022-05-23 15:09:46 -04:00
Thomas Harte
e2f4db3e45
Shuffle more of the flow controller methods into their proper place.
2022-05-23 12:06:14 -04:00
Thomas Harte
cdb9eae1ee
Merge branch 'master' into 68000Mk2
2022-05-23 11:02:57 -04:00
Thomas Harte
c1837af84a
Add notes to self on work remaining.
2022-05-23 11:02:31 -04:00
Thomas Harte
a87f6a28c9
Fix LINK A7.
2022-05-23 10:43:17 -04:00
Thomas Harte
98325325b1
Fix UNLINK A7.
2022-05-23 10:27:44 -04:00
Thomas Harte
26bf66e3f8
Fix shifts and rolls.
2022-05-23 10:09:46 -04:00
Thomas Harte
363cd97154
Resolve double definition of did_shift
.
2022-05-23 10:07:24 -04:00
Thomas Harte
5eb19da91f
Merge pull request #1034 from fedex81/patch-1
...
Update nbcd_pea.json
2022-05-23 10:06:01 -04:00
Thomas Harte
c6b3281274
Attempt the shifts and rolls.
2022-05-23 09:29:19 -04:00
Thomas Harte
1e8adc2bd9
Fix MOVEP to R.
2022-05-23 09:00:37 -04:00
Thomas Harte
c73021cf3c
Implement MOVE.
2022-05-23 08:46:06 -04:00
Thomas Harte
1b3acf9cd8
Eliminate assumption.
2022-05-23 08:18:37 -04:00
Federico Berti
1a26d4e409
Update nbcd_pea.json
...
Add missing bracket
2022-05-23 12:14:00 +01:00
Thomas Harte
c8ede400eb
Fix RTE.
2022-05-22 21:17:28 -04:00
Thomas Harte
269263eecf
Implement RTE, RTS, RTR.
2022-05-22 21:16:38 -04:00
Thomas Harte
4e21cdfc63
Enable NEGX/CLR tests.
2022-05-22 20:55:21 -04:00
Thomas Harte
faef5633f8
Ensure MOVE from SR has an effective address to write to.
2022-05-22 20:52:00 -04:00
Thomas Harte
7d1f1a3175
Implement MOVE [to/from] [CCR/SR].
2022-05-22 19:45:22 -04:00
Thomas Harte
4e34727195
Fully implement TAS.
2022-05-22 16:14:03 -04:00
Thomas Harte
1dd6ed6ae3
Implement TAS Dn, with detour for other TASes.
2022-05-22 16:08:30 -04:00
Thomas Harte
cb4d6710df
Switch to a more direct indication of progress.
2022-05-22 11:27:58 -04:00
Thomas Harte
3b68b9a83b
Implement PEA.
2022-05-22 11:27:38 -04:00
Thomas Harte
4279ce87ea
Implement LEA.
2022-05-22 08:29:12 -04:00
Thomas Harte
3c1c4f89e9
Add MULU/S functionality, though not timing.
2022-05-22 08:02:32 -04:00
Thomas Harte
4a6512f5d5
Reduce dispatch boilerplate.
2022-05-22 07:39:16 -04:00
Thomas Harte
284f23c6ea
Implement JMP.
2022-05-22 07:16:38 -04:00
Thomas Harte
11a9a5c126
Use common macros for the two forms of Perform.
2022-05-22 07:08:14 -04:00
Thomas Harte
4993801741
Add missing prefetch to BSET, BCHG, BCLR.
2022-05-21 21:05:05 -04:00
Thomas Harte
4b35899a12
Bcc: properly establish offset.
2022-05-21 20:59:34 -04:00
Thomas Harte
1304e930eb
DBcc is two-operand.
2022-05-21 20:06:03 -04:00
Thomas Harte
94288d5a94
Excludes DBcc from standard operand fetch.
2022-05-21 19:53:28 -04:00
Thomas Harte
3811ab1b82
Fix the two 8bit-with-displacement effective address Calc steps.
2022-05-21 16:20:01 -04:00
Thomas Harte
c869eb1eec
Correct omission: wasn't testing the final PC.
...
Plenty of new errors incoming.
2022-05-21 15:56:27 -04:00
Thomas Harte
f97d2a0eb9
Add DIVU/DIVS, at least as far as getting the correct numeric result.
2022-05-21 15:56:09 -04:00
Thomas Harte
176c8355cb
The tests in chk.json now pass.
2022-05-21 14:32:58 -04:00
Thomas Harte
2258434326
Ensure proper return addresses are calculated for JSR.
2022-05-21 14:28:44 -04:00
Thomas Harte
e46a3c4046
Implement JSR.
2022-05-21 10:29:36 -04:00
Thomas Harte
0e4cfde657
Fix MOVEM predec.
2022-05-21 08:17:39 -04:00
Thomas Harte
4bd9c36922
Fix postincrement mode.
2022-05-20 21:01:23 -04:00
Thomas Harte
256da43fe5
Fix MOVEM other than postinc and predec.
2022-05-20 20:47:54 -04:00
Thomas Harte
6a442e0136
MOVEM has an immediate first operand.
2022-05-20 20:34:51 -04:00
Thomas Harte
a818650027
Add a faulty attempt at MOVEM.
2022-05-20 18:48:19 -04:00
Thomas Harte
9d79e64f5c
Add a mere calculate effective address pathway.
...
Plus a lot of waffle to try to justify the further code duplication.
2022-05-20 16:23:52 -04:00
Thomas Harte
c7c12f9638
After a quick check, eori_andi_ori also now passes.
2022-05-20 14:47:11 -04:00
Thomas Harte
ee942c5c17
Fix PC-relative fetches.
2022-05-20 14:42:51 -04:00
Thomas Harte
d157819c49
Implement the various to-[SR/CCR] actions, which do a 'repeat' prefetch.
...
(which isn't exactly a repeat, at least in the SR cases, because the function code might have changed)
2022-05-20 14:29:14 -04:00
Thomas Harte
2d91fb5441
Implement MOVEP.
2022-05-20 14:22:32 -04:00
Thomas Harte
81431a5453
Attempt BTST, BCHG, BCLR and BSET.
2022-05-20 12:58:45 -04:00
Thomas Harte
6d7ec07216
Uncover another three already-working test files.
2022-05-20 12:44:57 -04:00
Thomas Harte
b4978d1452
Implement BSR, adding one more test file to the working set.
2022-05-20 12:40:35 -04:00
Thomas Harte
cb77519af8
Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.
2022-05-20 12:40:09 -04:00
Thomas Harte
45e9648b8c
Implement Bcc.
2022-05-20 12:04:43 -04:00
Thomas Harte
ce32957d9d
Shuffle two more into the working column.
2022-05-20 11:53:12 -04:00
Thomas Harte
ba8592ceae
At least on the 68000, Scc is read-modify-write.
2022-05-20 11:43:26 -04:00
Thomas Harte
4327af3760
DBcc: add write-back.
2022-05-20 11:37:18 -04:00
Thomas Harte
860cc63e21
Attempt DBcc.
2022-05-20 11:32:06 -04:00
Thomas Harte
452dd3ccfd
Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.
2022-05-20 11:20:23 -04:00
Thomas Harte
e5c1621382
Add missing fallthrough
, patterns for all ADDs and SUBs.
2022-05-20 07:02:02 -04:00
Thomas Harte
af3518dc1f
Implement various ADD, SUB patterns.
2022-05-19 20:50:37 -04:00
Thomas Harte
6cfc0e80d9
Don't test the unrecognised instruction exception.
2022-05-19 19:45:38 -04:00
Thomas Harte
1ee9c585ca
Fix segue into second operand.
2022-05-19 19:38:42 -04:00
Thomas Harte
efe5a5ac26
Signal will_perform even for invalid instructions.
2022-05-19 18:50:43 -04:00
Thomas Harte
334e3ec529
Add privilege and instruction error exceptions; permit two operands to be stored.
2022-05-19 16:55:16 -04:00
Thomas Harte
84c165459f
ext.json now passes.
2022-05-19 16:32:40 -04:00
Thomas Harte
282c4121d6
CLR also follows the NEGX/NEG/NOT pattern.
2022-05-19 16:30:08 -04:00
Thomas Harte
6c2eee0e44
Implement CHK, and therefore the standard exception pattern.
2022-05-19 16:27:39 -04:00
Thomas Harte
eeb6a088b8
Add a tag to avoid duplication.
2022-05-19 15:49:42 -04:00
Thomas Harte
22b63fe1f8
Add EXT, and notes to self.
2022-05-19 15:41:02 -04:00
Thomas Harte
7ef526e2d3
Fix destination decrement.
2022-05-19 15:22:59 -04:00
Thomas Harte
ce7f94559b
Add EXG, ABCD, SBCD.
2022-05-19 15:19:00 -04:00
Thomas Harte
0471decfc8
Implement the complete set of fetch addressing modes.
...
Subject to observations: (1) MOVE uses slightly custom versions of many of these for its stores; and (2) PEA and LEA need to do the calculation but not the read, so some of this will be duplicated further. It's either that or include greater conditionality on the path.
2022-05-19 15:03:22 -04:00
Thomas Harte
e4c0a89889
Just use the four-bit register number directly.
2022-05-19 15:01:09 -04:00
Thomas Harte
084d6ca11d
Simplify address handling; add perform patterns for CMP, AND, OR, EOR.
2022-05-19 12:18:47 -04:00
Thomas Harte
274902c3c1
Add to-memory write-back. Am going to reconsider usage of temporary_address_ as noted.
2022-05-19 11:23:26 -04:00
Thomas Harte
f46e7c65c5
Add AddressRegisterIndirect fetches.
2022-05-19 10:47:57 -04:00
Thomas Harte
c6c6213460
Bifurcate the fetch-operand flow.
...
Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.
2022-05-19 10:27:51 -04:00
Thomas Harte
29f6b02c04
Factor out register setup/testing, generalising the DIVU/DIVS flag check.
2022-05-18 21:13:34 -04:00
Thomas Harte
1bf7c0ae5f
Attempt better to avoid entering a second instruction.
2022-05-18 21:00:34 -04:00
Thomas Harte
1b87626b82
Move some way towards MOVE.
2022-05-18 21:00:10 -04:00
Thomas Harte
44ae084794
Avoid the repeated .fill; reduces debug-build executor test time to 1.5s.
...
i.e. eliminates about 95% of costs.
2022-05-18 17:10:23 -04:00
Thomas Harte
13a1809101
Avoid memset.
2022-05-18 17:00:35 -04:00
Thomas Harte
c35200fbd0
Shuffle mildly, primarily to avoid repeated 16mb allocations.
2022-05-18 16:59:37 -04:00
Thomas Harte
da9fb216b1
Remove setup_operation in favour of doing the equivalent inline.
...
... as it'll probably allow me a route to `goto` straight out of there, too. At least, if I can find a sufficiently neat macro formulation.
2022-05-18 16:45:40 -04:00
Thomas Harte
bef12f3d65
Move ExecutionState
into Implementation.hpp; use goto
to avoid some double switches.
...
Re: the latter, yuck. Yuck yuck yuck. But it does mean I can stop going back and forth on how to structure conditionality on effective address generation segueing into fetches without doubling up on tests.
2022-05-18 15:35:38 -04:00
Thomas Harte
aa9e7eb7a2
Codify MOVE's status somewhat, avoid reading write-only operands.
2022-05-17 16:57:33 -04:00
Thomas Harte
f3d3e588fd
Add enough of state to [sort-of] pass the first test.
...
i.e. until the processor overruns, as it is permitted to do, and can't handle the second instruction.
2022-05-17 16:51:26 -04:00
Thomas Harte
4a40581deb
Completes performance of NBCD D0.
2022-05-17 16:10:20 -04:00
Thomas Harte
eed2672db5
Add documentation, honour signal_will_perform
.
2022-05-17 15:05:11 -04:00
Thomas Harte
84071ac6d0
Implement reset logic, advance as far as actually performing an NBCD on D0 (but not writing it back).
2022-05-17 14:51:49 -04:00
Thomas Harte
1a27eea46c
Establish general pattern for selecting a performance phase and obtaining operands.
2022-05-17 14:08:50 -04:00
Thomas Harte
d0b6451f02
Step gingerly on to fetching operands.
2022-05-17 08:26:35 -04:00
Thomas Harte
2147c5a5f2
Fill in missing #undefs.
2022-05-16 21:02:25 -04:00
Thomas Harte
c7aa4d8b6d
Fix state transitions.
...
Confirmed that the 68000 mk 2 now appears correctly to perform a reset.
2022-05-16 21:00:25 -04:00
Thomas Harte
e94efe887c
Switch to use of __COUNTER__.
2022-05-16 20:38:17 -04:00
Thomas Harte
3db2de7478
Works 68000 mk2 into the comparative tests.
...
... revealing that I've leant a little too hard on __LINE__.
2022-05-16 20:04:13 -04:00
Thomas Harte
345f7c3c62
Fill in just enough to attempt the reset exception, assuming DTACK rather than VPA or BERR.
2022-05-16 16:57:40 -04:00
Thomas Harte
13848ddbbc
Add half-and-half access for SlicedInt32.
2022-05-16 16:56:54 -04:00
Thomas Harte
6f6e466c08
Make a first sketch of the coroutine-esque structure I'm going to experiment with here.
2022-05-16 11:59:03 -04:00
Thomas Harte
b0518040b5
Plants the seek of a 68000 mark 2.
2022-05-16 11:44:16 -04:00
Thomas Harte
29c872d867
Merge pull request #1032 from TomHarte/68000DIVUDIVS
...
Generalises the 68000's DIVU and DIVS.
2022-05-15 20:33:22 -04:00
Thomas Harte
acb63a1307
Pull generalised DIVU/DIVS into a macro.
2022-05-15 20:01:51 -04:00
Thomas Harte
341bf2e480
Repattern DIVS after DIVU.
2022-05-15 16:54:58 -04:00
Thomas Harte
20a191f144
Switch to same tests, run through a more modern emulator.
2022-05-15 16:33:08 -04:00
Thomas Harte
81f4581f41
Merge pull request #1031 from TomHarte/BCDTests
...
Correct 68000 BCD test results.
2022-05-15 07:24:30 -04:00
Thomas Harte
dfaf8ce64e
Merge pull request #1028 from TomHarte/68000Perform
...
Add free function implementation of 68000 operations, and an instruction-set interpreter.
2022-05-15 07:21:03 -04:00
Thomas Harte
f60f1932f2
Restrict DIVU and DIVS tests to those which are well-defined.
2022-05-14 20:28:54 -04:00
Thomas Harte
ff8e4754d7
Ensure STOP exits the run loop.
2022-05-14 19:17:32 -04:00
Thomas Harte
27c4d19455
Support STOP.
2022-05-14 11:35:35 -04:00
Thomas Harte
7f704fdae1
Improve README.
2022-05-13 16:28:56 -04:00
Thomas Harte
dd63a6b61e
Correct all [A/S/N]BCD tests.
2022-05-13 16:18:58 -04:00
Thomas Harte
1935d968c5
Add ability to suggest solutions.
2022-05-13 15:27:11 -04:00
Thomas Harte
f83954f5b7
Switch to common bit-selection logic.
2022-05-13 15:08:15 -04:00
Thomas Harte
77b56c50e6
Ensure you can't trace into divide-by-zero, etc.
2022-05-13 14:02:56 -04:00
Thomas Harte
002a8c061f
Trim the public interface of Executor
.
2022-05-13 13:55:37 -04:00
Thomas Harte
4299334e24
Clean up some TODOs, eliminate one further conditional.
2022-05-13 11:17:57 -04:00
Thomas Harte
4d03c73222
Ensure that the first instruction of privilege/line1010/etc exceptions isn't traced.
2022-05-13 11:08:22 -04:00
Thomas Harte
84cfbaa0a4
Remove manual test count, now that all are being performed.
2022-05-13 11:00:26 -04:00
Thomas Harte
7a2fd93d08
Document BusHandler interface.
2022-05-13 10:59:36 -04:00
Thomas Harte
0d81992f6a
Move object creation.
2022-05-13 10:50:16 -04:00
Thomas Harte
5b67c9bf4a
MOVE to SR requires supervisor privileges.
2022-05-13 09:01:03 -04:00
Thomas Harte
6594b38567
Tidy up, and reduce for now to a summary report.
2022-05-13 08:02:20 -04:00
Thomas Harte
6c854e8ecc
Simplify is_supervisor
semantics.
2022-05-13 07:53:40 -04:00
Thomas Harte
2e796f31d4
Support interrupts; documentation to come.
2022-05-12 20:52:24 -04:00
Thomas Harte
3d8f5d4302
Improve failure logging.
...
This confirms that it's only the *BCDs and DIVU/DIVS in which I do not match the tests.
2022-05-12 20:23:32 -04:00
Thomas Harte
2fa6b2301b
Move string logic into Preinstruction
.
2022-05-12 19:46:08 -04:00
Thomas Harte
4ba20132b9
Avoid repeated allocations on the new path, reducing total runtime by almost two thirds.
2022-05-12 16:35:41 -04:00
Thomas Harte
a6e4d23c29
Tidy up primarily as per PatickvL's comments.
...
... though pulling the flag values out of an enum and into a namespace is entirely my own contribution, to keep them in their own namespace but having them overtly be ints.
2022-05-12 16:23:07 -04:00
Thomas Harte
6d43576db7
Remove errant semicolon.
2022-05-12 16:21:36 -04:00
Thomas Harte
b7d1bff0c7
Eliminate branches from ABCD.
2022-05-12 15:25:01 -04:00
Thomas Harte
79c5af755f
Eliminate branches from SBCD.
2022-05-12 15:18:03 -04:00
Thomas Harte
c6d84e7e60
Use Status::FlagT
pervasively.
2022-05-12 11:42:33 -04:00
Thomas Harte
192513656a
After much guesswork, fix SBCD and thereby pass flamewing tests.
2022-05-12 11:39:01 -04:00
Thomas Harte
41dc728c9b
Merge branch '68000Perform' of github.com:TomHarte/CLK into 68000Perform
2022-05-12 11:27:59 -04:00
Thomas Harte
f3c1b1f052
Name flags, remove closing underscores on exposed data fields.
2022-05-12 08:19:41 -04:00
Thomas Harte
bd61c72007
Mutate SBCD to correct values, though not yet statuses.
2022-05-12 07:22:26 -04:00
Thomas Harte
0efeea1294
Slightly improve SBCD. Not there yet though.
2022-05-12 07:07:21 -04:00
Thomas Harte
56ce1ec6e8
No need to subclass.
2022-05-11 21:25:38 -04:00
Thomas Harte
de168956e4
Fix tested operand order.
2022-05-11 16:44:39 -04:00
Thomas Harte
5b80844d81
Add a sanity test count, temporarily.
2022-05-11 16:34:28 -04:00
Thomas Harte
a9902fc817
Fix ABCD when the result has an invalid lower digit.
2022-05-11 16:31:27 -04:00
Thomas Harte
ed75688251
Fix capture of the initial zero flag.
2022-05-11 15:40:17 -04:00
Thomas Harte
17add4b585
Introduce and overwhelmingly fail the flamewing BCD tests.
2022-05-11 15:19:39 -04:00
Thomas Harte
d492156453
Add noreturn
attribute as a warning.
2022-05-11 10:51:48 -04:00
Thomas Harte
96af3d5ec5
Fix infinite inner/outer loop.
2022-05-11 10:26:12 -04:00
Thomas Harte
69ba14e34e
Support the trace flag.
2022-05-11 09:39:15 -04:00
Thomas Harte
943c924382
Add missing: MOVE to/from USP, RESET.
2022-05-11 07:52:23 -04:00
Thomas Harte
4b97427937
Remove further magic constants.
2022-05-11 07:00:35 -04:00
Thomas Harte
ab8e1fdcbf
Take a swing at access faults and address errors.
2022-05-10 16:20:30 -04:00
Thomas Harte
477979c275
Fully formulate and document the flow controller.
2022-05-10 10:34:07 -04:00
Thomas Harte
c635720a09
Tidy up; provide a notification for bit-change operations.
2022-05-10 08:23:25 -04:00
Thomas Harte
f2a6a12f79
Remove further vestiges of timing.
2022-05-09 20:58:51 -04:00
Thomas Harte
7445c617bc
Start removing 68000-specific timing calculations.
2022-05-09 20:32:02 -04:00
Thomas Harte
8e7340860e
Minor thematic rearrangement.
2022-05-09 16:35:17 -04:00
Thomas Harte
2ca1eb4cf8
Move set_pc
into the operation-specific group.
2022-05-09 16:20:15 -04:00
Thomas Harte
0af8660181
Remove add_pc
and decline_branch
in favour of operation-specific signals.
2022-05-09 16:19:25 -04:00
Thomas Harte
330ec1b848
TODO is done.
2022-05-09 11:52:33 -04:00
Thomas Harte
2f7cff84d9
Enable missing rotates and shifts.
2022-05-09 11:26:01 -04:00
Thomas Harte
8e5650fde9
Clean up Instruction.hpp.
2022-05-09 10:13:42 -04:00
Thomas Harte
539932dc56
Provide function codes. TODO: optionally.
2022-05-09 09:18:02 -04:00
Thomas Harte
5ab5e1270e
Fix test for new MOVEM semantics.
2022-05-09 09:17:48 -04:00
Thomas Harte
e35de357fa
Route reads and writes through a common path.
2022-05-08 17:17:46 -04:00
Thomas Harte
0818fd7828
Ensure no status updates fall through the cracks.
2022-05-07 21:29:12 -04:00
Thomas Harte
98cb9cc1eb
Fix CHK operand size.
2022-05-07 21:16:44 -04:00
Thomas Harte
bf8c97abbb
Permit TRAP, TRAPV and CHK to push the next PC rather than the current.
2022-05-07 20:32:39 -04:00
Thomas Harte
ad6cf5e401
Pull out magic constant, simplify sp
and TAS
.
2022-05-07 20:20:24 -04:00
Thomas Harte
2b3900fd14
Fix LINK A7.
2022-05-07 08:15:26 -04:00
Thomas Harte
1defeca1ad
Implement RTS, RTR, RTE.
2022-05-06 12:30:49 -04:00
Thomas Harte
ac6a9ab631
Fix TAS Dn.
2022-05-06 12:23:04 -04:00
Thomas Harte
8176bb6f79
Expose issues with TST and TAS.
2022-05-06 12:18:56 -04:00
Thomas Harte
9c266d4316
Proceed to unimplemented TST.
2022-05-06 11:33:57 -04:00
Thomas Harte
d478a1b448
Proceed to next failure: PEA.
2022-05-06 10:04:20 -04:00
Thomas Harte
190a351a29
Fix address writeback.
2022-05-06 09:56:01 -04:00
Thomas Harte
607ddd2f78
Preserve MOVEM order in Operation
.
2022-05-06 09:45:06 -04:00
Thomas Harte
fed79a116f
Be overt about the size being described here.
2022-05-06 09:22:38 -04:00
Thomas Harte
5db0ea0236
Add note for my tomorrow self.
2022-05-05 21:11:02 -04:00
Thomas Harte
06fe320cc0
Correct source counting, but this leaves the operands still being the wrong way around.
2022-05-05 21:06:53 -04:00
Thomas Harte
f7991e18de
Makes a failed attempt to implement MOVEM to registers.
2022-05-05 20:32:21 -04:00
Thomas Harte
d7d0a5c15e
Implement MOVEM to memory.
2022-05-05 18:51:29 -04:00
Thomas Harte
47f4bbeec6
Switch to a contiguous block of 16 registers.
2022-05-05 15:31:59 -04:00
Thomas Harte
9ab70b340c
Route MOVEM appropriately.
2022-05-05 12:42:57 -04:00
Thomas Harte
70cdc2ca9f
Fix MOVEP to register.
...
Advance to lack of MOVEM.
2022-05-05 12:37:47 -04:00
Thomas Harte
f63a872387
BTST does not write back.
2022-05-05 12:32:15 -04:00
Thomas Harte
67462c2f92
Rewire MOVEP.
2022-05-05 12:27:36 -04:00
Thomas Harte
4a4e786060
Hit a realisation: write-back isn't going to work with MOVEP as formulated.
2022-05-05 09:26:26 -04:00
Thomas Harte
665f2d4c00
Attempts MOVEP.
2022-05-05 09:00:33 -04:00
Thomas Harte
64586ca7ba
Implement BTST/etc.
2022-05-04 20:57:22 -04:00
Thomas Harte
46686b4b9c
Start testing move.
2022-05-04 20:38:56 -04:00
Thomas Harte
15c90e546f
Fix rotates and shifts to memory.
2022-05-04 19:44:59 -04:00
Thomas Harte
5aabe01b6d
Mostly fix LINK and UNLK.
2022-05-04 08:41:55 -04:00
Thomas Harte
5d1d94848c
Take a bash at LINK and UNLK.
2022-05-04 08:26:11 -04:00
Thomas Harte
7d10976e08
Add LINK and UNLINK to operand_flags
.
2022-05-03 20:51:02 -04:00
Thomas Harte
d3b55a74a5
Fix LEA, proceed to non-functional LINK and UNLK.
2022-05-03 20:45:36 -04:00
Thomas Harte
de58ec71fd
Fix EXT, SWAP.
2022-05-03 20:17:36 -04:00
Thomas Harte
052ba80fd7
Add enough wiring to complete but fail EXT and JMP/JSR.
2022-05-03 15:49:55 -04:00
Thomas Harte
39f0ec7536
Get far enough through CHK to realise that MOVEM probably needs to be divided by direction.
2022-05-03 15:40:04 -04:00
Thomas Harte
af973138df
Correct decoding of Bcc.b, satisfying Bcc and BSR tests.
2022-05-03 15:32:54 -04:00
Thomas Harte
5a87506f3d
Fix Bcc, making decision that add_pc
is relative to start of instruction.
2022-05-03 15:21:42 -04:00
Thomas Harte
90f0005cf2
Proceed to failing Bcc and flagging up my lack of an implementation for BSR.
2022-05-03 14:45:49 -04:00
Thomas Harte
d8b3748d24
Fix Scc size, DBcc behaviour.
2022-05-03 14:40:51 -04:00
Thomas Harte
1b224c961e
Fix Scc, add operand flags for DBcc.
2022-05-03 14:23:57 -04:00
Thomas Harte
b6ffff5bbd
Distinguish [ADD/SUB]QA from [ADD/SUB]Q.
2022-05-03 14:17:26 -04:00
Thomas Harte
5ebae85a16
Start recording successes.
2022-05-03 11:28:50 -04:00
Thomas Harte
b3cf13775b
Consume operand_flags into Instruction.hpp.
2022-05-03 11:09:57 -04:00
Thomas Harte
c61809f0c4
Add CMPAl
.
2022-05-03 09:20:02 -04:00
Thomas Harte
2f2d6bc08b
Correct CMPw.
2022-05-03 09:05:34 -04:00
Thomas Harte
1bb809098c
Switch — messily — to a more compact way of indicating sequence.
2022-05-03 09:04:54 -04:00
Thomas Harte
17a2ce0464
Fix missung #undefs.
2022-05-02 21:29:46 -04:00
Thomas Harte
011506f00d
Add basic exceptions.
2022-05-02 21:27:58 -04:00
Thomas Harte
25ab478461
Fix immediate byte and word fetches.
2022-05-02 20:17:44 -04:00
Thomas Harte
fc9a35dd04
Test add/sub, add an exception for invalid Sequence
s.
2022-05-02 20:09:38 -04:00
Thomas Harte
7efe30f34c
Fix (d8, _, Xn) calculation.
2022-05-02 15:09:59 -04:00
Thomas Harte
ef28d5512b
Annotate further.
2022-05-02 12:58:04 -04:00
Thomas Harte
3827ecd6d3
Proceed to complete test running.
2022-05-02 12:57:45 -04:00
Thomas Harte
fa49737538
Correct processor name.
2022-05-02 08:40:47 -04:00
Thomas Harte
14532867a4
Sneaks towards testing EXT.
2022-05-02 08:00:56 -04:00
Thomas Harte
73f340586d
Proceed to building, but failing tests.
2022-05-02 07:45:07 -04:00
Thomas Harte
56fe00c5fb
Correct errors preparatory to Executor's lack of flow controller actions.
2022-05-01 20:40:57 -04:00
Thomas Harte
3c26177239
Provide both compile- and run-time operation selection options.
2022-05-01 17:39:56 -04:00
Thomas Harte
fe8f0d960d
Equivocate.
...
(Specifically: addresses cannot generally be obtained in advance, as they are often the product of registers, but things like displacements, immediate values and absolute addresses can)
2022-05-01 15:30:03 -04:00
Thomas Harte
c72caef4fd
Correct further size specifiers.
2022-05-01 15:21:58 -04:00
Thomas Harte
0720a391e8
Correct address register mutations.
2022-05-01 15:18:06 -04:00
Thomas Harte
d16ac70a50
Correct include path.
2022-05-01 15:14:12 -04:00
Thomas Harte
fc8e020436
Improve field name.
2022-05-01 15:12:13 -04:00
Thomas Harte
6b073c6067
Attempt to round out addressing modes, shift to a header, as per templating on BusHandler.
2022-05-01 15:10:54 -04:00
Thomas Harte
0b19bbff8d
Marginally refactor, to avoid repetition of read/write branch.
2022-05-01 13:09:28 -04:00
Thomas Harte
42927c1e32
Establish more of the 680x0 executor loop.
2022-05-01 13:00:20 -04:00
Thomas Harte
df999978f1
Figure out what the call to perform
should look like.
...
Albeit that this class doesn't currently offer any of the proper flow control actions.
2022-04-30 20:34:44 -04:00
Thomas Harte
43cd740a7b
Shuffle Step
to give meaning to the LSB.
2022-04-30 20:33:35 -04:00
Thomas Harte
52f355db24
Decision: operation is not a template parameter. Hence can use condition as fully typed.
2022-04-30 14:08:51 -04:00
Thomas Harte
a86c5ccdc9
Merge branch '68000Perform' of github.com:TomHarte/CLK into 68000Perform
2022-04-30 14:02:23 -04:00
Thomas Harte
e532562108
Merge branch 'master' into 68000Perform
2022-04-30 14:02:17 -04:00
Thomas Harte
4293ab2acb
Merge pull request #1030 from TomHarte/68000cc
...
Include decoded condition in Preinstruction.
2022-04-30 13:56:49 -04:00
Thomas Harte
8d24c00df2
Include decoded condition in Preinstruction.
2022-04-30 09:00:47 -04:00
Thomas Harte
f4074e0bba
Add basic status.
2022-04-30 08:38:28 -04:00
Thomas Harte
e4426dc952
Introduce calculate EA steps.
2022-04-29 20:30:48 -04:00
Thomas Harte
9359f6477b
Start drafting an Executor.
2022-04-29 17:12:06 -04:00
Thomas Harte
a103f30d51
Attempt to game out LEA, PEA. Add various special MOVEs.
2022-04-29 14:43:58 -04:00
Thomas Harte
78b60dbd1a
Evict MOVEM and MOVEP, enable TRAP and TRAPV, complete CHK.
2022-04-29 14:43:30 -04:00
Thomas Harte
cde75a1c00
Make steps more visible.
2022-04-29 11:26:39 -04:00
Thomas Harte
b9d243552c
MOVEs don't read from operand 2.
2022-04-29 11:22:06 -04:00
Thomas Harte
85242ba896
Add to Xcode project, template on Model as per CLR being odd. Fill in some obvious answers.
2022-04-29 11:10:14 -04:00
Thomas Harte
d16dab6f62
Starts introducing a sequencer, to resolve responsibility of perform
.
2022-04-29 10:40:19 -04:00
Thomas Harte
8066b19f93
Correct typos.
2022-04-29 07:57:02 -04:00
Thomas Harte
abd2a831a3
Added a further ambiguity.
2022-04-29 05:08:44 -04:00
Thomas Harte
824d3ae3f7
Conclusion: a union does produce better code.
...
(But needn't be so verbose)
2022-04-29 04:51:02 -04:00
Thomas Harte
727a14c6f9
Add notes for myself on decisions yet to make.
2022-04-29 03:53:17 -04:00
Thomas Harte
13d20137d3
Tackle two lingering references to exception_handler.
2022-04-29 03:38:23 -04:00
Thomas Harte
9680566595
Include in automated build, temporarily.
2022-04-28 20:42:44 -04:00
Thomas Harte
33c9ea2cf7
A flow controller feels more natural than an exception handler.
2022-04-28 20:42:04 -04:00
Thomas Harte
1d8d2b373b
Port all simple instruction bodies.
2022-04-28 16:55:47 -04:00
Thomas Harte
611b472b12
Add evaluate_condition
, to check standard 68000 condition codes.
2022-04-28 16:54:57 -04:00
Thomas Harte
bb73eb0db3
Start working on an isolation of 68000 instruction execution.
2022-04-28 15:35:40 -04:00
Thomas Harte
8a18685902
Relocated RegisterSizes to Numeric.
2022-04-28 15:10:08 -04:00
Thomas Harte
872b941b20
Merge pull request #1027 from TomHarte/GCCWarnings
...
Resolve GCC compilation warnings.
2022-04-27 20:00:38 -04:00
Thomas Harte
39261436c8
Remove unused type alias.
2022-04-27 19:53:32 -04:00
Thomas Harte
5e355383df
Correct SIB test.
2022-04-27 19:53:15 -04:00
Thomas Harte
90bfec8c04
Merge pull request #1026 from TomHarte/FarewellOfft
...
Eliminate `off_t`.
2022-04-27 19:29:10 -04:00
Thomas Harte
866b6c6129
Eliminate off_t
.
2022-04-27 19:16:37 -04:00
Thomas Harte
649fe7a1ec
Merge pull request #1021 from TomHarte/68kDecoder
...
Establishes a formal 68k [pre-]decoder.
2022-04-27 08:14:24 -04:00
Thomas Harte
9cbbb6e508
Adjust path to match namespace; add to Qt project.
2022-04-27 08:05:36 -04:00
Thomas Harte
9908769bb3
Normalise test name.
2022-04-26 20:32:39 -04:00
Thomas Harte
8902bb1af0
Include size and supervisor flag in Preinstruction.
2022-04-26 19:44:02 -04:00
Thomas Harte
baf1bd354d
Avoid packing/unpacking of operands.
2022-04-26 19:37:07 -04:00
Thomas Harte
539c2985aa
Fill in size table, define quick
to return a uint32_t
.
2022-04-26 12:30:14 -04:00
Thomas Harte
5c356e15b5
Completes requires_supervisor
.
2022-04-25 20:05:45 -04:00
Thomas Harte
8ff0b71b29
Subsume MOVEQ into MOVE.l; add missing invalid_operands.
2022-04-25 19:58:19 -04:00
Thomas Harte
4e5a6c89b9
Merge pull request #1025 from TomHarte/AndValidate
...
Switch to validation via a simple AND mask.
2022-04-25 16:29:23 -04:00
Thomas Harte
8f8f201186
Complete transition to simple AND-based verification.
2022-04-25 16:23:16 -04:00
Thomas Harte
0c688757b0
Adapt the last of the MOVEs, TAS, NOT, SUB and TST.
2022-04-25 16:05:44 -04:00
Thomas Harte
5778e92e70
Adapt MOVE, DIV, MUL, OR.
2022-04-25 15:43:25 -04:00
Thomas Harte
3268ea42ff
Translate SUB, PEA.
2022-04-25 12:41:41 -04:00
Thomas Harte
1538500903
Add enough to make AND masks the default case.
2022-04-25 12:30:44 -04:00
Thomas Harte
6ca30a16ca
Update JMP, JSR.
2022-04-25 12:05:07 -04:00
Thomas Harte
e6dc2e0d31
Add EXG, EXT.
2022-04-25 11:49:14 -04:00
Thomas Harte
9bbd1390c1
Add new-style validation of EORI to CCR, move EXG decoding into page navigation.
2022-04-25 11:43:30 -04:00
Thomas Harte
27f8db6e8b
Update DBcc, DIVU/DIVS, EOR.
2022-04-25 09:49:18 -04:00
Thomas Harte
dda0c0e097
Update CMPM, CMPI.
2022-04-25 09:39:22 -04:00
Thomas Harte
f5ea5c26a3
Translate CHK, CLR, CMP, CMPA.
2022-04-24 21:05:00 -04:00
Thomas Harte
d01fa96177
Port BSR, BTST.
2022-04-24 20:49:41 -04:00
Thomas Harte
03caa53863
Translate BSET.
2022-04-24 19:58:10 -04:00
Thomas Harte
4f4a2e6d92
Translate ASL, ASR, Bcc, BCHG, BCLR.
2022-04-24 19:53:54 -04:00
Thomas Harte
87178ed725
Port AND.
2022-04-24 15:12:18 -04:00
Thomas Harte
94e5436f6e
Attempt a more compact retelling.
2022-04-24 14:47:14 -04:00
Thomas Harte
b965f2053a
Start experimenting with a simple AND for operand validation.
2022-04-24 10:43:06 -04:00
Thomas Harte
959db77b88
Eliminate concept of skips.
2022-04-22 20:59:25 -04:00
Thomas Harte
edee078f0a
Eliminate last set of failures.
2022-04-22 20:57:45 -04:00
Thomas Harte
d4b766bf3f
Introduce directional ADD/SUB/AND/OR.
...
Just 512 failures to go.
2022-04-22 20:37:09 -04:00
Thomas Harte
72772c9a83
Remove branch from combined_mode
.
...
On x86 it was probably only a conditional move, but this is fine.
2022-04-22 15:11:41 -04:00
Thomas Harte
4c806d7c51
Tidy up slightly, ahead of a final push to getting complete test success.
...
After which I can start undoing style errors.
2022-04-22 14:51:25 -04:00
Thomas Harte
c16a60c5ea
Import correct STOP, LINK, EXT.
2022-04-22 14:36:29 -04:00
Thomas Harte
96afcb7a43
Introduce remainder of tests.
2022-04-22 14:33:43 -04:00
Thomas Harte
e5a8d8b9ad
Import corrected TRAPs and RTE/RTR.
2022-04-22 14:26:44 -04:00
Thomas Harte
efeee5160e
Add tests for RTE, RTR, TRAP, TRAPV, CHK.
2022-04-22 10:06:39 -04:00
Thomas Harte
06fb502047
Add MUL/DIV tests and exclusions.
2022-04-22 09:47:16 -04:00
Thomas Harte
977192f480
Resolve D-page decoding errors.
...
In particular: that I'd overlooked CMPM, and was treating NOT as two-operand.
2022-04-22 09:24:16 -04:00
Thomas Harte
cf66d9d38d
Add failing tests for EOR, NOT, OR; disambiguate EOR vs CMP.
2022-04-21 20:36:04 -04:00
Thomas Harte
25eeff8fc5
Correct CMP decoding, correct AND as far as asymmetry of Dn, Dn.
2022-04-21 20:14:52 -04:00
Thomas Harte
d342cdad2b
Import corrected MOVEPs.
2022-04-21 19:04:14 -04:00
Thomas Harte
c899ee0d55
Enable MOVEP tests.
2022-04-21 18:57:47 -04:00
Thomas Harte
220408fcaa
Introduce MOVEM tests.
...
12662 opcodes to go.
2022-04-21 16:39:17 -04:00
Thomas Harte
f4e99be7e1
Import BSRs, corrected MOVEMs.
2022-04-21 16:35:24 -04:00
Thomas Harte
bf9fc0ae96
Correct decoding of BSR.
2022-04-21 16:24:34 -04:00
Thomas Harte
9697e666b7
With a shift to MOVE.q, all tests now pass again.
...
12802 opcodes now untested.
2022-04-21 16:16:34 -04:00
Thomas Harte
a8a1a74b79
Correct BSRb quick value.
2022-04-21 16:13:06 -04:00
Thomas Harte
216ca7cbc9
Import BCC/BSR/BRA quick values.
2022-04-21 16:11:29 -04:00
Thomas Harte
549e440f7c
Add 'quick' decoding and testing.
2022-04-21 16:05:00 -04:00
Thomas Harte
45c02c31f8
Add MOVEM exclusions.
2022-04-21 15:47:34 -04:00
Thomas Harte
b6b092d124
Add tests, exclusions for rest of shift/roll group.
2022-04-21 11:26:56 -04:00
Thomas Harte
d346d4a9b6
Import updated quick values.
2022-04-21 09:59:04 -04:00
Thomas Harte
c84e98774a
Import corrected register ASL/etcs.
2022-04-21 09:51:21 -04:00
Thomas Harte
e1f4187430
Introduce failing ASL test.
2022-04-20 20:22:56 -04:00
Thomas Harte
3af93ada6f
Test and correct Bcc, BSR, CLR, NEGX, NEG.
2022-04-20 20:19:56 -04:00
Thomas Harte
fa4dee8cfd
Import two-operand DBccs.
2022-04-20 20:07:20 -04:00
Thomas Harte
3888492f0d
Import corrected DBccs and JSRs.
2022-04-20 19:57:54 -04:00
Thomas Harte
dc16928f74
Add appropriate exclusions for JSR, JMP, Scc.
2022-04-20 16:56:26 -04:00
Thomas Harte
a4e440527b
Import corrected CMPA references.
2022-04-20 16:46:05 -04:00
Thomas Harte
80ff146620
Add CMP, CMPA and TST tests and exclusions.
2022-04-20 16:29:45 -04:00
Thomas Harte
d4fe9d8166
Complete BTST/etc exclusions.
2022-04-20 16:16:24 -04:00
Thomas Harte
85a0af03c1
Import more standard JSON; start validating.
2022-04-20 09:17:00 -04:00
Thomas Harte
dc43f5605b
Give MOVEPs precedence.
2022-04-20 08:40:56 -04:00
Thomas Harte
e0d2baae58
Test ANDI/ORI/EORI SR/CCR, and fail BTST/BCLR/BCHG/BSET.
2022-04-20 08:39:43 -04:00
Thomas Harte
437de19ecb
Correct MOVE USP entries.
2022-04-20 08:34:10 -04:00
Thomas Harte
fab064641f
Add Move[to/from][SR/CCR/USP] tests, correct decodings.
2022-04-20 07:59:13 -04:00
Thomas Harte
cc69d01bdc
Strip dead code.
2022-04-19 20:41:39 -04:00
Thomas Harte
461a95d7ff
Introduce missing register numbers for PEA, and elsewhere.
2022-04-19 20:39:01 -04:00
Thomas Harte
316e9681cc
Weed out false PEAs.
2022-04-19 20:34:08 -04:00
Thomas Harte
4181313cc6
Correct decoding of SWAP.
2022-04-19 20:28:00 -04:00
Thomas Harte
aa1665acce
Fix LEA transcription problems.
2022-04-19 20:24:03 -04:00
Thomas Harte
6aabc5e7b0
Test LEA, PEA, add name for MOVEq.
2022-04-19 19:45:51 -04:00
Thomas Harte
343a8e0192
Resolve wrong-headed mapping of LEA to MOVEAl.
2022-04-19 19:36:21 -04:00
Thomas Harte
2707887a65
Indicate MOVEAs.
2022-04-19 17:17:19 -04:00
Thomas Harte
ef87d09cfa
Clear up MOVEs, fail on MOVEAs.
2022-04-19 17:13:23 -04:00
Thomas Harte
d21c67f237
Don't permit byte move from address register.
2022-04-19 16:49:26 -04:00
Thomas Harte
de0432b317
Include register numbers in MOVEs.
2022-04-19 16:34:22 -04:00
Thomas Harte
de40fed248
Test MOVEs and add operand validation.
2022-04-19 16:31:03 -04:00
Thomas Harte
76d7e0e1f8
Test and correct SUBs.
2022-04-19 16:27:20 -04:00
Thomas Harte
bfa551ec08
Correct ADDX and SUBX listings.
2022-04-19 16:21:40 -04:00
Thomas Harte
740e564bc7
Improve validation, add all ADDs.
...
It now looks like probably the ADDXs in the JSON are incorrect.
2022-04-19 14:45:15 -04:00
Thomas Harte
1f585d67b6
ADDA: correct decoding, add validation.
2022-04-19 14:43:01 -04:00
Thomas Harte
5b22e94a4b
Map invalid reg+mode combinations to AddressingMode::None; add validation of ADDs and decoding of ADDX.
2022-04-19 14:36:36 -04:00
Thomas Harte
7749aef6b6
Improve const correctness.
2022-04-19 14:35:40 -04:00
Thomas Harte
5de8fb0d08
Disallow four illegal NBCD addressing modes.
2022-04-19 09:59:02 -04:00
Thomas Harte
19f7335926
Add post validation step.
2022-04-19 09:44:02 -04:00
Thomas Harte
9b61830a55
Add ADD.b as a note to self that .q decoding is also required.
2022-04-19 08:44:44 -04:00
Thomas Harte
99f4cd867d
Decode the two EXTs.
2022-04-19 08:42:17 -04:00
Thomas Harte
f29fec33a2
Eliminate mismatches due to unsupported addressing modes.
2022-04-19 08:37:53 -04:00
Thomas Harte
93fe3459fd
The quick value won't always fit in reg; turf the problem elsewhere.
2022-04-19 08:37:35 -04:00
Thomas Harte
1abd3bd7f3
Decode SWAP.
2022-04-19 08:37:13 -04:00
Thomas Harte
5509f20025
Fix MOVEfrom/toSR and NBCD listings.
2022-04-19 08:07:34 -04:00
Thomas Harte
fc4fd41be4
Reorder from most specific to least.
2022-04-19 08:00:52 -04:00
Thomas Harte
3ffca20001
Uncover various discrepancies with NBCD.
2022-04-19 07:15:54 -04:00
Thomas Harte
7c29305788
Test all ABCDs.
2022-04-18 20:00:39 -04:00
Thomas Harte
41fb18e573
Add 68k decoder to SDL build.
...
... and therefore to automated compilation testing.
2022-04-18 14:43:41 -04:00
Thomas Harte
e4c6251ef5
Express the BSR/Bcc.l test properly.
2022-04-18 14:42:31 -04:00
Thomas Harte
7aa250eaf7
Advances to hitting the same absent/present mapping as the old decoder.
2022-04-18 14:41:26 -04:00
Thomas Harte
ff380b686a
Decode MOVEq.
2022-04-18 09:12:45 -04:00
Thomas Harte
d2452f4b68
Fix SUBQ ExtendedOperation mappings.
2022-04-18 09:08:49 -04:00
Thomas Harte
deb9c32a38
Add missing Sccs.
2022-04-18 09:04:17 -04:00
Thomas Harte
440f45b996
Attempt decoding and disambiguation of Scc, DBcc, Bcc and BSR.
2022-04-18 08:55:46 -04:00
Thomas Harte
7d64c4ec66
Add STOP.
2022-04-18 08:29:10 -04:00
Thomas Harte
7fe0d530c1
Add a decoder for TRAP.
2022-04-18 08:05:33 -04:00
Thomas Harte
c944767554
Better document decoding patterns, add LEA and CHK.
2022-04-18 08:00:43 -04:00
Thomas Harte
fde5a1c507
Ensure ADDI, SUBI, etc, provide an operation.
2022-04-18 07:42:30 -04:00
Thomas Harte
0fbfb41fa8
Expand on none-matching text.
2022-04-18 07:42:14 -04:00
Thomas Harte
1991ed0804
Introduce failing [partial-]test of new 68000 decoder.
2022-04-18 07:23:25 -04:00
Thomas Harte
e782b92a80
Add exposition.
2022-04-17 19:56:39 -04:00
Thomas Harte
07635ea2be
Add register names, Q values.
2022-04-17 19:46:21 -04:00
Thomas Harte
fb3de9ce9d
Merge pull request #1023 from TomHarte/AppleIIAutostart
...
Undo bad guess at initial switch state.
2022-04-17 17:07:56 -04:00
Thomas Harte
efff91ea3d
Undo bad guess at initial switch state.
2022-04-17 17:03:05 -04:00
Thomas Harte
1916bd3bd0
Import a first effort at listing all 68000 instruction specs.
2022-04-17 07:57:59 -04:00
Thomas Harte
4eb752b000
Even out tabs.
2022-04-15 20:41:39 -04:00
Thomas Harte
bfb29a58f3
Take another crack at neatness; make LEA overt.
2022-04-15 20:33:59 -04:00
Thomas Harte
f86e455a87
Advance permissively through the 4xxx page to LEA.
2022-04-15 16:01:33 -04:00
Thomas Harte
faa35fe9fc
Decode MOVE and the fixed 0x4xxx set.
2022-04-15 15:40:31 -04:00
Thomas Harte
89b8b59658
Ostensibly completes the 0 line.
2022-04-15 15:33:54 -04:00
Thomas Harte
de55a1adc4
Require a model for decoding; shift a bunch of immediates into ExtendedOperation.
2022-04-15 09:40:37 -04:00
Thomas Harte
d1613025ee
For now, assume the .q actions can be handled inside Preinstruction.
2022-04-13 09:29:12 -04:00
Thomas Harte
cc4431c409
Expand decode to accept a wider array of operations, and then funnel them down.
2022-04-12 16:17:30 -04:00
Thomas Harte
3d5986c55d
Some minor style changes, plus I think I've talked myself into an expanded Operation-tracking enum. Probably.
2022-04-12 14:54:11 -04:00
Thomas Harte
9aeb6ee532
Formally prepare for one- and two-operand instructions.
2022-04-12 09:14:46 -04:00
Thomas Harte
e7f6cc598d
Make first attempt to complete broad phase of decoding.
2022-04-12 09:08:46 -04:00
Thomas Harte
cd465dd121
Decode page E.
2022-04-12 09:04:40 -04:00
Thomas Harte
174b48a14a
Populate lines 9 and D.
2022-04-12 08:57:40 -04:00
Thomas Harte
bca18e7aba
Fill in line decoders for 5, 6 and 7.
...
This leaves 9, D and E to go.
2022-04-12 08:44:32 -04:00
Thomas Harte
17e761d6c6
Add enough code to pages 0–3 to shift problem to decode().
2022-04-12 08:36:44 -04:00
Thomas Harte
c50556dde4
Create empty line decoders.
2022-04-12 08:16:29 -04:00
Thomas Harte
dd5bdd67d7
Add B page and a large chunk of 4.
2022-04-12 07:49:08 -04:00
Thomas Harte
21ac9363e9
Add page 8.
2022-04-11 16:32:57 -04:00
Thomas Harte
8e3cccf4d6
Begins a formalised 68k decoder.
2022-04-11 15:00:55 -04:00
Thomas Harte
945e935312
Merge pull request #1020 from TomHarte/RotateMask
...
Improve PowerPC rotate mask generation.
2022-04-10 15:24:17 -04:00
Thomas Harte
bb5cf570e5
Remove conditional, make generic enough for both 32- and 64-bit operation.
2022-04-10 15:18:23 -04:00
Thomas Harte
a5ed288db2
Merge pull request #1018 from TomHarte/PowerPCTests
...
Import Dingusdev PowerPC tests
2022-04-10 09:45:39 -04:00
Thomas Harte
7002d6d306
Improve accuracy of comment.
2022-04-10 09:37:18 -04:00
Thomas Harte
1b8d8f3a04
Default to 32-bit versions.
2022-04-10 09:35:58 -04:00
Thomas Harte
284440336d
Correct rotate_mask().
2022-04-10 09:31:39 -04:00
Thomas Harte
140ae7a513
Clarify template parameters.
2022-04-10 08:57:09 -04:00
Thomas Harte
21328d9e37
Normalise macros, remove unused AssertEqualOperationNameO.
2022-04-09 21:25:00 -04:00
Thomas Harte
5177fe1db7
Update tests.
2022-04-09 21:11:58 -04:00
Thomas Harte
7de50b5e2e
Provide 64-bit me, mb and sh. Add direct getter for rotate masks.
2022-04-09 21:08:01 -04:00
Thomas Harte
4652a84b43
Add exposition.
2022-04-09 19:20:13 -04:00
Thomas Harte
9e0755bc86
Introduce overlooked: ld, ldu, rldclx, rldcrx, rldicx, rldiclx, rldicrx, rldimix.
2022-04-09 18:28:51 -04:00
Thomas Harte
da0f7d7907
Rearrange into alphabetical order.
2022-04-09 10:20:03 -04:00
Thomas Harte
88d72bf31d
Fill in more mnemonics.
2022-04-08 10:01:52 -04:00
Thomas Harte
aac2f7dd73
Add missing validations.
2022-04-08 09:47:04 -04:00
Thomas Harte
1f44ad1723
Completes test cases.
2022-04-06 21:09:58 -04:00
Thomas Harte
4ab1857a11
Complete MPC601 commentary.
2022-04-06 20:53:44 -04:00
Thomas Harte
d23c714ec7
Build in an optional post hoc validation.
...
TODO: validate.
2022-04-05 11:23:54 -04:00
Thomas Harte
ac524532e7
Handle the synonym test cases.
2022-04-04 08:09:59 -04:00
Thomas Harte
59a1fde2a1
Fix is_zero_mask.
2022-04-03 20:37:09 -04:00
Thomas Harte
31276de5c3
Complete 'misc instructions' tests.
2022-04-03 20:33:32 -04:00
Thomas Harte
c581aef11d
Test as far as mffs.
2022-04-03 18:29:40 -04:00
Thomas Harte
7f6a955a71
Complete the cmp set.
2022-04-03 15:50:03 -04:00
Thomas Harte
125d97cc41
Complete floating point tests.
2022-04-03 08:55:28 -04:00
Thomas Harte
de7d9ba471
Add further floating point tests.
2022-04-03 08:06:59 -04:00
Thomas Harte
ad54b44235
Begin documentation and testing of the floating point instructions.
2022-04-02 19:58:21 -04:00
Thomas Harte
42532ec0f5
Test floating point loads and stores.
2022-04-02 15:40:17 -04:00
Thomas Harte
b84fa619da
Test integer loads and stores.
2022-04-02 15:27:12 -04:00
Thomas Harte
8a1409184f
Add decoding of lwa.
2022-04-02 10:31:55 -04:00
Thomas Harte
8a3c16a5bc
Add lwa.
2022-04-02 10:26:47 -04:00
Thomas Harte
6343c65ce2
Document further; mftb is optional.
2022-04-02 10:09:58 -04:00
Thomas Harte
20b4736a1f
Test tw, twi.
2022-04-02 10:09:35 -04:00
Thomas Harte
d5967f7834
Correct decoding of stwcx. and stdcx.
2022-04-01 20:37:36 -04:00
Thomas Harte
d5f7650ac1
Test synchronising loads and stores, further expand documentation.
2022-04-01 18:30:48 -04:00
Thomas Harte
6330caffde
Test logical immediates.
2022-04-01 17:52:38 -04:00
Thomas Harte
8f580c256c
Remove explanations; saying nothing is better than giving incomplete advice.
2022-04-01 17:49:34 -04:00
Thomas Harte
4671b8db5c
Add tests for non-immediate logicals.
2022-04-01 17:35:47 -04:00
Thomas Harte
7c8f044380
Complete shift tests.
2022-04-01 17:22:32 -04:00
Thomas Harte
8efd506471
Transcribe up to the end of 'e', use extswx
and remove extsw
.
2022-04-01 17:11:57 -04:00
Thomas Harte
e83267751e
Start shuffling parameters into conventional order; expand on cmp–cmpli, dcbf–dcbz.
2022-03-30 20:36:46 -04:00
Thomas Harte
a3b110aee5
Clean up. Shifts next.
2022-03-30 17:04:41 -04:00
Thomas Harte
84f0b0a84c
Test rotates.
2022-03-30 16:43:09 -04:00
Thomas Harte
c9c5adc650
Test crand ... crxor.
2022-03-30 12:40:57 -04:00
Thomas Harte
52e7226655
Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests
2022-03-29 20:50:40 -04:00
Thomas Harte
b89c8decd4
Test addx–divwx and mtcrf; document fields for crand, etc.
2022-03-29 20:48:43 -04:00
Thomas Harte
d783975597
Start offering a list of relevant fields per Operation.
2022-03-29 19:59:21 -04:00
Thomas Harte
5ec291df5c
Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests
2022-03-29 14:38:28 -04:00
Thomas Harte
0a45355055
Add a few more field comments.
2022-03-29 14:37:21 -04:00
Thomas Harte
e696624da0
Now passes negx, subfex, subfzex, subfmex, dozx, absx, nabsx.
2022-03-28 20:47:32 -04:00
Thomas Harte
99ad40f3e0
Test subfcx, subfx; correct decoding of oe().
2022-03-28 20:39:52 -04:00
Thomas Harte
b9c8016aca
Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests
2022-03-28 20:20:59 -04:00
Thomas Harte
8ad1f2d4f5
Add bad attempt to catch subfc.
2022-03-28 20:18:41 -04:00
Thomas Harte
dc30581be0
Fix typo; . -> ,
2022-03-28 16:39:55 -04:00
Thomas Harte
2e56b606fa
Improve file division, document some further operations.
2022-03-27 18:44:56 -04:00
Thomas Harte
d84c72afe5
Test loads and stores, and immediate arithmetic.
2022-03-27 08:47:01 -04:00
Thomas Harte
2d69896f64
Merge branch 'master' into PowerPCTests
2022-03-26 10:12:15 -04:00
Thomas Harte
b3dd2db815
Merge pull request #1017 from TomHarte/CPC128k
...
CPC: ensure 64/128k RAM is properly selected.
2022-03-26 09:08:40 -04:00
Thomas Harte
290dd3993b
CPC: ensure 64/128k RAM is properly selected.
2022-03-26 08:54:07 -04:00
Thomas Harte
4f6a9917c6
Test lbzx, lbzux.
2022-03-26 08:45:07 -04:00
Thomas Harte
3d48183753
Test lwzux.
2022-03-25 20:31:47 -04:00
Thomas Harte
33c31eb798
Test lwzx.
2022-03-25 20:23:21 -04:00
Thomas Harte
73ae7ad82f
Resolve final branch test: aa() applies.
2022-03-25 20:10:08 -04:00
Thomas Harte
ee6470708b
Merge pull request #1016 from TomHarte/unistd
...
Eliminate usages of unistd.h.
2022-03-25 17:04:29 -04:00
Thomas Harte
61f25926b5
Eliminate usages of unistd.h.
2022-03-25 16:58:06 -04:00
Thomas Harte
1a5d3bb69c
Match majority of branch tests.
2022-03-25 08:41:57 -04:00
Thomas Harte
7d4fe55d63
Handle bclrx set and clear.
2022-03-25 06:25:06 -04:00
Thomas Harte
089e03afe8
Navigates bcctrx tests, adding simplified bo() helpers and bi() helpers.
2022-03-24 20:44:03 -04:00
Thomas Harte
8e019f01ab
Document dozx and dozi.
2022-03-21 10:49:01 -04:00
Thomas Harte
77bdaf3c78
These are likely to be useful outside of the decoder.
2022-03-21 10:41:17 -04:00
Thomas Harte
0b6828c895
Decision: these enums will be at namespace scope.
2022-03-21 10:19:30 -04:00
Thomas Harte
d4704c656f
Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests
2022-03-21 10:18:36 -04:00
Thomas Harte
c01192c784
Add exposition for absx to divsx.
2022-03-21 10:17:55 -04:00
Thomas Harte
8adb611edf
Attempt to clarify with an enum.
2022-03-19 12:27:28 -04:00
Thomas Harte
e5af5b57ad
Add documentation for bx, bcx, bcctrx.
...
Catch bcx tests.
2022-03-18 19:55:26 -04:00
Thomas Harte
f05d3e6af3
Introduce dingusdev tests, do just enough to check bx
.
2022-03-18 17:24:12 -04:00
Thomas Harte
5963d038ef
Merge pull request #1014 from TomHarte/DDFSTRTSTOP
...
Improve application of DDFSTRT and DDFSTOP.
2022-03-18 15:48:06 -04:00
Thomas Harte
bfd28a04ba
Remove noise.
2022-03-18 10:41:20 -04:00
Thomas Harte
359ec257c0
Add a further state, seemingly to fix high-res mode.
2022-03-18 08:27:46 -04:00
Thomas Harte
88767e402c
Switch DDFSTART/STOP state machine.
2022-03-17 20:03:36 -04:00
Thomas Harte
88c7a6d053
Merge pull request #1013 from TomHarte/CroppedBottom
...
Switches all Copper WAITs to 12 cycles
2022-03-13 13:38:32 -04:00
Thomas Harte
e698cbf092
Silence debugging information.
2022-03-13 12:48:05 -04:00
Thomas Harte
f2ce646d8d
Undo 8-cycle-if-met WAIT.
2022-03-13 12:47:48 -04:00
Thomas Harte
cbf9b345ff
Merge pull request #1010 from TomHarte/80386
...
Expands x86 decoder to recognise 80386 opcodes.
2022-03-12 12:46:15 -05:00
Thomas Harte
1725894fe9
Eliminate redundant CMPSD, CDQ, CWDE.
...
Also removes IBTS for now, as I'm unclear where it should sit in the opcode map.
2022-03-12 12:24:44 -05:00
Thomas Harte
fd4f85eb19
Add SMSW.
2022-03-12 12:23:48 -05:00
Thomas Harte
f1c4864016
Eliminate INSD.
2022-03-12 11:37:21 -05:00
Thomas Harte
e6bd265729
Explain which BOUNDs operand is which.
2022-03-11 20:34:28 -05:00
Thomas Harte
c22e8112e7
Expand exposition.
2022-03-11 20:30:56 -05:00
Thomas Harte
44252984c2
Eliminate INT3 special case.
2022-03-11 14:03:46 -05:00
Thomas Harte
4b4f92780e
Shuffle extension word order.
...
The primary objective here is simplifying index calculation, but as per the note it does also potentially open up options with regard to packing in the future.
2022-03-11 13:24:45 -05:00
Thomas Harte
f694620087
Resolve TODO.
2022-03-11 13:10:44 -05:00
Thomas Harte
dc1d1f132e
Add one more address size modifier test.
2022-03-11 13:01:02 -05:00
Thomas Harte
9b4048ec6e
The address size modifier doesn't seem to affect far address sizes.
...
It's meant to affect only instructions with operands that reside in memory, I think. So probably only ::DirectAddress in my nomenclature. More research to do.
2022-03-11 12:46:07 -05:00
Thomas Harte
727342134c
Add 8086 length limit test.
2022-03-11 11:55:41 -05:00
Thomas Harte
c744a97e3c
Ensure no extensions for default constructed Instruction.
2022-03-11 11:55:26 -05:00
Thomas Harte
40cafb95ed
Add 286 and 386 instruction length tests.
2022-03-11 09:48:51 -05:00
Thomas Harte
91d75d7704
Switch strategy on 8086 instruction lengths.
2022-03-11 09:48:26 -05:00
Thomas Harte
dc8cff364f
Switch to common test.
2022-03-11 09:48:02 -05:00
Thomas Harte
572dc40e6b
Allow assignments.
2022-03-11 09:47:23 -05:00
Thomas Harte
f92ffddb82
Add instruction length limits.
2022-03-10 20:47:56 -05:00
Thomas Harte
641e0c1afc
Resolve default segment question.
2022-03-10 20:27:35 -05:00
Thomas Harte
bf7faa80c1
Add TODO.
2022-03-10 16:47:54 -05:00
Thomas Harte
a2ae3771eb
Add test for switch to Source::IndirectNoBase.
2022-03-10 15:45:56 -05:00
Thomas Harte
673ffc50da
Switch to intended compact version of Instruction
.
2022-03-10 15:14:50 -05:00
Thomas Harte
6dc9973754
Incorporate length into Instruction
.
2022-03-10 07:12:12 -05:00
Thomas Harte
cf6a910630
Handle no-base case directly in existing switch.
2022-03-09 20:20:32 -05:00
Thomas Harte
520baa6ec8
Formalise IndirectNoBase
and permit a knowledgable caller to avoid conditionals.
2022-03-09 20:19:40 -05:00
Thomas Harte
c1cc4f96df
Switch to const auto
.
2022-03-09 16:56:32 -05:00
Thomas Harte
bbf925a27e
Clarify, unify and correct decoding and encoding of [CALL/RET/JMP][near/far/relative/absolute].
2022-03-09 16:48:06 -05:00
Thomas Harte
381fd5dbe4
E8 is a relative call.
2022-03-09 16:37:07 -05:00
Thomas Harte
ead8b7437e
Remove done TODO.
2022-03-09 15:26:20 -05:00
Thomas Harte
9f2d18b7ba
Improve comment formatting.
2022-03-09 15:25:46 -05:00
Thomas Harte
acd9df6745
Fix segment/offset sizes for far calls.
2022-03-09 15:23:43 -05:00
Thomas Harte
f96c051932
Record PUSH immediate operation size.
2022-03-09 14:24:57 -05:00
Thomas Harte
67b2e40fae
Fixed: INs and OUTs remain single byte.
2022-03-09 10:51:16 -05:00
Thomas Harte
081a2acd61
Fix shift group operand size.
2022-03-09 09:33:25 -05:00
Thomas Harte
de79acc790
Fix RegAddr/AddrRegs and group 2 decoding.
2022-03-09 08:38:34 -05:00
Thomas Harte
a125bc7242
Fill in more of test32bitSequence
.
2022-03-08 20:16:19 -05:00
Thomas Harte
ebed4cd728
Introduce failing 32-bit parsing test.
2022-03-08 19:57:10 -05:00
Thomas Harte
21d4838322
Fix current implementation of data_segment
.
...
As far as it goes.
2022-03-08 17:08:21 -05:00
Thomas Harte
926a373591
Extend SIB test, correct decoder.
2022-03-08 15:03:37 -05:00
Thomas Harte
0cbb481fa4
Add a formal SIB test.
2022-03-08 14:56:27 -05:00
Thomas Harte
a954f23642
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 14:39:49 -05:00
Thomas Harte
41a104cc10
Adds special test/control/debug MOVs.
...
This'll do; it's not ideal but avoids bloating up the `Source` enum.
2022-03-07 17:04:05 -05:00
Thomas Harte
f0b4971c7b
Correct SHLD format.
2022-03-07 16:39:02 -05:00
Thomas Harte
8e669a32a3
Take a stab at group 8.
2022-03-07 16:34:56 -05:00
Thomas Harte
0e16e7935e
Correct double reference to Group 6.
2022-03-07 16:26:17 -05:00
Thomas Harte
7ea84d9a4e
Add MOVZX, MOVSX.
2022-03-07 16:25:44 -05:00
Thomas Harte
7313c89dec
Add BT, BTS, BTR, BTC, BSF, BSR.
2022-03-07 16:23:25 -05:00
Thomas Harte
35a66c03c2
Add the SETs.
2022-03-07 10:32:34 -05:00
Thomas Harte
bbb3168bae
Adds the missing shift group segues at c0 and c1.
2022-03-07 09:18:59 -05:00
Thomas Harte
1ea9d3faf8
Introduce additional forms of IMUL.
2022-03-07 09:05:22 -05:00
Thomas Harte
4479be4fd0
Add the two immediate PUSHes.
2022-03-06 14:28:41 -05:00
Thomas Harte
e7aaf4dd2e
Add LDS, LES, LSS test.
2022-03-06 12:10:25 -05:00
Thomas Harte
91a6bf671d
Also 'easy': LSS, LFS, LGS.
...
Though perhaps I'm off on LES and LDS?
2022-03-06 09:28:43 -05:00
Thomas Harte
49b5889d9e
0x8c is available on the 8086.
2022-03-06 09:24:59 -05:00
Thomas Harte
ede61ae130
Flag up TODOs, for easier in-editor navigation.
2022-03-05 17:48:01 -05:00
Thomas Harte
7a79111767
Add the easiest 80386 extensions: PUSH/POP FS/GS and longer conditional jumps.
2022-03-05 17:32:21 -05:00
Thomas Harte
6432521b9d
Correct two references to JP that should be JL.
2022-03-05 17:16:32 -05:00
Thomas Harte
65f578fe61
Add notes on all missing opcodes.
2022-03-05 17:16:13 -05:00
Thomas Harte
3a8eb4a4f0
Add 80386 segment overrides.
2022-03-05 17:03:46 -05:00
Thomas Harte
eb180656bb
Fix $8e data size, add $8c.
2022-03-05 17:00:48 -05:00
Thomas Harte
1afcbba218
Clarify sign extension availability.
2022-03-05 16:44:26 -05:00
Thomas Harte
8a0902a83b
Adapts existing opcodes for 32-bit parsing.
2022-03-05 13:52:07 -05:00
Thomas Harte
dfb312fee6
Make column and row meanings overt.
2022-03-05 11:56:08 -05:00
Thomas Harte
11bb594fa2
Sets up [ignored] memory and data size prefixes.
2022-03-02 20:23:35 -05:00
Thomas Harte
8e3ae2c78f
Add opcode map as documentation.
2022-03-02 20:00:21 -05:00
Thomas Harte
8080d1d961
Extend test case slightly.
2022-03-01 20:22:43 -05:00
Thomas Harte
4b4135e35a
Correct #undef.
2022-03-01 18:23:24 -05:00
Thomas Harte
d1148c4cab
Switch to constexpr function, for guaranteed semantics.
2022-03-01 17:30:41 -05:00
Thomas Harte
8ee62b4789
Simplify address size semantics.
...
Since it'll no longer be a mode-dependant toggle, but a fully-retained value.
2022-03-01 17:29:26 -05:00
Thomas Harte
5e7a142ff1
Fix is_write
errors, update comment, add additional source for asserts.
2022-03-01 16:51:54 -05:00
Thomas Harte
2c816db45e
Refactor: (i) to expose effective address calculation; and (ii) to include address size in Instruction.
2022-03-01 09:36:37 -05:00
Thomas Harte
b920507f34
Double down on AddressT
, add an assert
on memory_mask
.
2022-02-28 10:03:58 -05:00
Thomas Harte
d8601ef01f
Add missing hex specifier. Test now passes.
2022-02-28 09:54:29 -05:00
Thomas Harte
afbc57cc0c
Incorporate displacement, switch macro flag.
2022-02-28 09:53:23 -05:00
Thomas Harte
9f12c009d6
Correct data size when accessing address registers.
2022-02-27 19:45:03 -05:00
Thomas Harte
84ac68a58b
Fix indirect memory read/write
2022-02-27 18:43:00 -05:00
Thomas Harte
27d1df4699
Introduce enough of a DataPointerResolver test to build but fail.
2022-02-27 18:27:58 -05:00
Thomas Harte
0d7a7dc7c9
Introduce DataPointerResolver
, to codify the meaning of DataPointer
and validate that enough information is present.
2022-02-27 11:25:02 -05:00
Thomas Harte
b8bff0e7f5
Double up eSP, eBP, eSI, eDI and AH, CH, DH, BH enums, as per Intel's encoding.
2022-02-24 05:16:15 -05:00
Thomas Harte
60bf1ef7ea
Rename SourceSIB to DataPointer, extend to allow for an absent base.
2022-02-23 08:28:20 -05:00
Thomas Harte
dc37b692cf
Switch to templated test function.
2022-02-23 04:33:28 -05:00
Thomas Harte
95976d8b58
Add missing #include.
2022-02-21 16:33:58 -05:00
Thomas Harte
ecb20cc29b
Improve tabbing.
2022-02-21 16:09:03 -05:00
Thomas Harte
b6183e86eb
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 16:06:02 -05:00
Thomas Harte
229af0380c
This is normatively called the address size.
2022-02-21 15:52:16 -05:00
Thomas Harte
b968a662d3
Dump notes on intended Instruction layout, add memory size flag.
2022-02-21 15:48:58 -05:00
Thomas Harte
159e869fe6
Justifies the templatisation.
2022-02-21 15:33:08 -05:00
Thomas Harte
76814588b8
Template Instruction
on its content size.
2022-02-21 12:36:03 -05:00
Thomas Harte
1934c7faa2
Switch Decoder
into a template.
2022-02-21 12:21:57 -05:00
Thomas Harte
9e9e160c43
Eliminate Ind[BXPlusSI/etc] in favour of specifying everything via a ScaleIndexBase.
2022-02-21 11:45:46 -05:00
Thomas Harte
546b4edbf1
Ensure ScaleIndexBase
can be used constexpr
; add note-to-self on indexing table.
2022-02-20 19:22:28 -05:00
Thomas Harte
63d8a88e2f
Switch to holding the SIB as a typed ScaleIndexBase.
...
(and permit copy assignment)
2022-02-20 17:54:53 -05:00
Thomas Harte
75d2d64e7c
Albeit that it requires nuanced shift/roll semantics, eliminates CL
constant.
...
Shifts and rolls are already slightly semantically special for being undefined for values greater than 8/16/32 — i.e. in some implementations they don't even use the entirety of CL, just the low five bits. Which makes me feel a little better.
The upside of no ambiguity between eCX size 1 and CL justifies the trade.
2022-02-20 17:52:19 -05:00
Thomas Harte
a5113998e2
Accept that IN and OUT are going to have special semantics, thereby kill ::AX and ::DX.
2022-02-20 17:15:01 -05:00
Thomas Harte
4d2e8cd71d
Adds a presently-unreachable step for SIB consumption.
2022-02-19 18:00:27 -05:00
Thomas Harte
30b355fd6f
Chips away further at the legacy register names.
2022-02-18 18:37:47 -05:00
Thomas Harte
c257b91552
Update tests to preference away from [A/B/C/D]L.
2022-02-18 16:32:28 -05:00
Thomas Harte
12df7112da
Starts adjusting the concept of a Source
.
2022-02-17 11:32:09 -05:00
Thomas Harte
cd5ca3f65b
Attempts a full decoding of the 80286 instruction set.
2022-02-10 17:13:50 -05:00
Thomas Harte
0bd63cf00f
Introduces the easy F page instructions.
2022-02-10 09:35:05 -05:00
Thomas Harte
7ceb3369eb
Attempts decoding of the 80186 set.
2022-02-09 17:51:48 -05:00
Thomas Harte
ae21726287
Splits 80186 additions from 80286; fills in a touch more.
2022-02-01 20:38:10 -05:00
Thomas Harte
a4da1b6eb0
Begins enumerating the 80286 and 80386 instructions.
2022-01-31 09:11:06 -05:00
Thomas Harte
85bfd2eba3
Remove further errant 'Awaiting's.
2022-01-31 08:22:07 -05:00
Thomas Harte
2d543590dc
Make a noun, for better consistency.
2022-01-31 08:14:33 -05:00
Thomas Harte
18b6f17e86
With some refactoring makes some minor steps towards supporting gaps.
2022-01-06 17:24:31 -05:00
Thomas Harte
f37179d9f2
Gaps appear to contain pre-MFM data (?)
2022-01-02 15:39:26 -05:00
Thomas Harte
3e0b7d71d4
Properly handle partial bytes.
2022-01-01 19:09:19 -05:00
Thomas Harte
58d10943ed
Add asserts to validate my reserve sizes.
2022-01-01 19:08:44 -05:00
Thomas Harte
dc920a04f6
Add missing #include.
2022-01-01 19:03:07 -05:00
Thomas Harte
d031381e70
Gaps provide content, and data chunk lengths seem to be in terms of unencoded bytes.
2022-01-01 18:47:07 -05:00
Thomas Harte
ed1b0b90f7
Makes a first attempt at encoding data.
2022-01-01 18:36:44 -05:00
Thomas Harte
38dd3c5c60
On second thoughts, no need to use a vector here.
2022-01-01 17:15:12 -05:00
Thomas Harte
d3189acaa6
Add a constexpr route that explicitly calculates the simplest possible form.
2022-01-01 17:14:52 -05:00
Thomas Harte
350c98ab4d
Add those densities I've yet discovered the rules for.
2021-12-29 18:15:37 -05:00
Thomas Harte
4f3c754771
Adds exposition.
2021-12-27 19:15:46 -05:00
Thomas Harte
dc994f001d
Mention units.
2021-12-27 18:55:11 -05:00
Thomas Harte
9b6ccbcc95
Parses data and gap stream elements.
2021-12-27 18:12:44 -05:00
Thomas Harte
9d3cf9c73c
Collate descriptions of all tracks.
2021-12-26 14:49:51 -05:00
Thomas Harte
28572d4392
Enforce string-length requirement.
2021-12-26 09:12:44 -05:00
Thomas Harte
0433db0370
Eliminate macro.
2021-12-25 19:36:54 -05:00
Thomas Harte
a6b326da48
Parse the INFO record.
2021-12-25 18:17:13 -05:00
Thomas Harte
e457ce66ea
Adds sanity checks around CAPS block.
2021-12-25 17:32:29 -05:00
Thomas Harte
c118dd8afe
Adds just enough to list all the blocks in an IPF.
2021-12-25 17:27:50 -05:00
Thomas Harte
dba3a3d942
Add through route to an IPF container.
2021-12-25 17:06:47 -05:00
Thomas Harte
6c606b5506
Fix through route to TargetPlatform::TypeDistinguisher
.
2021-12-25 17:06:12 -05:00
Thomas Harte
55dbeefeb2
Merge pull request #1005 from TomHarte/SerialPort
...
Adds empty callouts for all serial port registers.
2021-12-25 16:39:27 -05:00
Thomas Harte
4d9589af7c
Merge pull request #1006 from TomHarte/Shared68000Tables
...
Minor 68000 style improvements.
2021-12-25 14:11:25 -05:00
Thomas Harte
ee625cb8a8
Minor style improvements; especially: don't assume value of NoBusProgram.
2021-12-25 14:05:38 -05:00
Thomas Harte
f20940a37b
Give Program
full ownership of the sentinel value.
...
In case I want to reduce the size of this field later.
2021-12-23 16:32:21 -05:00
Thomas Harte
32e0a66610
Trust the compiler with this bit field.
2021-12-23 16:28:55 -05:00
Thomas Harte
d9598b35c2
Add some additional metrics.
2021-12-23 16:27:54 -05:00
Thomas Harte
acba357df6
Adds empty callouts for all serial port registers.
2021-12-23 15:22:20 -05:00
Thomas Harte
7ce335d9da
Merge pull request #1004 from TomHarte/FastRAM
...
Adds fast RAM to the Amiga, along with size selection for both fast & chip.
2021-12-23 11:43:42 -05:00
Thomas Harte
3caf9ca914
Remove a bunch of unused names.
2021-12-23 11:39:00 -05:00
Thomas Harte
fd569201ef
Add Qt GUI for Amiga memory selection.
2021-12-23 11:28:44 -05:00
Thomas Harte
f094aa946a
Add Mac GUI for Amiga memory selection.
2021-12-22 18:20:55 -05:00
Thomas Harte
a17c192a9e
Allow chip RAM size selection, while I'm here.
2021-12-22 15:30:19 -05:00
Thomas Harte
1916a9b99c
Remove stdout noise.
2021-12-22 15:22:28 -05:00
Thomas Harte
9796b308dc
Add basic implementation of fast RAM.
2021-12-22 15:17:11 -05:00
Thomas Harte
bdf0a1941c
Merge pull request #1002 from TomHarte/FastBlitterFills
...
Switch to a table-based implementation of fill mode.
2021-12-19 17:35:27 -05:00
Thomas Harte
d0e3024bec
Switch to nibble-oriented lookup tables for fill mode.
2021-12-19 17:16:46 -05:00
Thomas Harte
d2ad149e56
Fill mode always runs right to left.
2021-12-19 16:43:18 -05:00
Thomas Harte
ad602a4722
Merge pull request #1001 from TomHarte/AmigaReadWrite
...
Ensures Chipset reads can map to writes and vice versa.
2021-12-19 16:35:43 -05:00
Thomas Harte
348840a2aa
It's probably a net detriment to use a template in this scenario.
2021-12-19 16:31:44 -05:00
Thomas Harte
3a719633eb
Consolidate interface; correct LOGs.
2021-12-18 19:39:41 -05:00
Thomas Harte
bd69948d37
The Copper can now skip Chipset::perform
.
2021-12-18 17:53:11 -05:00
Thomas Harte
54aa211f56
Avoid infinite loops for completely undefined addresses.
2021-12-18 17:48:45 -05:00
Thomas Harte
f118891970
Breaks Chipset::perform
into read
and write
.
...
This allows each to call the other when a read occurs of a write-only address, and vice versa.
2021-12-18 17:43:53 -05:00
Thomas Harte
c4055fde97
Merge pull request #1000 from TomHarte/CopperTests
...
Amiga: regularises timing; improves Copper sleep/wait costs
2021-12-18 16:46:53 -05:00
Thomas Harte
dbae3fc9a5
Propagate to bitplanes immediately; fix odd/even confusion.
2021-12-18 16:37:40 -05:00
Thomas Harte
7c73ed7ed5
Bump Xcode version number.
2021-12-18 14:55:27 -05:00
Thomas Harte
c834960bfb
Withdraw separate x-and-y guess, make MOVE lose a cycle if a sleep/wake occurs.
2021-12-12 19:18:18 -05:00
Thomas Harte
600abc55b5
Compare x and y separately, wake immediately from a sleep, log more.
2021-12-12 17:26:33 -05:00
Thomas Harte
f3ec7d54bb
Clarifies wait-for-CPU-slot semantics.
...
Big bonus: this guarantees `advance_dma`s will be called at most once per output cycle, even if they return `false`.
2021-12-09 19:17:44 -05:00
Thomas Harte
090760e526
Merge pull request #998 from TomHarte/QtAmiga
...
Add the Amiga to the Qt UI.
2021-12-08 13:45:34 -05:00
Thomas Harte
cccde7dc89
Correct given memory size.
2021-12-08 11:41:50 -05:00
Thomas Harte
849e48f519
Add the Amiga to Qt's UI.
2021-12-08 11:41:38 -05:00
Thomas Harte
1c3935eb40
Add README.md
...
As a warning.
2021-12-07 18:19:51 -05:00
Thomas Harte
466bed3163
Merge pull request #994 from TomHarte/AmigaREADME
...
Fess up to the Amiga.
2021-12-07 04:32:43 -05:00
Thomas Harte
641a9c72e9
Fess up to the Amiga.
2021-12-07 04:30:54 -05:00
Thomas Harte
5138216ba1
Merge pull request #978 from TomHarte/Amiga
...
Introduces nascent Amiga emulation
2021-12-07 04:18:53 -05:00
Thomas Harte
de1f5686a8
Reenable hardened runtime.
2021-12-07 04:05:10 -05:00
Thomas Harte
c983678fcd
Reenable app sandbox.
2021-12-07 03:57:58 -05:00
Thomas Harte
2b0415d552
Attempt to avoid off-by-one buffer reads, add modulation.
2021-12-06 19:28:40 -05:00
Thomas Harte
066e4421e8
Attempt volcntrld.
2021-12-06 06:35:08 -05:00
Thomas Harte
f02a241249
Inserts an additional reload.
2021-12-05 17:47:12 -05:00
Thomas Harte
a5fe1e4259
Largely debugs audio state machine.
...
I think I'm still missing an address reload somewhere though, and attachment doesn't actually push.
2021-12-05 15:27:35 -05:00
Thomas Harte
9b80563443
Exposes targets for modulation.
2021-12-05 06:38:55 -05:00
Thomas Harte
91b5da06e3
Perform reload on Disabled -> WaitingForDummyDMA.
2021-12-04 19:17:40 -05:00
Thomas Harte
7320f96ae7
Capture attachment flags.
2021-12-04 18:02:43 -05:00
Thomas Harte
fdf2b9cd7b
Add local data pointers.
2021-12-04 17:58:41 -05:00
Thomas Harte
bfc70a1b60
Ensure interrupt request bits always propagate.
2021-12-04 16:50:42 -05:00
Thomas Harte
aff7a93106
Move DMAFlags to Flags.hpp.
2021-12-04 08:26:28 -05:00
Thomas Harte
3b027c4593
Switch and -> or for testing transitions from ::PlayingLow.
2021-12-04 08:24:41 -05:00
Thomas Harte
42d3bdd373
Adds a begin_state template.
2021-12-04 07:20:17 -05:00
Thomas Harte
57789092c1
Keep audio fetches in bounds.
2021-12-03 07:16:21 -05:00
Thomas Harte
6bc5268cbd
Reload period counter on low -> high transition.
2021-12-02 18:43:02 -05:00
Thomas Harte
887ab705d1
Add missing <cassert>.
2021-12-02 13:00:25 -05:00
Thomas Harte
ff6ddaed2e
Full scale is 65536.
2021-12-02 12:55:11 -05:00
Thomas Harte
e6fe36f45c
Add buffer-length assert; add <tuple> where std::tuple_size is used.
2021-12-02 12:53:20 -05:00
Thomas Harte
3a26f6b8bf
Ensure full buffer provision.
2021-12-02 12:52:43 -05:00
Thomas Harte
06b6f85d55
Correct stereo.
2021-12-02 11:15:29 -05:00
Thomas Harte
d6f1ea50a6
Switch to slightly more straightforward presumption of no data wanted.
2021-12-02 09:41:16 -05:00
Thomas Harte
9554869886
Simplify DMA logic.
2021-12-02 09:33:02 -05:00
Thomas Harte
364059551c
Add extra notes per errata, plus bonus state code repetitions.
2021-12-02 09:30:52 -05:00
Thomas Harte
06340b1ad7
Advance DMA pointer, treat audio as signed, request data on low -> high transition.
...
There's now some audio, sometimes when there should be. But it's not correct.
2021-12-01 18:34:54 -05:00
Thomas Harte
d23511860d
Attempts audio output.
2021-12-01 06:01:58 -05:00
Thomas Harte
a8dd4660b2
Adds a pipeline for audio output.
2021-12-01 05:37:58 -05:00
Thomas Harte
eb3a0eb3c7
Attempt full implementation of collisions.
2021-11-29 18:39:33 -05:00
Thomas Harte
cd0148e0bc
Switch to a default 1mb of Chip RAM.
2021-11-29 16:55:45 -05:00
Thomas Harte
8584ee609f
Support a fetch window start on line 0.
2021-11-28 05:37:49 -05:00
Thomas Harte
373847e2b7
Avoid posting redundant key events.
2021-11-28 05:31:00 -05:00
Thomas Harte
84f7d8dfc2
Factors out pixel generation, adds HAM.
2021-11-28 05:06:30 -05:00
Thomas Harte
e057a7d0dd
Attempts to implement sprite/playfield priorities.
2021-11-27 15:03:46 -05:00
Thomas Harte
7bab15bf99
Minor copy improvements.
2021-11-27 11:38:41 -05:00
Thomas Harte
dac40630fd
Adds support for the Blitter-busy flag to WAIT and SKIP.
2021-11-27 11:36:15 -05:00
Thomas Harte
33bfa1b81c
Move BitplaneShifter adjacent to expand_bitplane_byte
.
2021-11-26 18:29:09 -05:00
Thomas Harte
8fc27dc292
Moves bitplane collection and shifter out of Chipset.[h/c]pp.
2021-11-26 18:16:24 -05:00
Thomas Harte
f8e8f18be5
Switch to std::clamp
.
2021-11-26 18:10:29 -05:00
Thomas Harte
8b38c567d2
Add missing #include for std::clamp.
2021-11-26 18:08:39 -05:00
Thomas Harte
cd53e42d79
Resolve operator precedence.
2021-11-26 18:08:10 -05:00
Thomas Harte
bea6cf2038
Move mouse and joystick into a separate file, give a common parent.
2021-11-26 17:50:47 -05:00
Thomas Harte
eca80f1425
Sprites: avoid magic constants, ensure proper DMA resumption.
2021-11-26 16:02:18 -05:00
Thomas Harte
1c0962e53c
Move sprites into their own source file.
2021-11-26 15:30:31 -05:00
Thomas Harte
4b21549ff4
Add a couple of static asserts.
2021-11-26 15:23:54 -05:00
Thomas Harte
30d7b0129b
Correct sprite ordering within pairs.
2021-11-26 11:58:50 -05:00
Thomas Harte
ce6877d6e4
Sprites: infer part of DMA state from slot, no access during blank.
...
Also sets the proper vertical blank length.
2021-11-26 09:37:52 -05:00
Thomas Harte
0ab5177637
Allow DMAState::FetchStopAndControl on y == v_stop_.
2021-11-25 14:29:12 -05:00
Thomas Harte
276cbfa505
Simplify sprite state machine.
...
This now better matches the explanation given on Page 133 of the Amiga System Programmer's Guide.
2021-11-25 14:08:55 -05:00
Thomas Harte
610c85a354
Correct test logic.
...
All tests now pass.
2021-11-25 04:11:20 -05:00
Thomas Harte
012084b37b
Fix exclusive fill, sizing, eliminate ECS call-ins.
...
The clock test now proceeds further, but still doesn't seem to pass.
2021-11-24 17:25:32 -05:00
Thomas Harte
55af6681af
Avoid unnecessary get_port_input
calls.
2021-11-24 17:15:48 -05:00
Thomas Harte
2a7a42ff8f
Add header for assert
.
2021-11-24 16:28:18 -05:00
Thomas Harte
7af5737ec5
Switch to LOG
.
2021-11-24 16:15:40 -05:00
Thomas Harte
0ad1529f3f
Retain delegate bit length for non-self-clocked data.
2021-11-24 16:15:27 -05:00
Thomas Harte
0df8173536
Merge branch 'master' into Amiga
2021-11-24 08:58:03 -05:00
Thomas Harte
b517811e2f
Merge pull request #988 from TomHarte/HeaderOnly6502
...
Moves the 6502 towards being a header-only dependency.
2021-11-24 08:57:45 -05:00
Thomas Harte
83d3a9c6dd
Merge branch 'master' into HeaderOnly6502
2021-11-24 08:48:36 -05:00
Thomas Harte
d0402261e6
Merge pull request #993 from TomHarte/PushAudio
...
Adds a push route for lowpass-filtered audio.
2021-11-24 08:47:10 -05:00
Thomas Harte
6f6e09d200
Correct: load
-> store
.
2021-11-22 15:18:12 -05:00
Thomas Harte
24e2fd4184
Avoid implicit conversion.
2021-11-22 11:28:02 -05:00
Thomas Harte
1aada996dc
Correct const
ing.
2021-11-22 11:18:17 -05:00
Thomas Harte
f5d3d6bcea
Splits the lowpass filter into push and pull variants.
2021-11-21 15:37:29 -05:00
Thomas Harte
a8a99f647f
Further improves framing.
2021-11-21 08:13:55 -05:00
Thomas Harte
ff68b26c44
Push HSYNC 11 slots over, to its proper position, and add a frame crop.
2021-11-20 12:39:50 -05:00
Thomas Harte
a94b4f62fd
Takes a stab at attached sprites.
2021-11-19 14:19:47 -05:00
Thomas Harte
bcc959d938
Sprites: deconflate vertical and modification flags; disarm on CTL not POS.
2021-11-19 08:03:10 -05:00
Thomas Harte
cf25d8a378
Increase logging (but leave it disabled).
2021-11-19 08:01:23 -05:00
Thomas Harte
c750bdafd5
Switch to a saturating conversion.
2021-11-18 18:01:30 -05:00
Thomas Harte
693d46f8ea
Mask by index, not colour.
2021-11-18 05:36:38 -05:00
Thomas Harte
3496ebd1d7
Constrain sprite fetches to Chip RAM.
2021-11-17 17:49:42 -05:00
Thomas Harte
be763cf7fe
Expose joystick to the world.
2021-11-17 15:33:46 -05:00
Thomas Harte
c3b4bee210
Adds a joystick class.
2021-11-17 14:26:51 -05:00
Thomas Harte
6df0227ab1
Hacks in a basic effort at dual playfields.
2021-11-16 18:26:27 -05:00
Thomas Harte
2a3a7fa8a0
Reset will_request_interrupt
.
2021-11-15 16:00:35 -05:00
Thomas Harte
50a6496399
Avoids over-greedy DMA.
2021-11-15 12:31:15 -05:00
Thomas Harte
c99dee86dd
Adds missing low -> high actions, implements more transitions.
2021-11-15 12:29:32 -05:00
Thomas Harte
0c5bb9626b
Separates state transitions and tests.
2021-11-15 05:29:28 -05:00
Thomas Harte
a9971917f5
Attempts a translation of Commodore's documentation.
2021-11-14 14:54:33 -05:00
Thomas Harte
4c62611da3
Adds enough state machine to get into the near-incomprehensible stuff on the right.
2021-11-14 10:48:50 -05:00
Thomas Harte
47f36f08fb
Switches to a synchronous audio state machine; renames advance -> advance_dma.
...
I can worry about how to just-in-time things once I better understand the hardware in general.
2021-11-13 15:53:41 -05:00
Thomas Harte
f906bab1a5
Provides feedback on interrupt flags, starts on state machine.
2021-11-13 11:05:39 -05:00
Thomas Harte
fffc03c4e4
Propagates time to the audio subsystem.
2021-11-12 15:30:52 -05:00
Thomas Harte
0f6934a131
This uses Cycles and HalfCycles, so should include ClockReceiver.
2021-11-11 09:24:32 -05:00
Thomas Harte
0a94184d6b
Provides a greater wealth of audio data.
2021-11-11 09:24:15 -05:00
Thomas Harte
7be3578497
Adds a target for audio writes.
2021-11-09 07:11:23 -05:00
Thomas Harte
eeaccb8ac0
Implements clear_all_keys
.
2021-11-08 17:49:09 -05:00
Thomas Harte
8ef9a932aa
Adds inclusive fill test; fixes inclusive fills.
2021-11-07 14:26:13 -08:00
Thomas Harte
31e22e4cfb
Provides full serial input.
2021-11-07 05:19:16 -08:00
Thomas Harte
4fc25fb798
Adds basic shift input.
2021-11-07 05:18:54 -08:00
Thomas Harte
941d9a46a2
Makes a better effort at exposition; better implements clocked line.
2021-11-07 05:18:40 -08:00
Thomas Harte
ecfe68d70f
Introduce the principle that a Serial::Line can be two-wire — clock + data.
2021-11-06 16:54:20 -07:00
Thomas Harte
c0c2b5e3a9
Post key actions to the nominated serial line.
...
Albeit that I'm still thinking through whether I want the option of including a clock on Serial::Line. It'd be natural in one sense — there's already one built in — but might weaken Serial::Line's claim to be a one-stop shop for both enqueued and real-time connections without a reasonable bit of extra work.
2021-11-06 12:03:09 -07:00
Thomas Harte
f102d8a4b4
Extend to allow full-[byte/word/dword] writes, in LSB or MSB order.
2021-11-06 12:01:32 -07:00
Thomas Harte
471e13efbc
Transcribes keycodes.
2021-11-04 18:54:42 -07:00
Thomas Harte
6d34432988
Starts to build in a serial line for input.
2021-11-04 18:54:28 -07:00
Thomas Harte
d3f0d15732
Merge branch 'master' into Amiga
2021-11-03 19:27:06 -07:00
Thomas Harte
b827b9e33e
Add necessary shift storage.
2021-11-03 19:26:45 -07:00
Thomas Harte
29e5ecc282
Add TODOs rather than complete stop on shift register acccesses.
2021-11-02 18:19:31 -07:00
Thomas Harte
c9bf2dda16
Attempt implementation of disk sync.
2021-11-02 18:18:59 -07:00
Thomas Harte
3ceb378b9b
Relocate disk logic into a separate compilation unit.
2021-11-02 17:35:23 -07:00
Thomas Harte
1cf1c90511
Adds support for interlaced output.
2021-11-02 14:34:03 -07:00
Thomas Harte
491b9f83f2
Merge pull request #990 from mariuszkurek/master
...
Make SDL and Qt binary names consistent
2021-11-02 13:15:27 -07:00
Thomas Harte
d989825216
Add bonus notes on VPOSR.
2021-11-02 03:47:39 -07:00
Thomas Harte
3976420b88
Retains a little more of output controls.
2021-11-01 17:15:36 -07:00
Thomas Harte
2f1ce5fe43
Switch to using the swizzled palette for playfield output.
2021-11-01 14:44:30 -07:00
Thomas Harte
42145a5b8a
Delay bitplane installation until end of slot.
2021-11-01 14:18:58 -07:00
mariuszkurek
04f4536cb2
Make SDL and Qt binary names consistent
2021-11-01 09:13:06 +01:00
Thomas Harte
4e66017205
Enable sprite reuse and toggle to inactive when visible region is over.
2021-10-31 16:52:48 -07:00
Thomas Harte
2c1f2edcf2
Introduce failing 'clock' test case.
...
i.e. a few seconds of the Workbench 1.0 clock application.
2021-10-31 16:12:51 -07:00
Thomas Harte
299d517449
Performs a first implementation of fill mode.
2021-10-31 14:36:31 -07:00
Thomas Harte
561e73dbd7
Merge branch 'Amiga' of github.com:TomHarte/CLK into Amiga
2021-10-31 14:12:40 -07:00
Thomas Harte
9e6ffaad7d
Introduce test case for fill mode.
2021-10-31 14:12:26 -07:00
Thomas Harte
9cded1e92c
Introduce test case for fill mode.
2021-10-31 14:08:37 -07:00
Thomas Harte
4c1ab6ff25
Rethinks bitplane stops.
2021-10-31 09:01:38 -07:00
Thomas Harte
16f31cab6a
Avoid duplication of CIA select test.
2021-10-30 12:05:18 -07:00
Thomas Harte
02c88e6826
VHPOSR's fields are the other way around.
2021-10-30 12:04:46 -07:00
Thomas Harte
9ecd43238f
Correct 8520 TOD setting and getting.
2021-10-30 12:02:43 -07:00
Thomas Harte
5ffe71346c
Eliminate interrupt magic constants.
2021-10-29 19:04:06 -07:00
Thomas Harte
d25804f4a2
Throws in official register names.
2021-10-29 14:05:11 -07:00
Thomas Harte
edb75e69cb
Implement bitplane modulos.
2021-10-29 11:29:22 -07:00
Thomas Harte
f3e895f17c
Tag intended unused parameters.
2021-10-29 06:21:02 -07:00
Thomas Harte
b952d73e83
Disallow programmatic setting of blitter status.
2021-10-29 06:19:57 -07:00
Thomas Harte
07facc0636
Takes a stab at BZERO.
2021-10-28 18:12:46 -07:00
Thomas Harte
da1a69be27
Caps mouse speed.
...
Also takes another guess at CIA interrupt bits. To no avail.
2021-10-27 18:38:02 -07:00
Thomas Harte
7e31658932
Remove accidental commit.
2021-10-26 21:49:32 -07:00
Thomas Harte
5ebc59dd1f
Introduce additional test cases.
2021-10-26 20:58:38 -07:00
Thomas Harte
b10f5ab110
Apply A mask when loading into barrel shifter.
2021-10-26 20:02:28 -07:00
Thomas Harte
b4286bb42b
Modulos are subtracted in descending mode.
2021-10-26 07:21:51 -07:00
Thomas Harte
4d7ce3792f
Use additional test cases.
2021-10-25 21:48:43 -07:00
Thomas Harte
76767da300
Undo accidental change.
2021-10-25 21:48:19 -07:00
Thomas Harte
dc8701a929
Introduce some additional Blitter test cases.
2021-10-25 21:40:20 -07:00
Thomas Harte
139d35c6f9
Switches to basic use of sprite shifters.
2021-10-25 20:58:48 -07:00
Thomas Harte
cb24457b4a
Starts on a two-at-a-time sprite shifter.
2021-10-25 16:30:30 -07:00
Thomas Harte
9f3efb7f05
Limits graphical output to [all but one bit] of the display window.
2021-10-25 14:12:23 -07:00
Thomas Harte
e6001e0f22
Shifts bitplanes irrespective of output window.
2021-10-25 13:59:39 -07:00
Thomas Harte
c6535bf035
Switches bitplane shifter to returning four high-res pixels at a time.
2021-10-25 13:34:36 -07:00
Thomas Harte
7118a515e0
Reduce logging in trustworthy areas.
2021-10-23 20:36:41 -07:00
Thomas Harte
952451c9b8
Add mouse input.
2021-10-23 20:17:13 -07:00
Thomas Harte
610327a04e
Fix sprite H start bit order.
2021-10-22 23:20:20 -07:00
Thomas Harte
2121e32409
Fix sprite bit ordering.
2021-10-22 21:10:01 -07:00
Thomas Harte
7ec21edc2f
Attempts to hack in some form of sprite display.
2021-10-22 19:51:10 -07:00
Thomas Harte
003162f710
Limit to specific purpose.
2021-10-22 16:16:19 -07:00
Thomas Harte
040ac93042
Takes a shot at the vertical stuff of sprite DMA.
2021-10-22 14:32:59 -07:00
Thomas Harte
b489ba3d0d
Adds sprite DMA windows.
2021-10-22 13:07:20 -07:00
Thomas Harte
c5e8b547af
Captures the attach flag and observes activation rule.
2021-10-22 11:21:58 -07:00
Thomas Harte
e67de90ad0
Starts to bring sprites inside DMADevice orthodoxy.
2021-10-21 21:57:46 -07:00
Thomas Harte
c3c84c88a1
Switch to ahead-of-time planar to chunky conversion.
2021-10-21 20:48:57 -07:00
Thomas Harte
0dc9c4cee1
Undo hard-coding of fetch window.
2021-10-19 15:18:39 -07:00
Thomas Harte
544c137cb0
Add updated intel.
2021-10-16 13:30:56 -07:00
Thomas Harte
b312a61a81
Add two dummy reads.
2021-10-16 13:30:45 -07:00
Thomas Harte
4917556a99
The shift goes the other way in descending mode.
2021-10-16 11:09:40 -07:00
Thomas Harte
15ed4a0d09
Introduce failing test case for sector decoding.
2021-10-16 10:48:32 -07:00
Thomas Harte
aa6b0f07b7
Correct filename.
2021-10-16 05:37:46 -07:00
Thomas Harte
d9d20d9d30
Walk back slightly.
2021-10-14 18:02:58 -07:00
Thomas Harte
689bfbbdb3
Be overt in initialiser list.
2021-10-14 16:57:26 -07:00
Thomas Harte
e27a10bde4
Simplify control flow.
2021-10-14 16:47:18 -07:00
Thomas Harte
253a199f27
Fire sync-match interrupt upon any match.
2021-10-14 16:36:17 -07:00
Thomas Harte
61e5702520
Remove dead TODO.
2021-10-14 16:09:11 -07:00
Thomas Harte
b12c640807
Makes drives non-copyable.
...
To avoid error in the future.
2021-10-14 12:37:55 -07:00
Thomas Harte
9be23ecc34
Add end-of-Blit interrupt.
...
Along with a slightly easier path for posting interrupts, in C++ compilation unit terms.
2021-10-13 15:09:19 -07:00
Thomas Harte
8960f471a0
Use unspread_bits
for FM and MFM decoding.
2021-10-12 15:18:50 -07:00
Thomas Harte
955cb6411c
Factor out bit spreading.
...
(And do a better job of it)
2021-10-12 14:49:01 -07:00
Thomas Harte
fc4ca4f8e3
I don't think there are sync words at the start of the track.
2021-10-12 10:38:15 -07:00
Thomas Harte
eec068914e
Slightly improve logging.
2021-10-11 18:05:57 -07:00
Thomas Harte
a1f02d0cd8
Add track padding.
2021-10-11 18:05:37 -07:00
Thomas Harte
39b8285ba5
Trust the HRM on step bit, but catch rising edge.
2021-10-11 07:42:42 -07:00
Thomas Harte
7733fef3bd
DSKLEN has to be written twice.
2021-10-11 06:16:01 -07:00
Thomas Harte
6acddfdb98
Add the sync match interrupt.
...
Albeit that it doesn't yet unblock disk DMA.
2021-10-11 03:37:56 -07:00
Thomas Harte
ec3d5c0b32
Increase maximum number of activity LEDs to eight.
2021-10-10 18:37:33 -07:00
Thomas Harte
99492c2ec2
Further tweak logging.
2021-10-10 18:19:50 -07:00
Thomas Harte
addf9f9af4
Moves block byte writes into Storage::Encodings::MFM::Encoder
.
2021-10-10 16:06:51 -07:00
Thomas Harte
846b505d27
Reduce logging; disk data probably isn't the immediate obstacle.
2021-10-10 13:04:10 -07:00
Thomas Harte
c4cfcfab8e
Checksums appear to be calculated as 32-bit quantities.
2021-10-10 12:58:10 -07:00
Thomas Harte
5e083426c5
Takes another run at checksums.
...
It turns out I'd read entirely the wrong section of the ADF FAQ. Am now trying to piece things together from various EAB threads.
2021-10-10 11:47:48 -07:00
Thomas Harte
8d43b4a98d
Expands Disk DMA access window.
2021-10-10 11:47:02 -07:00
Thomas Harte
aeaea073c6
Switch both: (i) which bits are odd/even; and (ii) nibble ordering.
2021-10-09 13:45:19 -07:00
Thomas Harte
6b0dd19442
Name file appropriately: the logo comes from Kickstart.
2021-10-09 08:02:15 -07:00
Thomas Harte
9336ffe216
Take a stab at index-hole sync.
2021-10-09 08:01:02 -07:00
Thomas Harte
eb157f15f3
Adds index hole interrupt.
2021-10-09 04:08:59 -07:00
Thomas Harte
d6e2a3f425
Make a first attempt to spool into RAM.
2021-10-08 18:11:47 -07:00
Thomas Harte
b47ca13ed3
Push disk data onwards.
2021-10-08 17:18:11 -07:00
Thomas Harte
67546c4d6e
Per the HRM, the index hole is connected to CIA B, potentially to raise an interrupt.
2021-10-08 17:12:37 -07:00
Thomas Harte
f72deb0a5c
Correct RDY position.
2021-10-08 04:32:13 -07:00
Thomas Harte
616ccbb878
Correct ID bit placement, multiplex with motor state.
...
The latter per my reading of http://www.primrosebank.net/computers/amiga/upgrades/amiga_upgrades_storage_fdis.htm
2021-10-08 04:05:57 -07:00
Thomas Harte
5899af0038
Starts accumulating disk data.
2021-10-07 05:11:32 -07:00
Thomas Harte
ed303310bb
Spell out slightly more; this makes debugging a touch easier.
2021-10-06 13:40:48 -07:00
Thomas Harte
33ff4f3b5c
Eliminate drive copies.
2021-10-06 13:40:28 -07:00
Thomas Harte
20bad38d42
Add drive activity lights.
2021-10-06 04:54:40 -07:00
Thomas Harte
92a07398cd
I think CHNG works the other way around.
2021-10-06 04:47:52 -07:00
Thomas Harte
ce8f782577
Corrects meaning of IBM-style RDY.
2021-10-06 04:42:44 -07:00
Thomas Harte
e961d0b4a3
Switch RDY type.
2021-10-06 04:41:09 -07:00
Thomas Harte
2253ff656a
Adds route for inserting disks.
2021-10-05 16:12:30 -07:00
Thomas Harte
18631399ad
Attempts to clock the disk controller.
2021-10-05 15:38:56 -07:00
Thomas Harte
ad4afcdcd5
Switch stepping direction.
...
Empirically, based on the actions of Kickstart, and assuming my confusion is because the relevant signal is active low.
2021-10-05 15:23:48 -07:00
Thomas Harte
2cf5bcc5db
Clarify logic somewhat.
2021-10-05 15:20:05 -07:00
Thomas Harte
1180ad7662
Disables a couple of now-trustworthy LOGs.
2021-10-05 06:51:47 -07:00
Thomas Harte
5463cd1ae3
Attempts to support stepping and head selection.
2021-10-05 06:36:17 -07:00
Thomas Harte
647ec770ce
Implements motor latching, drive ID shift registers.
2021-10-05 05:12:01 -07:00
Thomas Harte
e47bec2e65
Switch CIA B ports over.
2021-10-05 03:38:11 -07:00
Thomas Harte
6566936be9
Be overt about the intended interface.
2021-10-04 16:45:33 -07:00
Thomas Harte
674941abdf
Starts to add a disk controller.
2021-10-04 16:45:05 -07:00
Thomas Harte
b3f0ca39ed
Adds some unused drives.
2021-10-04 08:12:13 -07:00
Thomas Harte
5ccb512883
Moves the CIAs into the Chipset class.
...
This reflects the routing of interrupt signals for now, but also prepares for the addition of disk drives.
2021-10-04 06:44:54 -07:00
Thomas Harte
da286d5ae8
Switch spaces to tabs.
2021-10-04 05:27:25 -07:00
Thomas Harte
73e45511dc
Add missing #include.
2021-10-04 05:26:38 -07:00
Thomas Harte
a282a51673
Remove last of the direct printf'ing.
2021-09-30 02:42:59 -04:00
Thomas Harte
b7b13e20d1
Single column blits should use both masks.
2021-09-29 22:49:35 -04:00
Thomas Harte
ad90c6b6ce
Now that this is getting close, don't stop at the first error.
2021-09-29 22:19:34 -04:00
Thomas Harte
402fa41bc0
Corrects initial error value.
2021-09-29 22:19:17 -04:00
Thomas Harte
0b9ebafc0f
Flip bit deserialisation order.
2021-09-28 22:12:13 -04:00
Thomas Harte
140e24ef15
Grab further copy flags.
2021-09-28 22:11:58 -04:00
Thomas Harte
0c998d60cb
Correct test logic for line draws that repeatedly write to the same address.
2021-09-28 21:45:55 -04:00
Thomas Harte
ffcd2ea10c
Attempts more properly to implement line mode.
2021-09-28 21:39:09 -04:00
Thomas Harte
cb460de94d
Makes bad first attempt at a Bresenham inner loop.
2021-09-27 22:06:00 -04:00
Thomas Harte
f6624bf776
Edges mildly closer to line output.
2021-09-26 19:18:12 -04:00
Thomas Harte
b4b6c4d86f
Attempts to support left and right masks.
2021-09-26 18:42:08 -04:00
Thomas Harte
759689ff31
Fix line mode flag, add busy status.
2021-09-26 18:16:00 -04:00
Thomas Harte
1dfc36f311
Flip loop, add modulo mappings.
2021-09-26 18:15:32 -04:00
Thomas Harte
1c03ff1d37
Fix bltdptl to bltbptl misstatement; remove pre-DMA writes.
2021-09-26 18:14:50 -04:00
Thomas Harte
19dd2f92bd
Implements test case. Failing at present, naturally.
2021-09-25 21:52:41 -04:00
Thomas Harte
acfaa016a0
Adds a capture of traffic leading up to the Workbench boot logo.
...
Around which to construct a test case.
2021-09-25 18:10:07 -04:00
Thomas Harte
732761433a
Merge branch 'master' into HeaderOnly6502
2021-09-23 23:00:11 -04:00
Thomas Harte
9012a7f5e1
Merge branch 'master' into Amiga
2021-09-23 23:00:03 -04:00
Thomas Harte
e957b471b2
Merge pull request #989 from TomHarte/Xcode13
...
Resolves Clang 13 implicit conversion warnings.
2021-09-23 22:59:42 -04:00
Thomas Harte
e5a5faa417
Resolves Clang 13 implicit conversion warnings.
2021-09-23 22:53:41 -04:00
Thomas Harte
313dbe05e0
Switch to more consistent inlining.
2021-09-23 22:36:15 -04:00
Thomas Harte
adf7124e2c
Eliminate 6502Base.cpp.
2021-09-23 22:33:33 -04:00
Thomas Harte
c4ab2bbeed
Hard-code fetch window width. For now.
2021-09-23 22:06:13 -04:00
Thomas Harte
42ef459e20
Resolve resting values.
2021-09-23 22:05:59 -04:00
Thomas Harte
cad1a9e0f1
Correct bit test.
2021-09-23 20:42:31 -04:00
Thomas Harte
f1d514470d
Add note to future self.
2021-09-23 20:29:39 -04:00
Thomas Harte
9a7a54f22f
Take alternative guess as to meaning of 'use' bits.
2021-09-23 18:42:12 -04:00
Thomas Harte
137d1c61bd
Allow for channel enables and blitting direction.
2021-09-23 18:38:37 -04:00
Thomas Harte
adc071ed7a
Fix: modulos are 15-bit signed, the minterms are also in regular BLTCON0.
2021-09-23 18:30:35 -04:00
Thomas Harte
e06f470044
Ensure no implicit conversion from int to IntT.
2021-09-23 18:30:04 -04:00
Thomas Harte
ab69fe56c9
Take a first shot at magical instant blitting.
2021-09-23 18:13:51 -04:00
Thomas Harte
60bad22a91
Correct fetch window.
2021-09-23 18:13:24 -04:00
Thomas Harte
7092429f7c
Added some notes to self on line mode.
2021-09-20 23:08:26 -04:00
Thomas Harte
fa800bb809
Introduces code for minterm application.
2021-09-20 19:13:23 -04:00
Thomas Harte
e15f1103a0
Takes a shot at low resolution shifting.
2021-09-20 19:00:52 -04:00
Thomas Harte
a4263b5a8c
Ties bitplane collection to line position.
...
Outgoing bug: incrementing the video relative offset too often, due to cycles that are discovered to be CPU-targetted.
2021-09-19 21:55:45 -04:00
Thomas Harte
3d85f820f4
Add missing file to kiosk project.
2021-09-16 21:29:11 -04:00
Thomas Harte
245b7baa61
Moves the Copper into its own file.
2021-09-16 21:17:23 -04:00
Thomas Harte
0eeaaa150a
Correct Copper start address.
2021-09-16 21:01:37 -04:00
Thomas Harte
692d87f446
Attempts to restrict blitter slot allocation.
2021-09-16 19:56:28 -04:00
Thomas Harte
6572efe2a7
Clarifies word addressing.
2021-09-16 08:24:52 -04:00
Thomas Harte
8aac2bd029
Stubs in serial port status.
2021-09-14 21:53:07 -04:00
Thomas Harte
add11db369
Factors out DMADevice, which is now a parent of Blitter.
2021-09-14 20:51:32 -04:00
Thomas Harte
e47eab1d40
Merge branch 'master' into Amiga
2021-09-14 20:27:59 -04:00
Thomas Harte
2f86dfdf2b
Merge pull request #987 from TomHarte/IIgsImprovements
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Further iterates the IIgs towards full functionality.
2021-09-14 20:27:25 -04:00
Thomas Harte
fa71ae3174
Add apology.
2021-09-14 20:23:36 -04:00
Thomas Harte
dfcd1508c9
Establishes valid initial BRAM.
2021-09-10 19:56:20 -04:00
Thomas Harte
0ca4631279
Switch to zero-initialised state; be more careful about resetting data.
2021-09-09 23:08:13 -04:00
Thomas Harte
7e5fc4444a
Default to ROM01.
2021-09-09 22:09:09 -04:00
Thomas Harte
a6221ca322
Reload data only if an output is found.
2021-09-09 22:07:03 -04:00
Thomas Harte
d8e42c4379
Tweak guess at initial state.
2021-09-09 22:06:36 -04:00
Thomas Harte
3bf109ae0b
Merge pull request #986 from TomHarte/IIgsSync
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Stabilises Apple IIgs display.
2021-09-09 20:14:40 -04:00
Thomas Harte
dd37fa49a0
Stabilises Apple IIgs display.
2021-09-09 20:08:15 -04:00
Thomas Harte
3227ec72a2
Merge branch 'master' into Amiga
2021-09-08 21:08:47 -04:00
Thomas Harte
ee324c3d89
Merge pull request #985 from TomHarte/68000Improvements
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68000: fix E alignment, expand Microcycle::apply.
2021-09-08 21:08:33 -04:00
Thomas Harte
863971f944
68000: fix E alignment, expand Microcycle::apply.
2021-09-08 21:03:37 -04:00
Thomas Harte
fd70f7ad43
Attempts to make pixel content observeable.
2021-09-08 20:57:26 -04:00
Thomas Harte
6e034c9b7f
At least manages to place a pixel region on screen.
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Albeit that I've suddenly realised that I've failed properly to think about high-res versus low-res.
2021-08-11 20:31:37 -04:00
Thomas Harte
52e375a985
Move towards playfield decoding.
2021-08-11 18:47:35 -04:00
Thomas Harte
635c1eacd5
Merge branch 'master' into Amiga
2021-08-11 17:31:17 -04:00
Thomas Harte
f49ba18627
Merge pull request #983 from TomHarte/MachinePickerLayout
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macOS: cleans up layout of machine picker.
2021-08-11 17:30:58 -04:00
Thomas Harte
6dbce96781
Switch to non-breaking space, to avoid orphan word.
2021-08-11 17:28:37 -04:00
Thomas Harte
9ec42f0f8f
Cleans up bottom constraints.
2021-08-11 17:12:01 -04:00
Thomas Harte
10a5e7313f
Makes a buggy first attempt at bitplane data collection.
2021-08-10 21:28:48 -04:00
Thomas Harte
ec9cb21fae
Starts towards bitplane collection.
2021-08-10 19:01:41 -04:00
Thomas Harte
fdd02ad6a6
Neaten, slightly.
2021-08-10 09:20:34 -04:00
Thomas Harte
76e9fcc94a
Obey blitter DMA-enable mask.
2021-08-10 09:19:15 -04:00
Thomas Harte
e412927415
Logs a bit more from the Blitter, gives it access to slots.
2021-08-10 07:17:01 -04:00
Thomas Harte
dda154c7c6
Adds nonsense disk reads, which seems to lead to bitplane and blitter requests.
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Progress, at last!
2021-08-09 20:31:14 -04:00
Thomas Harte
9215535bee
Adds a container for the disk controller.
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Thereby appears to prove that my Amiga is getting as far as attempting to load from floppy.
2021-08-09 17:35:09 -04:00
Thomas Harte
27726fd2d1
Merge branch 'master' into Amiga
2021-08-09 17:24:06 -04:00
Thomas Harte
77befb7f8e
Correct Atari ST text placement; add missing Enteprise constraint.
2021-08-09 17:14:37 -04:00
Thomas Harte
86c6248b48
Merge branch 'master' into Amiga
2021-08-09 17:09:04 -04:00
Thomas Harte
f2af8ff25d
Merge pull request #981 from TomHarte/ColourPrecision
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Increase precision of phase interpolation.
2021-08-09 17:08:17 -04:00
Thomas Harte
7d8894415c
Increase precision of phase interpolation.
2021-08-09 15:48:27 -04:00
Thomas Harte
f8380d2d4c
Add 8250 feature of 'count, regardless'.
2021-08-08 22:32:41 -04:00
Thomas Harte
5cc25d0846
Adds a further sanity assert.
2021-08-08 21:52:52 -04:00
Thomas Harte
1502c4530e
Takes a further step towards real timing.
2021-08-08 21:52:28 -04:00
Thomas Harte
c1df4d1c0b
Mirroring is correct.
2021-08-08 20:20:12 -04:00
Thomas Harte
1f9e41e9cb
Ensure TOD isn't firing from power-on.
2021-08-08 18:51:58 -04:00
Thomas Harte
e402e690b0
Assume and test that divide-by-zero posts the PC of the offending instruction.
2021-08-07 17:51:00 -04:00
Thomas Harte
6a15bb15ca
Adds a simpler way of deferring single values.
2021-08-07 17:29:21 -04:00
Thomas Harte
3255fc91fa
Merge branch 'Amiga' of github.com:TomHarte/CLK into Amiga
2021-08-07 17:00:54 -04:00
Thomas Harte
7f2610c4fc
Disambiguates serial control logs.
2021-08-07 16:57:30 -04:00
Thomas Harte
79bd3eb6ae
Merge branch 'Amiga' of github.com:TomHarte/CLK into Amiga
2021-08-07 16:56:40 -04:00
Thomas Harte
b11dd6950c
Adds an entry for DiagROM.
2021-08-07 16:56:18 -04:00
Thomas Harte
98bd6fc240
Adds a further logging hint.
2021-08-06 23:16:06 -04:00
Thomas Harte
8be053fd35
Fixes top constraint for Atari ST.
2021-08-06 22:57:45 -04:00
Thomas Harte
99fee22a9f
Adjusts defaults.
2021-08-06 22:13:21 -04:00
Thomas Harte
084d002353
Adds the Amiga to macOS File -> New...
2021-08-06 21:58:31 -04:00
Thomas Harte
dcbc9847a3
Attempts to get E synchronisation correct.
2021-08-05 20:08:34 -04:00
Thomas Harte
db3c158215
Further increases logging.
2021-08-05 20:07:14 -04:00
Thomas Harte
25e2bd307a
Sets VPA for CIA accesses; logs a little more.
2021-08-05 20:06:48 -04:00
Thomas Harte
b9f78f5d33
Fix final timer B test.
2021-08-03 22:27:23 -04:00
Thomas Harte
b4ec9d70da
Adds the CNT input.
2021-08-03 22:19:41 -04:00
Thomas Harte
738999a8b7
Further expands list of applied tests.
2021-08-03 22:08:50 -04:00
Thomas Harte
dd91d793d9
Correct typo.
2021-08-03 21:45:44 -04:00
Thomas Harte
1f0bf1b32d
Merge pull request #980 from adamsmasher/improve-apple-ii-kb
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Improve raw keyboard handling for original Apple ][
2021-08-03 21:14:06 -04:00
Thomas Harte
8e51e8eb77
Does just a touch of 6526 TOD work.
2021-08-03 21:13:08 -04:00
Thomas Harte
6210605bc7
Transfers full TOD responsibility onto the chip-specific templates.
2021-08-03 19:10:09 -04:00
Thomas Harte
0245b040b0
Splits TOD storage by model.
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TOD storage will probably end up being a full-on class.
2021-08-03 18:50:58 -04:00
Thomas Harte
34c1cc5693
Adds entry points for all remaining tests.
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Failing now: the TB123s, which are TOD related, both CIA2 tests, and CIA1TAB (which I think needs me to implement Port B output toggling).
2021-08-03 17:19:35 -04:00
Thomas Harte
8795719c18
This counts reloads, most accurately.
2021-08-03 17:12:08 -04:00
Thomas Harte
6bbbf43341
At least attempts to chain correctly.
2021-08-03 17:03:58 -04:00
Thomas Harte
f0ef45f0ca
Introduces two further tests.
2021-08-03 16:58:51 -04:00
Thomas Harte
ee6039bfa5
Writes to a timer _during reload_ now have effect.
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Net: one CIA test passed.
2021-08-03 16:57:05 -04:00
Thomas Harte
ef58ce6277
Gets a bit more rigorous about the clocking stage.
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Albeit without advancing relative to the test.
2021-08-02 21:04:00 -04:00
Thomas Harte
15de5e98c4
Adds [partial] test for whether counters are linked.
2021-08-02 20:17:37 -04:00
Thomas Harte
38848ca2db
Rationalises reload logic and cuts storage.
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Failure point is now chaining, I think.
2021-08-02 20:14:01 -04:00
Thomas Harte
77c627e822
Ensure that reading the interrupt flags really clears the master bit.
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Also makes some guesses on one-shot and reload timing. Alas the test isn't in itself specific enough to be more systematic here.
2021-08-02 07:47:08 -04:00
Thomas Harte
c640132699
Reinstates clocking.
2021-08-01 21:35:08 -04:00
Thomas Harte
60b09d9bb0
Increases compile-time logging options.
2021-08-01 21:22:33 -04:00
Thomas Harte
57dd38aef2
Reintroduces reload-on-off, adds interrupt delay.
2021-08-01 21:09:02 -04:00
Thomas Harte
460a6cb6fe
Attempts a more literal implementation.
2021-08-01 18:14:10 -04:00
Adam Smith
fdb676da4e
.
2021-08-01 00:26:14 -07:00
Thomas Harte
26aaddaa33
Adds further documentation.
2021-07-30 21:34:22 -04:00
Thomas Harte
e51151e558
Adds readme related to C64 ROMs.
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Necessary for the Lorenz 6526 tests. I've no current plans to work on the C64.
2021-07-30 21:23:12 -04:00
Thomas Harte
f576baf214
I'm not yet sure this is the best approach, but starts trying to make use of Lorenz's 6526 tests.
2021-07-30 21:21:16 -04:00
Thomas Harte
5c1ac05170
Add documentation.
2021-07-30 21:20:45 -04:00
Thomas Harte
1bae4973bc
Post the serial control write onwards.
2021-07-30 18:24:27 -04:00
Thomas Harte
3d9f86c584
Begins keyboard sketches and notes.
2021-07-30 18:23:15 -04:00
Thomas Harte
3514e537ca
Minor logging tweaks.
2021-07-30 18:22:59 -04:00
Thomas Harte
3d160ce85f
Add another potential warning.
2021-07-30 18:21:38 -04:00
Thomas Harte
b78090ec76
Fixes IOPortsAndTimers classification.
2021-07-28 19:39:42 -04:00
Thomas Harte
759007ffc1
Attempts to route CIA interrupts.
2021-07-28 19:36:30 -04:00
Thomas Harte
37a55c3a77
Corrects 6526 interrupt control write.
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This seems to imply that the 6526 should be interrupting too.
2021-07-28 19:26:02 -04:00
Thomas Harte
69ae9d72c8
Remove dead non-access.
2021-07-27 22:27:20 -04:00
Thomas Harte
604232acd9
Establish appropriate word-size mask.
2021-07-27 22:23:38 -04:00
Thomas Harte
82205d71cc
Breaks up loop for arithmetic simplicity.
2021-07-27 21:59:27 -04:00
Thomas Harte
402eab10f8
Breaks video output while attempting to pull it into the main loop.
2021-07-27 21:33:07 -04:00
Thomas Harte
b6bf4d73ad
Blitter-finished bit aside, attempts to complete the Copper.
2021-07-27 21:10:14 -04:00
Thomas Harte
5425b5c423
Adds some form of WAITing to the Copper.
2021-07-27 19:32:55 -04:00
Thomas Harte
29cd8504ca
Implements enough Copper to get a first store.
2021-07-27 19:06:16 -04:00
Thomas Harte
3544746934
Modifies interface, starts on scheduler.
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Probably corrects the pixel clock, which I think was scaled up by a factor of 4.
2021-07-27 16:41:18 -04:00
Thomas Harte
d8f814f1c4
If I'm going to push only a single colour, might as well make it fast.
2021-07-26 21:19:43 -04:00
Thomas Harte
a43175125a
Assuming I'm going to keep this synchronous, extends function signature.
2021-07-26 20:13:06 -04:00
Thomas Harte
1d03bc560a
Stores the colour palette, uses entry 0 as my new always output.
2021-07-26 18:59:11 -04:00
Thomas Harte
3832acf6e3
Produces a static white box, at least.
2021-07-26 18:51:01 -04:00
Thomas Harte
7894b50321
Starts towards an actual pixel output loop.
2021-07-26 18:44:20 -04:00
Thomas Harte
ffded619e6
Returns track 0 found, as a guess.
2021-07-26 18:44:01 -04:00
Thomas Harte
bcb7bb5cce
Improves logging further.
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To investigate the new perpetual loop.
2021-07-26 17:02:30 -04:00
Thomas Harte
87dcd82f69
Makes a first attempt at some sort of interrupt functionality.
2021-07-26 16:40:42 -04:00
Thomas Harte
e671cc6056
Add stubs for joystick/mouse querying.
2021-07-26 16:21:51 -04:00
Thomas Harte
5da89b88a6
Add missing space.
2021-07-25 22:17:55 -04:00
Thomas Harte
5d60c1f20b
Stubs in Paula.
2021-07-25 22:16:31 -04:00
Thomas Harte
7fd00165c9
Switch to [hard-coded] PAL, for now.
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In the hope that I get to see some graphics soon, this should better conform to my expectations.
2021-07-25 20:41:51 -04:00
Thomas Harte
34d4420e8c
Correct reading of top byte of counter 2.
2021-07-25 20:41:15 -04:00
Thomas Harte
20da194fab
Log slightly more accurately.
2021-07-25 19:59:24 -04:00
Thomas Harte
8d2d4c850f
Revoke temporary debugging.
2021-07-25 19:59:10 -04:00
Thomas Harte
b7bed027d7
Ensures the value initially loaded to A7 is aligned.
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This is a bit of a guess; it's likely to be true though per the rule that A7 is always kept aligned.
2021-07-25 19:55:23 -04:00
Thomas Harte
fcd6b7b0ea
Takes further aim at the conters.
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I think test cases are needed, probably.
2021-07-24 16:06:49 -04:00
Thomas Harte
ceca32ceb3
Takes a guess at one-shot mode.
2021-07-24 15:53:18 -04:00
Thomas Harte
e3bb9fc1d7
Increase logging.
2021-07-23 23:10:00 -04:00
Thomas Harte
77a8ddb95c
Edges towards working counters.
2021-07-23 22:43:47 -04:00
Thomas Harte
c733a4dbf8
Beefs up interrupt awareness.
2021-07-23 21:58:52 -04:00
Thomas Harte
d898a43dff
Implements time-of-day counters, provisionally.
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Interrupts to do.
2021-07-23 21:24:07 -04:00
Thomas Harte
6216d53b1a
Adds a faster flushing HalfCycles -> Cycles conversion.
2021-07-23 20:07:57 -04:00
Thomas Harte
86c30769d9
Add a divide-by-ten for the CIAs.
2021-07-23 19:25:53 -04:00
Thomas Harte
956a6dbd64
Improve commentary.
2021-07-23 19:23:54 -04:00
Thomas Harte
68fe19818e
Expose more information about the E clock state.
2021-07-23 19:22:00 -04:00
Thomas Harte
de208ead4e
Stubs in enough to get back into a persistent loop.
2021-07-22 22:00:53 -04:00
Thomas Harte
69d62560b4
Adds comment to avoid potential future error.
2021-07-22 22:00:33 -04:00
Thomas Harte
87d2fc1491
Adds enough raster position to return something.
2021-07-22 21:45:51 -04:00
Thomas Harte
2bc9af09e1
Factors out the chipset.
2021-07-22 21:16:23 -04:00
Thomas Harte
26f4758523
Makes a further accommodation for PermitRead/Write.
2021-07-22 21:11:25 -04:00
Thomas Harte
6123349b79
Stubs in control registers and disables exit-on-miss.
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I think I may be running up against the limits of stubbing now. Probably time to implement some stuff.
2021-07-22 19:28:01 -04:00
Thomas Harte
d1ac54fe92
Stubs in sprite containers.
2021-07-22 19:00:26 -04:00
Thomas Harte
9468adf737
Stubs in Copper addresses.
2021-07-22 18:51:23 -04:00
Thomas Harte
e85db40b0f
Sketches out a blitter class.
2021-07-22 18:43:07 -04:00
Thomas Harte
b3d55cc16d
Adds non-committal reads for some write-only registers.
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The hardware now proceeds to trying to talk to the Blitter. So that's next.
2021-07-22 16:10:30 -04:00
Thomas Harte
56b62a5e49
Adds a dummy interrupt control register.
2021-07-22 16:09:32 -04:00
Thomas Harte
3ee1fc544f
Fix: (1) memory base adjustment; (2) out-of-bounds writes.
2021-07-21 21:49:20 -04:00
Thomas Harte
5401744dc0
Add additional asserts.
2021-07-21 21:47:44 -04:00
Thomas Harte
fe10a10ac2
Correct address on stack upon priviliege exception.
2021-07-21 21:46:55 -04:00
Thomas Harte
ba2e5a97a9
Provisionally adds a status LED.
2021-07-19 22:31:36 -04:00
Thomas Harte
4515d1220c
Switches CIA A/B byte connections; applies reset to memory map.
2021-07-19 22:17:40 -04:00
Thomas Harte
486959bce8
With minor additional logging, it appears the Amiga just keeps resetting itself.
2021-07-19 21:50:35 -04:00
Thomas Harte
e1a410bf3d
Further mildly increases logging.
2021-07-19 20:54:32 -04:00
Thomas Harte
3767cc7c0b
Increase logging; fix set/clear of interrupt enable mask.
2021-07-19 19:03:37 -04:00
Thomas Harte
96b0ce9ef2
Merge branch 'master' into Amiga
2021-07-18 22:16:05 -04:00
Thomas Harte
038ed0551e
Merge pull request #979 from TomHarte/Warnings
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Resolve all dangling GCC warnings.
2021-07-18 22:15:45 -04:00
Thomas Harte
cfaf4a8a65
Add advised brackets; clarify type punning.
2021-07-18 22:11:11 -04:00
Thomas Harte
22dd8a8847
Stubs onward to a second endless loop.
2021-07-18 20:55:33 -04:00
Thomas Harte
b2ae8e7a4a
Adds a type for the operation bitfield.
2021-07-18 20:54:54 -04:00
Thomas Harte
3e2bac8129
Stubs in enough to get to a permanent loop.
2021-07-18 20:25:43 -04:00
Thomas Harte
50b9d0e86d
Logically, I think this should be unsigned.
2021-07-18 20:25:22 -04:00
Thomas Harte
a030d9935e
Adds port input.
2021-07-18 20:25:04 -04:00
Thomas Harte
c425dec4d5
Makes some attempt to get as far as the overlay being disabled.
2021-07-18 17:17:41 -04:00
Thomas Harte
67d53601d5
Latch and return data direction.
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Albeit with no port-handling effect yet.
2021-07-18 12:23:47 -04:00
Thomas Harte
622cca0acf
Adds sufficient address decoding to print a more helpful exit message.
2021-07-18 12:13:56 -04:00
Thomas Harte
48999c03a5
Adds concept of time, captured port handler.
2021-07-18 11:49:10 -04:00
Thomas Harte
377cc7bdcd
Start to introduce a 6526/8250.
2021-07-18 11:36:13 -04:00
Thomas Harte
a5d0976c2d
Eliminate unused #includes.
2021-07-18 11:35:57 -04:00
Thomas Harte
ae05010255
Improve indentation.
2021-07-18 11:29:26 -04:00
Thomas Harte
66cacbd0e0
Be overt about the type being supplied.
2021-07-18 11:28:18 -04:00
Thomas Harte
b1616be4b8
Gets to what is probably a CIA access?
2021-07-17 21:36:20 -04:00
Thomas Harte
a0a9a72d8f
Begins sketching out a memory mapper.
2021-07-17 21:10:06 -04:00
Thomas Harte
0cfc7f732c
Extends to support read/write permissions in apply
.
2021-07-17 21:09:52 -04:00
Thomas Harte
f7de6f790c
Meanders vaguely towards a memory map.
2021-07-16 21:42:17 -04:00
Thomas Harte
d1f3b5ed80
Obtains a Kickstart ROM, adds a 68000.
2021-07-16 21:07:12 -04:00
Thomas Harte
7925dcc5a2
Advances far enough for the Amiga to be autonomous.
2021-07-16 20:49:12 -04:00
Thomas Harte
6ade36bf09
Adds an empty shell of a machine.
2021-07-16 20:30:48 -04:00
Thomas Harte
c52945aab5
Adds passthrough for Amiga media.
2021-07-16 20:15:36 -04:00
Thomas Harte
2b0a4055f7
Makes an attempt at Amiga ADF encoding.
2021-07-16 20:07:17 -04:00
Thomas Harte
7cb16a3fc5
Introduces a shell for Amiga ADF decoding.
2021-07-16 18:11:07 -04:00
Thomas Harte
0b80c1988b
Add Amiga enums.
2021-07-16 17:59:08 -04:00
Thomas Harte
eab9bc1503
Make implicit conversion explicit.
2021-07-16 17:45:14 -04:00
Thomas Harte
5bfedff8d1
Mutate dangling printf to a LOG.
2021-07-16 17:32:05 -04:00
Thomas Harte
c8638c0ffb
Merge pull request #977 from TomHarte/MouseFade
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Slightly adjusts macOS mouse hiding semantics.
2021-07-16 17:25:59 -04:00
Thomas Harte
8a95b91e2a
Merge pull request #976 from TomHarte/DiskIIClocking
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Correct Disk II sleeping test to allow for spin-down.
2021-07-16 17:22:04 -04:00
Thomas Harte
c226be612f
Slightly adjusts mouse hiding semantics.
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This allows the Macintosh and ST to fade out volume and settings even without having captured the mouse.
2021-07-16 17:21:25 -04:00
Thomas Harte
c8699d9770
Correct Disk II sleeping test to allow for spin-down.
2021-07-16 17:12:57 -04:00
Thomas Harte
a0799e14cc
Merge pull request #975 from TomHarte/LEDStyles
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Classify some LEDs as 'persistent'
2021-07-15 22:05:14 -04:00
Thomas Harte
dea6048849
Add documentation.
2021-07-15 22:00:10 -04:00
Thomas Harte
813e252539
Ignore hidden files.
2021-07-15 21:57:25 -04:00
Thomas Harte
b41e29a83b
Slows CPC typer to avoid dropped characters.
2021-07-15 21:54:02 -04:00
Thomas Harte
d35c7ad127
Take advantage of persistence flag for more intelligent LED presentation.
2021-07-15 21:49:11 -04:00
Thomas Harte
ea63415d0e
Exposes persistent LED flag to Swift.
2021-07-15 21:34:14 -04:00
Thomas Harte
52ea3b741c
Introduces a presentation flag for LEDs.
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All existing receivers ignore it.
2021-07-15 21:26:02 -04:00
Thomas Harte
2731ca8c92
Merge pull request #974 from TomHarte/KickstartROMs
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Introduces Amiga ROMs to the catalogue.
2021-07-15 21:14:50 -04:00
Thomas Harte
af1ade9433
Introduces Amiga ROMs to the catalogue.
2021-07-15 21:09:20 -04:00
Thomas Harte
fc248951cc
Merge pull request #973 from TomHarte/TransientActivity
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Converts activity indicators to transient in-window presentation.
2021-07-15 20:15:33 -04:00
Thomas Harte
84547ee1c1
Reduce spurious in-window appearances.
2021-07-15 19:53:40 -04:00
Thomas Harte
a42848c62f
Add windowed LED reappearance upon blink.
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Also fix crash-at-startup for fullscreen.
2021-07-15 19:51:23 -04:00
Thomas Harte
c7b5d69431
Add extra usage hint.
2021-07-15 19:50:43 -04:00
Thomas Harte
81374b70b5
Switch to transient LED presentation in windowed mode.
2021-07-15 19:22:23 -04:00
Thomas Harte
47a530fd5c
Fixes LED ordering.
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Still work to do on capturing the proper window title.
2021-07-14 22:01:42 -04:00
Thomas Harte
58451d7c0c
Attempts to incorporate LEDs into the window title when in windowed mode.
2021-07-14 21:43:58 -04:00
Thomas Harte
5c8f8c76fe
Thus ends the View menu.
2021-07-14 21:02:58 -04:00
Thomas Harte
ae1d1bdb5b
Wires up controller for QuickLoadOptions.
2021-07-14 21:02:04 -04:00
Thomas Harte
33cc1154a2
Simplify ViewFader
and avoid second-guessing when to hard-set opacity.
2021-07-14 20:50:41 -04:00
Thomas Harte
4bc0b75c30
Ensure Macintosh controller is effective.
2021-07-14 20:50:12 -04:00
Thomas Harte
eb8ec1efb1
Makes ViewFader
the full master of fading.
2021-07-14 19:03:44 -04:00
Thomas Harte
616f8efc47
Improves optional hysteresis.
2021-07-13 23:40:15 -04:00
Thomas Harte
29e4369420
Attempts to switch activity indicators to smart in-window presentation.
2021-07-13 23:32:00 -04:00
Thomas Harte
bd7f7bc8d7
Remove dead 'show options'.
2021-07-13 22:28:03 -04:00
Thomas Harte
e689ca92c4
Minor rearrangements, for cleanliness.
2021-07-13 22:26:50 -04:00
Thomas Harte
4ef3005072
Merge pull request #972 from TomHarte/InWindowOptions
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macOS: moves machine options into the emulation window
2021-07-13 22:06:08 -04:00
Thomas Harte
174c837767
Switches to a logarithmic volume dial.
2021-07-13 21:45:07 -04:00
Thomas Harte
486bb911a9
Adapts ZX80/81 options.
2021-07-13 21:26:20 -04:00
Thomas Harte
754221d697
Adapts QuickLoadOptions.
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Not that it currently seems to be used.
2021-07-13 21:21:02 -04:00
Thomas Harte
3c36c90729
Adapts QuickLoadCompositeOptions.
2021-07-13 21:17:52 -04:00
Thomas Harte
3d1d15a25b
Updates the Oric options.
2021-07-13 19:32:23 -04:00
Thomas Harte
000d99f26c
Adapts the Macintosh options.
2021-07-13 19:26:29 -04:00
Thomas Harte
524e2abc8c
Adapts composite options.
2021-07-13 19:19:47 -04:00
Thomas Harte
00bab98e09
Converts the Apple II options into an in-window view.
2021-07-13 19:14:54 -04:00
Thomas Harte
6d98349be1
Fully invests in options controllers, distinct from the views.
...
Per MVC, I should have been doing something closer to this from day one.
2021-07-13 19:04:24 -04:00
Thomas Harte
d24d153c08
Use modern constraint specification, add layers to XIBs.
2021-07-12 22:55:53 -04:00
Thomas Harte
b01561712c
Tightens spacing slightly.
2021-07-12 22:49:42 -04:00
Thomas Harte
324edcb391
Starts towards using an in-window options panel.
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With the same fade in/out behaviour as the volume control.
2021-07-12 22:38:08 -04:00
Thomas Harte
6e62e4e296
Merge branch 'master' of github.com:TomHarte/CLK
2021-07-12 22:01:25 -04:00
Thomas Harte
f81ecbf4a0
Force icons back to white.
2021-07-12 22:01:19 -04:00
Thomas Harte
4370456323
Switch to an NSVisualEffectView for volume controls.
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It provides a background that better contrasts with arbitrary content.
2021-07-12 21:28:04 -04:00
Thomas Harte
a424ed7c00
Makes for slightly more straightforward constraints.
2021-07-12 19:25:06 -04:00
Thomas Harte
a2065f59a1
Adds a 0.1 second pause before exit-related menu fadeout.
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This is because the system may post a quick succession of exits and enters if the view hierarchy changes.
2021-07-12 19:12:04 -04:00
Thomas Harte
c1bd7f5c67
Pull release links up closer to the lede.
2021-07-12 10:03:03 -04:00