Record updated version number.

Fix order of `if` tests.

Analyser/Static/AmstradCPC/StaticAnalyser.cpp

@@ -228,26 +228,13 @@ Analyser::Static::TargetList Analyser::Static::AmstradCPC::GetTargets(const Medi
 	}
 
 	if(!media.disks.empty()) {
-		Storage::Disk::CPM::ParameterBlock data_format;
-		data_format.sectors_per_track = 9;
-		data_format.tracks = 40;
-		data_format.block_size = 1024;
-		data_format.first_sector = 0xc1;
-		data_format.catalogue_allocation_bitmap = 0xc000;
-		data_format.reserved_tracks = 0;
-
-		Storage::Disk::CPM::ParameterBlock system_format;
-		system_format.sectors_per_track = 9;
-		system_format.tracks = 40;
-		system_format.block_size = 1024;
-		system_format.first_sector = 0x41;
-		system_format.catalogue_allocation_bitmap = 0xc000;
-		system_format.reserved_tracks = 2;
+		const auto data_format = Storage::Disk::CPM::ParameterBlock::cpc_data_format();
+		const auto system_format = Storage::Disk::CPM::ParameterBlock::cpc_system_format();
 
 		for(auto &disk: media.disks) {
-			// Check for an ordinary catalogue.
+			// Check for an ordinary catalogue, making sure this isn't actually a ZX Spectrum disk.
 			std::unique_ptr<Storage::Disk::CPM::Catalogue> data_catalogue = Storage::Disk::CPM::GetCatalogue(disk, data_format);
-			if(data_catalogue) {
+			if(data_catalogue && !data_catalogue->is_zx_spectrum_booter()) {
 				InspectCatalogue(*data_catalogue, target);
 				target->media.disks.push_back(disk);
 				continue;
@@ -261,7 +248,7 @@ Analyser::Static::TargetList Analyser::Static::AmstradCPC::GetTargets(const Medi
 
 			// Failing that check for a system catalogue.
 			std::unique_ptr<Storage::Disk::CPM::Catalogue> system_catalogue = Storage::Disk::CPM::GetCatalogue(disk, system_format);
-			if(system_catalogue) {
+			if(system_catalogue && !system_catalogue->is_zx_spectrum_booter()) {
 				InspectCatalogue(*system_catalogue, target);
 				target->media.disks.push_back(disk);
 				continue;

Analyser/Static/AmstradCPC/Target.hpp

@@ -20,10 +20,18 @@ struct Target: public Analyser::Static::Target, public Reflection::StructImpl<Ta
 	Model model = Model::CPC464;
 	std::string loading_command;
 
+	ReflectableEnum(CRTCType, Type0, Type1, Type2, Type3);
+	CRTCType crtc_type = CRTCType::Type2;
+
+	// This is used internally for testing; it therefore isn't exposed reflectively.
+	bool catch_ssm_codes = false;
+
 	Target() : Analyser::Static::Target(Machine::AmstradCPC) {
 		if(needs_declare()) {
 			DeclareField(model);
+			DeclareField(crtc_type);
 			AnnounceEnum(Model);
+			AnnounceEnum(CRTCType);
 		}
 	}
 };

Analyser/Static/ZXSpectrum/StaticAnalyser.cpp

@@ -8,11 +8,14 @@
 
 #include "StaticAnalyser.hpp"
 
+#include "../../../Storage/Disk/Parsers/CPM.hpp"
 #include "../../../Storage/Disk/Encodings/MFM/Parser.hpp"
 #include "../../../Storage/Tape/Parsers/Spectrum.hpp"
 
 #include "Target.hpp"
 
+#include <algorithm>
+
 namespace {
 
 bool IsSpectrumTape(const std::shared_ptr<Storage::Tape::Tape> &tape) {
@@ -35,23 +38,67 @@ bool IsSpectrumTape(const std::shared_ptr<Storage::Tape::Tape> &tape) {
 bool IsSpectrumDisk(const std::shared_ptr<Storage::Disk::Disk> &disk) {
 	Storage::Encodings::MFM::Parser parser(Storage::Encodings::MFM::Density::Double, disk);
 
-	// Get logical sector 1; the Spectrum appears to support various physical
-	// sectors as sector 1.
-	const Storage::Encodings::MFM::Sector *boot_sector = nullptr;
-	uint8_t sector_mask = 0;
-	while(!boot_sector) {
-		boot_sector = parser.sector(0, 0, sector_mask + 1);
-		sector_mask += 0x40;
-		if(!sector_mask) break;
-	}
+	// Grab absolutely any sector from the first track to determine general encoding.
+	const Storage::Encodings::MFM::Sector *any_sector = parser.any_sector(0, 0);
+	if(!any_sector) return false;
+
+	// Determine the sector base and get logical sector 1.
+	const uint8_t sector_base = any_sector->address.sector & 0xc0;
+	const Storage::Encodings::MFM::Sector *boot_sector = parser.sector(0, 0, sector_base + 1);
 	if(!boot_sector) return false;
 
-	// Test that the contents of the boot sector sum to 3, modulo 256.
-	uint8_t byte_sum = 0;
-	for(auto byte: boot_sector->samples[0]) {
-		byte_sum += byte;
+	Storage::Disk::CPM::ParameterBlock cpm_format{};
+	switch(sector_base) {
+		case 0x40:	cpm_format = Storage::Disk::CPM::ParameterBlock::cpc_system_format();	break;
+		case 0xc0:	cpm_format = Storage::Disk::CPM::ParameterBlock::cpc_data_format();		break;
+
+		default: {
+			// Check the first ten bytes of the first sector for the disk format; if these are all
+			// the same value then instead substitute a default format.
+			std::array<uint8_t, 10> format;
+			std::copy(boot_sector->samples[0].begin(), boot_sector->samples[0].begin() + 10, format.begin());
+			if(std::all_of(format.begin(), format.end(), [&](const uint8_t v) { return v == format[0]; })) {
+				format = {0x00, 0x00, 0x28, 0x09, 0x02, 0x01, 0x03, 0x02, 0x2a, 0x52};
+			}
+
+			// Parse those ten bytes as:
+			//
+			// Byte 0: disc type
+			// Byte 1: sidedness
+			//		bits 0-6: arrangement
+			//			0 => single sided
+			//			1 => double sided, flip sides
+			//			2 => double sided, up and over
+			//		bit 7: double-track
+			// Byte 2: number of tracks per side
+			// Byte 3: number of sectors per track
+			// Byte 4: Log2(sector size) - 7
+			// Byte 5: number of reserved tracks
+			// Byte 6: Log2(block size) - 7
+			// Byte 7: number of directory blocks
+			// Byte 8: gap length (read/write)
+			// Byte 9: gap length(format)
+			cpm_format.sectors_per_track = format[3];
+			cpm_format.tracks = format[2];
+			cpm_format.block_size = 128 << format[6];
+			cpm_format.first_sector = sector_base + 1;
+			cpm_format.reserved_tracks = format[5];
+
+			// i.e. bits set downward from 0x4000 for as many blocks as form the catalogue.
+			cpm_format.catalogue_allocation_bitmap = 0x8000 - (0x8000 >> format[7]);
+		} break;
 	}
-	return byte_sum == 3;
+
+	// If the boot sector sums to 3 modulo 256 then this is a Spectrum disk.
+	const auto byte_sum = static_cast<uint8_t>(
+		std::accumulate(boot_sector->samples[0].begin(), boot_sector->samples[0].end(), 0));
+	if(byte_sum == 3) {
+		return true;
+	}
+
+	// ... otherwise read a CPM directory and look for a BASIC program called "DISK".
+	const auto catalogue = Storage::Disk::CPM::GetCatalogue(disk, cpm_format);
+	return catalogue && catalogue->is_zx_spectrum_booter();
 }
 
 }

Components/6845/CRTC6845.hpp

@@ -301,17 +301,17 @@ template <class BusHandlerT, Personality personality, CursorType cursor_type> cl
 						}
 					} else {
 						line_counter_ = (line_counter_ + 1) & 0x7f;
+					}
 
-						// Check for start of vertical sync.
-						if(line_counter_ == layout_.vertical.start_sync) {
-							bus_state_.vsync = true;
-							vsync_counter_ = 0;
-						}
+					// Check for start of vertical sync.
+					if(line_counter_ == layout_.vertical.start_sync) {
+						bus_state_.vsync = true;
+						vsync_counter_ = 0;
+					}
 
-						// Check for end of visible lines.
-						if(line_counter_ == layout_.vertical.displayed) {
-							line_is_visible_ = false;
-						}
+					// Check for end of visible lines.
+					if(line_counter_ == layout_.vertical.displayed) {
+						line_is_visible_ = false;
 					}
 				} else {
 					bus_state_.row_address = (bus_state_.row_address + 1) & 0x1f;

Machines/Acorn/Electron/Electron.cpp

@@ -213,21 +213,48 @@ template <bool has_scsi_bus> class ConcreteMachine:
 		}
 
 		forceinline Cycles perform_bus_operation(CPU::MOS6502::BusOperation operation, uint16_t address, uint8_t *value) {
-			unsigned int cycles = 1;
+			Cycles cycles{1};
+
+			if(address < 0x8000) {
+				cycles = video_.ram_delay();
+			} else {
+				if((address & 0xff00) == 0xfe00) {
+					cycles = video_.io_delay();
+				}
+			}
+
+			if(const auto video_interrupts = video_.run_for(cycles); video_interrupts) {
+				signal_interrupt(video_interrupts);
+			}
+
+			cycles_since_audio_update_ += cycles;
+			if(cycles_since_audio_update_ > Cycles(16384)) update_audio();
+			tape_.run_for(cycles);
+
+			if(typer_) typer_->run_for(cycles);
+			if(plus3_) plus3_->run_for(cycles * 4);
+			if(shift_restart_counter_) {
+				shift_restart_counter_ -= cycles.as<int>();
+				if(shift_restart_counter_ <= 0) {
+					shift_restart_counter_ = 0;
+					m6502_.set_power_on(true);
+					set_key_state(KeyShift, true);
+					is_holding_shift_ = true;
+				}
+			}
+
+			if constexpr (has_scsi_bus) {
+				if(scsi_is_clocked_) {
+					scsi_bus_.run_for(cycles);
+				}
+			}
 
 			if(address < 0x8000) {
 				if(isReadOperation(operation)) {
 					*value = ram_[address];
 				} else {
-					if(address >= video_access_range_.low_address && address <= video_access_range_.high_address) {
-						video_.flush();
-					}
 					ram_[address] = *value;
 				}
-
-				// For the entire frame, RAM is accessible only on odd cycles; in modes below 4
-				// it's also accessible only outside of the pixel regions.
-				cycles += video_.last_valid()->get_cycles_until_next_ram_availability(video_.time_since_flush().template as<int>() + 1);
 			} else {
 				switch(address & 0xff0f) {
 					case 0xfe00:
@@ -265,8 +292,7 @@ template <bool has_scsi_bus> class ConcreteMachine:
 					case 0xfe08: case 0xfe09: case 0xfe0a: case 0xfe0b:
 					case 0xfe0c: case 0xfe0d: case 0xfe0e: case 0xfe0f:
 						if(!isReadOperation(operation)) {
-							video_->write(address, *value);
-							video_access_range_ = video_.last_valid()->get_memory_access_range();
+							video_.write(address, *value);
 						}
 					break;
 					case 0xfe04:
@@ -472,39 +498,10 @@ template <bool has_scsi_bus> class ConcreteMachine:
 				}
 			}
 
-			if(video_ += Cycles(int(cycles))) {
-				signal_interrupt(video_.last_valid()->get_interrupts());
-			}
-
-			cycles_since_audio_update_ += Cycles(int(cycles));
-			if(cycles_since_audio_update_ > Cycles(16384)) update_audio();
-			tape_.run_for(Cycles(int(cycles)));
-
-			if(typer_) typer_->run_for(Cycles(int(cycles)));
-			if(plus3_) plus3_->run_for(Cycles(4*int(cycles)));
-			if(shift_restart_counter_) {
-				shift_restart_counter_ -= cycles;
-				if(shift_restart_counter_ <= 0) {
-					shift_restart_counter_ = 0;
-					m6502_.set_power_on(true);
-					set_key_state(KeyShift, true);
-					is_holding_shift_ = true;
-				}
-			}
-
-			if constexpr (has_scsi_bus) {
-				if(scsi_is_clocked_) {
-					scsi_bus_.run_for(Cycles(int(cycles)));
-				}
-			}
-
-			return Cycles(int(cycles));
+			return cycles;
 		}
 
 		void flush_output(int outputs) final {
-			if(outputs & Output::Video) {
-				video_.flush();
-			}
 			if(outputs & Output::Audio) {
 				update_audio();
 				audio_queue_.perform();
@@ -512,19 +509,19 @@ template <bool has_scsi_bus> class ConcreteMachine:
 		}
 
 		void set_scan_target(Outputs::Display::ScanTarget *scan_target) final {
-			video_.last_valid()->set_scan_target(scan_target);
+			video_.set_scan_target(scan_target);
 		}
 
 		Outputs::Display::ScanStatus get_scaled_scan_status() const final {
-			return video_.last_valid()->get_scaled_scan_status();
+			return video_.get_scaled_scan_status();
 		}
 
 		void set_display_type(Outputs::Display::DisplayType display_type) final {
-			video_.last_valid()->set_display_type(display_type);
+			video_.set_display_type(display_type);
 		}
 
 		Outputs::Display::DisplayType get_display_type() const final {
-			return video_.last_valid()->get_display_type();
+			return video_.get_display_type();
 		}
 
 		Outputs::Speaker::Speaker *get_speaker() final {
@@ -686,7 +683,10 @@ template <bool has_scsi_bus> class ConcreteMachine:
 			speaker_.run_for(audio_queue_, cycles_since_audio_update_.divide(Cycles(SoundGenerator::clock_rate_divider)));
 		}
 
-		inline void signal_interrupt(Interrupt interrupt) {
+		inline void signal_interrupt(uint8_t interrupt) {
+			if(!interrupt) {
+				return;
+			}
 			interrupt_status_ |= interrupt;
 			evaluate_interrupts();
 		}
@@ -732,7 +732,6 @@ template <bool has_scsi_bus> class ConcreteMachine:
 
 		// Counters related to simultaneous subsystems
 		Cycles cycles_since_audio_update_ = 0;
-		VideoOutput::Range video_access_range_ = {0, 0xffff};
 
 		// Tape
 		Tape tape_;
@@ -768,7 +767,7 @@ template <bool has_scsi_bus> class ConcreteMachine:
 		}
 
 		// Outputs
-		JustInTimeActor<VideoOutput, Cycles> video_;
+		VideoOutput video_;
 
 		Concurrency::AsyncTaskQueue<false> audio_queue_;
 		SoundGenerator sound_generator_;

Machines/Acorn/Electron/Video.cpp

@@ -12,44 +12,21 @@
 
 using namespace Electron;
 
-#define graphics_line(v)	((((v) >> 7) - first_graphics_line + field_divider_line) % field_divider_line)
-#define graphics_column(v)	((((v) & 127) - first_graphics_cycle + 128) & 127)
-
-namespace {
-	constexpr int cycles_per_line = 128;
-	constexpr int lines_per_frame = 625;
-	constexpr int cycles_per_frame = lines_per_frame * cycles_per_line;
-	constexpr int crt_cycles_multiplier = 8;
-	constexpr int crt_cycles_per_line = crt_cycles_multiplier * cycles_per_line;
-
-	constexpr int field_divider_line = 312;	// i.e. the line, simultaneous with which, the first field's sync ends. So if
-											// the first line with pixels in field 1 is the 20th in the frame, the first line
-											// with pixels in field 2 will be 20+field_divider_line
-	constexpr int first_graphics_line = 31;
-	constexpr int first_graphics_cycle = 33;
-
-	constexpr int display_end_interrupt_line = 256;
-
-	constexpr int real_time_clock_interrupt_1 = 16704;
-	constexpr int real_time_clock_interrupt_2 = 56704;
-	constexpr int display_end_interrupt_1 = (first_graphics_line + display_end_interrupt_line)*cycles_per_line;
-	constexpr int display_end_interrupt_2 = (first_graphics_line + field_divider_line + display_end_interrupt_line)*cycles_per_line;
-}
-
 // MARK: - Lifecycle
 
-VideoOutput::VideoOutput(uint8_t *memory) :
+VideoOutput::VideoOutput(const uint8_t *memory) :
 	ram_(memory),
-	crt_(crt_cycles_per_line,
+	crt_(h_total,
 		1,
 		Outputs::Display::Type::PAL50,
 		Outputs::Display::InputDataType::Red1Green1Blue1) {
-	memset(palette_, 0xf, sizeof(palette_));
-	setup_screen_map();
-	setup_base_address();
-
-	// TODO: as implied below, I've introduced a clock's latency into the graphics pipeline somehow. Investigate.
-	crt_.set_visible_area(crt_.get_rect_for_area(first_graphics_line - 1, 256, (first_graphics_cycle+1) * crt_cycles_multiplier, 80 * crt_cycles_multiplier, 4.0f / 3.0f));
+	crt_.set_visible_area(crt_.get_rect_for_area(
+		312 - vsync_end,
+		256,
+		h_total - hsync_start,
+		80 * 8,
+		4.0f / 3.0f
+	));
 }
 
 void VideoOutput::set_scan_target(Outputs::Display::ScanTarget *scan_target) {
@@ -57,7 +34,7 @@ void VideoOutput::set_scan_target(Outputs::Display::ScanTarget *scan_target) {
 }
 
 Outputs::Display::ScanStatus VideoOutput::get_scaled_scan_status() const {
-	return crt_.get_scaled_scan_status() / float(crt_cycles_multiplier);
+	return crt_.get_scaled_scan_status();
 }
 
 void VideoOutput::set_display_type(Outputs::Display::DisplayType display_type) {
@@ -68,435 +45,251 @@ Outputs::Display::DisplayType VideoOutput::get_display_type() const {
 	return crt_.get_display_type();
 }
 
-// MARK: - Display update methods
+uint8_t VideoOutput::run_for(const Cycles cycles) {
+	uint8_t interrupts{};
 
-void VideoOutput::start_pixel_line() {
-	current_pixel_line_ = (current_pixel_line_+1)&255;
-	if(!current_pixel_line_) {
-		start_line_address_ = start_screen_address_;
-		current_character_row_ = 0;
-		is_blank_line_ = false;
-	} else {
-		bool mode_has_blank_lines = (screen_mode_ == 6) || (screen_mode_ == 3);
-		is_blank_line_ = (mode_has_blank_lines && ((current_character_row_ > 7 && current_character_row_ < 10) || (current_pixel_line_ > 249)));
+	int number_of_cycles = cycles.as<int>();
+	while(number_of_cycles--) {
+		// The below is my attempt at transcription of the equivalent VHDL code in moogway82's
+		// JamSoftElectronULA — https://github.com/moogway82/JamSoftElectronULA — which is itself
+		// derived from hoglet67's https://github.com/hoglet67/ElectronFpga and that author's
+		// reverse-engineering of the Electron ULA. It should therefore be as accurate to the
+		// original hardware as my comprehension of VHDL and adaptation into sequential code allows.
 
-		if(!is_blank_line_) {
-			start_line_address_++;
+		// In this, the sequential world of C++, all tests below should assume that the position
+		// named by (h_count_, v_count_) is the one that was active **prior to this cycle**.
+		//
+		// So this cycle spans the period from (h_count_, v_count_) to (h_count_, v_count_)+1.
 
-			if(current_character_row_ > 7) {
-				start_line_address_ += ((screen_mode_ < 4) ? 80 : 40) * 8 - 8;
-				current_character_row_ = 0;
+		// Test for interrupts.
+		if(v_count_ == v_rtc && ((!field_ && !h_count_) || (field_ && h_count_ == h_half))) {
+			interrupts |= static_cast<uint8_t>(Interrupt::RealTimeClock);
+		}
+		if(h_count_ == hsync_start && ((v_count_ == v_disp_gph && !mode_text_) or (v_count_ == v_disp_txt && mode_text_))) {
+			interrupts |= static_cast<uint8_t>(Interrupt::DisplayEnd);
+		}
+
+		// Update syncs.
+		if(!field_) {
+			if(!h_count_ && v_count_ == vsync_start) {
+				vsync_int_ = true;
+			} else if(h_count_ == h_half && v_count_ == vsync_end) {
+				vsync_int_ = false;
+			}
+		} else {
+			if(h_count_ == h_half && v_count_ == vsync_start) {
+				vsync_int_ = true;
+			} else if(!h_count_ && v_count_ == vsync_end + 1) {
+				vsync_int_ = false;
+			}
+		}
+		
+		if(h_count_ == hsync_start) {
+			hsync_int_ = true;
+		} else if(h_count_ == hsync_end) {
+			hsync_int_ = false;
+		}
+		
+		// Update character row on the trailing edge of hsync.
+		if(h_count_ == hsync_end) {
+			if(is_v_end()) {
+				char_row_ = 0;
+			} else {
+				char_row_ = last_line() ? 0 : char_row_ + 1;
+			}
+		}
+
+		// Disable the top bit of the char_row counter outside of text mode.
+		if(!mode_text_) {
+			char_row_ &= 7;
+		}
+
+		// Latch video address at frame start.
+		if(h_count_ == h_reset_addr && is_v_end()) {
+			row_addr_ = byte_addr_ = screen_base_;
+		}
+		
+		// Copy byte_addr back into row_addr if a new character row has begun.
+		if(hsync_int_) {
+			if(last_line()) {
+				row_addr_ = byte_addr_;
+			} else {
+				byte_addr_ = row_addr_;
+			}
+		}
+
+		// Determine current output item.
+		OutputStage stage;
+		int screen_pitch = screen_pitch_;
+		if(vsync_int_ || hsync_int_) {
+			stage = OutputStage::Sync;
+		} else if(in_blank()) {
+			if(h_count_ >= hburst_start && h_count_ < hburst_end) {
+				stage = OutputStage::ColourBurst;
+			} else {
+				stage = OutputStage::Blank;
+			}
+		} else {
+			stage = OutputStage::Pixels;
+			screen_pitch = (mode_40_ ? 320 : 640) / static_cast<int>(mode_bpp_);
+		}
+
+		if(stage != output_ || screen_pitch != screen_pitch_) {
+			switch(output_) {
+				case OutputStage::Sync:			crt_.output_sync(output_length_);					break;
+				case OutputStage::Blank:		crt_.output_blank(output_length_);					break;
+				case OutputStage::ColourBurst:	crt_.output_default_colour_burst(output_length_);	break;
+				case OutputStage::Pixels:
+					if(current_output_target_) {
+						crt_.output_data(
+							output_length_,
+							static_cast<size_t>(current_output_target_ - initial_output_target_)
+						);
+					} else {
+						crt_.output_data(output_length_);
+					}
+				break;
+			}
+			output_length_ = 0;
+			output_ = stage;
+			screen_pitch_ = screen_pitch;
+
+			if(stage == OutputStage::Pixels) {
+				initial_output_target_ = current_output_target_ = crt_.begin_data(static_cast<size_t>(screen_pitch_));
+			}
+		}
+		output_length_ += 8;
+		if(output_ == OutputStage::Pixels && (!mode_40_ || h_count_ & 8) && current_output_target_) {
+			const uint8_t data = ram_[byte_addr_ | char_row_];
+
+			switch(mode_bpp_) {
+				case Bpp::One:
+					current_output_target_[0] = palette1bpp_[(data >> 7) & 1];
+					current_output_target_[1] = palette1bpp_[(data >> 6) & 1];
+					current_output_target_[2] = palette1bpp_[(data >> 5) & 1];
+					current_output_target_[3] = palette1bpp_[(data >> 4) & 1];
+					current_output_target_[4] = palette1bpp_[(data >> 3) & 1];
+					current_output_target_[5] = palette1bpp_[(data >> 2) & 1];
+					current_output_target_[6] = palette1bpp_[(data >> 1) & 1];
+					current_output_target_[7] = palette1bpp_[(data >> 0) & 1];
+					current_output_target_ += 8;
+				break;
+				case Bpp::Two:
+					current_output_target_[0] = palette2bpp_[((data >> 6) & 2) | ((data >> 3) & 1)];
+					current_output_target_[1] = palette2bpp_[((data >> 5) & 2) | ((data >> 2) & 1)];
+					current_output_target_[2] = palette2bpp_[((data >> 4) & 2) | ((data >> 1) & 1)];
+					current_output_target_[3] = palette2bpp_[((data >> 3) & 2) | ((data >> 0) & 1)];
+					current_output_target_ += 4;
+				break;
+				case Bpp::Four:
+					current_output_target_[0] = palette4bpp_[((data >> 4) & 8) | ((data >> 3) & 4) | ((data >> 2) & 2) | ((data >> 1) & 1)];
+					current_output_target_[1] = palette4bpp_[((data >> 3) & 8) | ((data >> 2) & 4) | ((data >> 1) & 2) | ((data >> 0) & 1)];
+					current_output_target_ += 2;
+				break;
+			}
+		}
+
+		// Increment the byte address across the line.
+		// (slghtly pained logic here because the input clock is still at the pixel rate, not the byte rate)
+		if(h_count_ < h_active) {
+			if(
+				(!mode_40_ && !(h_count_ & 0x7)) ||
+				(mode_40_ && ((h_count_ & 0xf) == 0x8))
+			) {
+				byte_addr_ += 8;
+
+				if(!(byte_addr_ & 0b0111'1000'0000'0000)) {
+					byte_addr_ = mode_base_ | (byte_addr_ & 0x0000'0111'1111'1111);
+				}
+			}
+		}
+
+		// Horizontal and vertical counter updates; code below should act
+		h_count_ += 8;
+		if(h_count_ == h_total) {
+			h_count_ = 0;
+
+			if(is_v_end()) {
+				v_count_ = 0;
+				field_ = !field_;
+			} else {
+				++v_count_;
 			}
 		}
 	}
-	current_screen_address_ = start_line_address_;
-	current_pixel_column_ = 0;
-	initial_output_target_ = current_output_target_ = nullptr;
-}
 
-void VideoOutput::end_pixel_line() {
-	const int data_length = int(current_output_target_ - initial_output_target_);
-	if(data_length) {
-		crt_.output_data(data_length * current_output_divider_, size_t(data_length));
-	}
-	current_character_row_++;
-}
-
-void VideoOutput::output_pixels(int number_of_cycles) {
-	if(!number_of_cycles) return;
-
-	if(is_blank_line_) {
-		crt_.output_blank(number_of_cycles * crt_cycles_multiplier);
-	} else {
-		int divider = 1;
-		switch(screen_mode_) {
-			case 0: case 3: divider = 1; break;
-			case 1: case 4: case 6: divider = 2; break;
-			case 2: case 5: divider = 4; break;
-		}
-
-		if(!initial_output_target_ || divider != current_output_divider_) {
-			const int data_length = int(current_output_target_ - initial_output_target_);
-			if(data_length) {
-				crt_.output_data(data_length * current_output_divider_, size_t(data_length));
-			}
-			current_output_divider_ = divider;
-			initial_output_target_ = current_output_target_ = crt_.begin_data(size_t(640 / current_output_divider_), size_t(8 / divider));
-		}
-
-#define get_pixel()	\
-				if(current_screen_address_&32768) {\
-					current_screen_address_ = (screen_mode_base_address_ + current_screen_address_)&32767;\
-				}\
-				last_pixel_byte_ = ram_[current_screen_address_];\
-				current_screen_address_ = current_screen_address_+8
-
-		switch(screen_mode_) {
-			case 0: case 3:
-				if(initial_output_target_) {
-					while(number_of_cycles--) {
-						get_pixel();
-						*reinterpret_cast<uint64_t *>(current_output_target_) = palette_tables_.eighty1bpp[last_pixel_byte_];
-						current_output_target_ += 8;
-						current_pixel_column_++;
-					}
-				} else current_output_target_ += 8*number_of_cycles;
-			break;
-
-			case 1:
-				if(initial_output_target_) {
-					while(number_of_cycles--) {
-						get_pixel();
-						*reinterpret_cast<uint32_t *>(current_output_target_) = palette_tables_.eighty2bpp[last_pixel_byte_];
-						current_output_target_ += 4;
-						current_pixel_column_++;
-					}
-				} else current_output_target_ += 4*number_of_cycles;
-			break;
-
-			case 2:
-				if(initial_output_target_) {
-					while(number_of_cycles--) {
-						get_pixel();
-						*reinterpret_cast<uint16_t *>(current_output_target_) = palette_tables_.eighty4bpp[last_pixel_byte_];
-						current_output_target_ += 2;
-						current_pixel_column_++;
-					}
-				} else current_output_target_ += 2*number_of_cycles;
-			break;
-
-			case 4: case 6:
-				if(initial_output_target_) {
-					if(current_pixel_column_&1) {
-						last_pixel_byte_ <<= 4;
-						*reinterpret_cast<uint32_t *>(current_output_target_) = palette_tables_.forty1bpp[last_pixel_byte_];
-						current_output_target_ += 4;
-
-						number_of_cycles--;
-						current_pixel_column_++;
-					}
-					while(number_of_cycles > 1) {
-						get_pixel();
-						*reinterpret_cast<uint32_t *>(current_output_target_) = palette_tables_.forty1bpp[last_pixel_byte_];
-						current_output_target_ += 4;
-
-						last_pixel_byte_ <<= 4;
-						*reinterpret_cast<uint32_t *>(current_output_target_) = palette_tables_.forty1bpp[last_pixel_byte_];
-						current_output_target_ += 4;
-
-						number_of_cycles -= 2;
-						current_pixel_column_+=2;
-					}
-					if(number_of_cycles) {
-						get_pixel();
-						*reinterpret_cast<uint32_t *>(current_output_target_) = palette_tables_.forty1bpp[last_pixel_byte_];
-						current_output_target_ += 4;
-						current_pixel_column_++;
-					}
-				} else current_output_target_ += 4 * number_of_cycles;
-			break;
-
-			case 5:
-				if(initial_output_target_) {
-					if(current_pixel_column_&1) {
-						last_pixel_byte_ <<= 2;
-						*reinterpret_cast<uint16_t *>(current_output_target_) = palette_tables_.forty2bpp[last_pixel_byte_];
-						current_output_target_ += 2;
-
-						number_of_cycles--;
-						current_pixel_column_++;
-					}
-					while(number_of_cycles > 1) {
-						get_pixel();
-						*reinterpret_cast<uint16_t *>(current_output_target_) = palette_tables_.forty2bpp[last_pixel_byte_];
-						current_output_target_ += 2;
-
-						last_pixel_byte_ <<= 2;
-						*reinterpret_cast<uint16_t *>(current_output_target_) = palette_tables_.forty2bpp[last_pixel_byte_];
-						current_output_target_ += 2;
-
-						number_of_cycles -= 2;
-						current_pixel_column_+=2;
-					}
-					if(number_of_cycles) {
-						get_pixel();
-						*reinterpret_cast<uint16_t *>(current_output_target_) = palette_tables_.forty2bpp[last_pixel_byte_];
-						current_output_target_ += 2;
-						current_pixel_column_++;
-					}
-				} else current_output_target_ += 2*number_of_cycles;
-			break;
-		}
-
-#undef get_pixel
-	}
-}
-
-void VideoOutput::run_for(const Cycles cycles) {
-	int number_of_cycles = int(cycles.as_integral());
-	const auto start_position = output_position_;
-	output_position_ = (output_position_ + number_of_cycles) % cycles_per_frame;
-
-	if(
-		(start_position < real_time_clock_interrupt_1 && output_position_ >= real_time_clock_interrupt_1) ||
-		(start_position < real_time_clock_interrupt_2 && output_position_ >= real_time_clock_interrupt_2)
-	) {
-		interrupts_ = Electron::Interrupt(interrupts_ | Electron::Interrupt::RealTimeClock);
-	}
-
-	if(
-		(start_position < display_end_interrupt_1 && output_position_ >= display_end_interrupt_1) ||
-		(start_position < display_end_interrupt_2 && output_position_ >= display_end_interrupt_2)
-	) {
-		interrupts_ = Electron::Interrupt(interrupts_ | Electron::Interrupt::DisplayEnd);
-	}
-
-	while(number_of_cycles) {
-		int draw_action_length = screen_map_[screen_map_pointer_].length;
-		int time_left_in_action = std::min(number_of_cycles, draw_action_length - cycles_into_draw_action_);
-		if(screen_map_[screen_map_pointer_].type == DrawAction::Pixels) output_pixels(time_left_in_action);
-
-		number_of_cycles -= time_left_in_action;
-		cycles_into_draw_action_ += time_left_in_action;
-		if(cycles_into_draw_action_ == draw_action_length) {
-			switch(screen_map_[screen_map_pointer_].type) {
-				case DrawAction::Sync:			crt_.output_sync(draw_action_length * crt_cycles_multiplier);					break;
-				case DrawAction::ColourBurst:	crt_.output_default_colour_burst(draw_action_length * crt_cycles_multiplier);	break;
-				case DrawAction::Blank:			crt_.output_blank(draw_action_length * crt_cycles_multiplier);					break;
-				case DrawAction::Pixels:		end_pixel_line();																break;
-			}
-			screen_map_pointer_ = (screen_map_pointer_ + 1) % screen_map_.size();
-			cycles_into_draw_action_ = 0;
-			if(screen_map_[screen_map_pointer_].type == DrawAction::Pixels) start_pixel_line();
-		}
-	}
+	return interrupts;
 }
 
 // MARK: - Register hub
 
 void VideoOutput::write(int address, uint8_t value) {
-	switch(address & 0xf) {
+	address &= 0xf;
+	switch(address) {
 		case 0x02:
-			start_screen_address_ = (start_screen_address_ & 0xfe00) | uint16_t((value & 0xe0) << 1);
-			if(!start_screen_address_) start_screen_address_ |= 0x8000;
+			screen_base_ =
+				(screen_base_ & 0b0111'1110'0000'0000) |
+				((value << 1) & 0b0000'0001'1100'0000);
 		break;
 		case 0x03:
-			start_screen_address_ = (start_screen_address_ & 0x01ff) | uint16_t((value & 0x3f) << 9);
-			if(!start_screen_address_) start_screen_address_ |= 0x8000;
+			screen_base_ =
+				((value << 9) & 0b0111'1110'0000'0000) |
+				(screen_base_ & 0b0000'0001'1100'0000);
 		break;
 		case 0x07: {
-			// update screen mode
-			uint8_t new_screen_mode = (value >> 3)&7;
-			if(new_screen_mode == 7) new_screen_mode = 4;
-			if(new_screen_mode != screen_mode_) {
-				screen_mode_ = new_screen_mode;
-				setup_base_address();
+			uint8_t mode = (value >> 3)&7;
+			mode_40_ = mode >= 4;
+			mode_text_ = mode == 3 || mode == 6;
+
+			switch(mode) {
+				case 0:
+				case 1:
+				case 2:		mode_base_ = 0x3000;	break;
+				case 3:		mode_base_ = 0x4000;	break;
+				case 6:		mode_base_ = 0x6000;	break;
+				default:	mode_base_ = 0x5800;	break;
 			}
-		}
-		break;
+
+			switch(mode) {
+				default:	mode_bpp_ = Bpp::One;	break;
+				case 1:
+				case 5:		mode_bpp_ = Bpp::Two;	break;
+				case 2:		mode_bpp_ = Bpp::Four;	break;
+			}
+		} break;
 		case 0x08: case 0x09: case 0x0a: case 0x0b:
 		case 0x0c: case 0x0d: case 0x0e: case 0x0f: {
-			constexpr int registers[4][4] = {
-				{10, 8, 2, 0},
-				{14, 12, 6, 4},
-				{15, 13, 7, 5},
-				{11, 9, 3, 1},
-			};
-			const int index = (address >> 1)&3;
-			const uint8_t colour = ~value;
-			if(address&1) {
-				palette_[registers[index][0]]	= (palette_[registers[index][0]]&3)	| ((colour >> 1)&4);
-				palette_[registers[index][1]]	= (palette_[registers[index][1]]&3)	| ((colour >> 0)&4);
-				palette_[registers[index][2]]	= (palette_[registers[index][2]]&3)	| ((colour << 1)&4);
-				palette_[registers[index][3]]	= (palette_[registers[index][3]]&3)	| ((colour << 2)&4);
+			palette_[address - 8] = ~value;
 
-				palette_[registers[index][2]]	= (palette_[registers[index][2]]&5)	| ((colour >> 4)&2);
-				palette_[registers[index][3]]	= (palette_[registers[index][3]]&5)	| ((colour >> 3)&2);
-			} else {
-				palette_[registers[index][0]]	= (palette_[registers[index][0]]&6)	| ((colour >> 7)&1);
-				palette_[registers[index][1]]	= (palette_[registers[index][1]]&6)	| ((colour >> 6)&1);
-				palette_[registers[index][2]]	= (palette_[registers[index][2]]&6)	| ((colour >> 5)&1);
-				palette_[registers[index][3]]	= (palette_[registers[index][3]]&6)	| ((colour >> 4)&1);
+			if(address <= 0x09) {
+				palette1bpp_[0] = palette_entry<1, 0, 1, 4, 0, 4>();
+				palette1bpp_[1] = palette_entry<1, 2, 0, 6, 0, 2>();
 
-				palette_[registers[index][0]]	= (palette_[registers[index][0]]&5)	| ((colour >> 2)&2);
-				palette_[registers[index][1]]	= (palette_[registers[index][1]]&5)	| ((colour >> 1)&2);
+				palette2bpp_[0] = palette_entry<1, 0, 1, 4, 0, 4>();
+				palette2bpp_[1] = palette_entry<1, 1, 1, 5, 0, 5>();
+				palette2bpp_[2] = palette_entry<1, 2, 0, 2, 0, 6>();
+				palette2bpp_[3] = palette_entry<1, 3, 0, 3, 0, 7>();
 			}
 
-			// regenerate all palette tables for now
-			for(int byte = 0; byte < 256; byte++) {
-				uint8_t *target = reinterpret_cast<uint8_t *>(&palette_tables_.forty1bpp[byte]);
-				target[0] = palette_[(byte&0x80) >> 4];
-				target[1] = palette_[(byte&0x40) >> 3];
-				target[2] = palette_[(byte&0x20) >> 2];
-				target[3] = palette_[(byte&0x10) >> 1];
+			palette4bpp_[0] = palette_entry<1, 0, 1, 4, 0, 4>();
+			palette4bpp_[2] = palette_entry<1, 1, 1, 5, 0, 5>();
+			palette4bpp_[8] = palette_entry<1, 2, 0, 2, 0, 6>();
+			palette4bpp_[10] = palette_entry<1, 3, 0, 3, 0, 7>();
 
-				target = reinterpret_cast<uint8_t *>(&palette_tables_.eighty2bpp[byte]);
-				target[0] = palette_[((byte&0x80) >> 4) | ((byte&0x08) >> 2)];
-				target[1] = palette_[((byte&0x40) >> 3) | ((byte&0x04) >> 1)];
-				target[2] = palette_[((byte&0x20) >> 2) | ((byte&0x02) >> 0)];
-				target[3] = palette_[((byte&0x10) >> 1) | ((byte&0x01) << 1)];
+			palette4bpp_[4] = palette_entry<3, 0, 3, 4, 2, 4>();
+			palette4bpp_[6] = palette_entry<3, 1, 3, 5, 2, 5>();
+			palette4bpp_[12] = palette_entry<3, 2, 2, 2, 2, 6>();
+			palette4bpp_[14] = palette_entry<3, 3, 2, 3, 2, 7>();
 
-				target = reinterpret_cast<uint8_t *>(&palette_tables_.eighty1bpp[byte]);
-				target[0] = palette_[(byte&0x80) >> 4];
-				target[1] = palette_[(byte&0x40) >> 3];
-				target[2] = palette_[(byte&0x20) >> 2];
-				target[3] = palette_[(byte&0x10) >> 1];
-				target[4] = palette_[(byte&0x08) >> 0];
-				target[5] = palette_[(byte&0x04) << 1];
-				target[6] = palette_[(byte&0x02) << 2];
-				target[7] = palette_[(byte&0x01) << 3];
+			palette4bpp_[5] = palette_entry<5, 0, 5, 4, 4, 4>();
+			palette4bpp_[7] = palette_entry<5, 1, 5, 5, 4, 5>();
+			palette4bpp_[13] = palette_entry<5, 2, 4, 2, 4, 6>();
+			palette4bpp_[15] = palette_entry<5, 3, 4, 3, 4, 7>();
 
-				target = reinterpret_cast<uint8_t *>(&palette_tables_.forty2bpp[byte]);
-				target[0] = palette_[((byte&0x80) >> 4) | ((byte&0x08) >> 2)];
-				target[1] = palette_[((byte&0x40) >> 3) | ((byte&0x04) >> 1)];
-
-				target = reinterpret_cast<uint8_t *>(&palette_tables_.eighty4bpp[byte]);
-				target[0] = palette_[((byte&0x80) >> 4) | ((byte&0x20) >> 3) | ((byte&0x08) >> 2) | ((byte&0x02) >> 1)];
-				target[1] = palette_[((byte&0x40) >> 3) | ((byte&0x10) >> 2) | ((byte&0x04) >> 1) | ((byte&0x01) >> 0)];
-			}
-		}
-		break;
+			palette4bpp_[1] = palette_entry<7, 0, 7, 4, 6, 4>();
+			palette4bpp_[3] = palette_entry<7, 1, 7, 5, 6, 5>();
+			palette4bpp_[9] = palette_entry<7, 2, 6, 2, 6, 6>();
+			palette4bpp_[11] = palette_entry<7, 3, 6, 3, 6, 7>();
+		} break;
 	}
 }
-
-void VideoOutput::setup_base_address() {
-	switch(screen_mode_) {
-		case 0: case 1: case 2: screen_mode_base_address_ = 0x3000; break;
-		case 3: screen_mode_base_address_ = 0x4000; break;
-		case 4: case 5: screen_mode_base_address_ = 0x5800; break;
-		case 6: screen_mode_base_address_ = 0x6000; break;
-	}
-}
-
-// MARK: - Interrupts
-
-Cycles VideoOutput::next_sequence_point() {
-	if(output_position_ < real_time_clock_interrupt_1) {
-		return real_time_clock_interrupt_1 - output_position_;
-	}
-
-	if(output_position_ < display_end_interrupt_1) {
-		return display_end_interrupt_1 - output_position_;
-	}
-
-	if(output_position_ < real_time_clock_interrupt_2) {
-		return real_time_clock_interrupt_2 - output_position_;
-	}
-
-	if(output_position_ < display_end_interrupt_2) {
-		return display_end_interrupt_2 - output_position_;
-	}
-
-	return real_time_clock_interrupt_1 + cycles_per_frame - output_position_;
-}
-
-Electron::Interrupt VideoOutput::get_interrupts() {
-	const auto interrupts = interrupts_;
-	interrupts_ = Electron::Interrupt(0);
-	return interrupts;
-}
-
-// MARK: - RAM timing and access information
-
-unsigned int VideoOutput::get_cycles_until_next_ram_availability(int from_time) {
-	unsigned int result = 0;
-	int position = (output_position_ + from_time) % cycles_per_frame;
-
-	// Apply the standard cost of aligning to the available 1Mhz of RAM bandwidth.
-	result += 1 + (position&1);
-
-	// In Modes 0-3 there is also a complete block on any access while pixels are being fetched.
-	if(screen_mode_ < 4) {
-		const int current_column = graphics_column(position + (position&1));
-		int current_line = graphics_line(position);
-		if(current_column < 80 && current_line < 256) {
-			// Mode 3 is a further special case: in 'every ten line block', the final two aren't painted,
-			// so the CPU is allowed access. But the offset of the ten-line blocks depends on when the
-			// user switched into Mode 3, so that needs to be calculated relative to current output.
-			if(screen_mode_ == 3) {
-				// Get the line the display was on.
-				int output_position_line = graphics_line(output_position_);
-
-				int implied_row;
-				if(current_line >= output_position_line) {
-					// Get the number of lines since then if still in the same frame.
-					int lines_since_output_position = current_line - output_position_line;
-
-					// Therefore get the character row at the proposed time, modulo 10.
-					implied_row = (current_character_row_ + lines_since_output_position) % 10;
-				} else {
-					// If the frame has rolled over, the implied row is just related to the current line.
-					implied_row = current_line % 10;
-				}
-
-				// Mode 3 ends after 250 lines, not the usual 256.
-				if(implied_row < 8 && current_line < 250) result += unsigned(80 - current_column);
-			}
-			else result += unsigned(80 - current_column);
-		}
-	}
-	return result;
-}
-
-VideoOutput::Range VideoOutput::get_memory_access_range() {
-	// This can't be more specific than this without applying a lot more thought because of mixed modes:
-	// suppose a program runs half the screen in an 80-column mode then switches to 40 columns. Then the
-	// real end address will be at 128*80 + 128*40 after the original base, subject to wrapping that depends
-	// on where the overflow occurred. Assuming accesses may run from the lowest possible position through to
-	// the end of RAM is good enough for 95% of use cases however.
-	VideoOutput::Range range;
-	range.low_address = std::min(start_screen_address_, screen_mode_base_address_);
-	range.high_address = 0x8000;
-	return range;
-}
-
-// MARK: - The screen map
-
-void VideoOutput::setup_screen_map() {
-	/*
-
-		Odd field:					Even field:
-
-		|--S--|						   -S-|
-		|--S--|						|--S--|
-		|-S-B-|	= 3					|--S--| = 2.5
-		|--B--|						|--B--|
-		|--P--|						|--P--|
-		|--B--| = 312				|--B--| = 312.5
-		|-B-
-
-	*/
-	for(int c = 0; c < 2; c++) {
-		if(c&1) {
-			screen_map_.emplace_back(DrawAction::Sync, (cycles_per_line * 5) >> 1);
-			screen_map_.emplace_back(DrawAction::Blank, cycles_per_line >> 1);
-		} else {
-			screen_map_.emplace_back(DrawAction::Blank, cycles_per_line >> 1);
-			screen_map_.emplace_back(DrawAction::Sync, (cycles_per_line * 5) >> 1);
-		}
-		for(int l = 0; l < first_graphics_line - 3; l++) emplace_blank_line();
-		for(int l = 0; l < 256; l++) emplace_pixel_line();
-		for(int l = 256 + first_graphics_line; l < 312; l++) emplace_blank_line();
-		if(c&1) emplace_blank_line();
-	}
-}
-
-void VideoOutput::emplace_blank_line() {
-	screen_map_.emplace_back(DrawAction::Sync, 9);
-	screen_map_.emplace_back(DrawAction::ColourBurst, 24 - 9);
-	screen_map_.emplace_back(DrawAction::Blank, 128 - 24);
-}
-
-void VideoOutput::emplace_pixel_line() {
-	// output format is:
-	// 9 cycles: sync
-	// ... to 24 cycles: colour burst
-	// ... to first_graphics_cycle: blank
-	// ... for 80 cycles: pixels
-	// ... until end of line: blank
-	screen_map_.emplace_back(DrawAction::Sync, 9);
-	screen_map_.emplace_back(DrawAction::ColourBurst, 24 - 9);
-	screen_map_.emplace_back(DrawAction::Blank, first_graphics_cycle - 24);
-	screen_map_.emplace_back(DrawAction::Pixels, 80);
-	screen_map_.emplace_back(DrawAction::Blank, 48 - first_graphics_cycle);
-}

Machines/Acorn/Electron/Video.hpp

@@ -30,10 +30,7 @@ class VideoOutput {
 
 			The pointer supplied should be to address 0 in the unexpanded Electron's memory map.
 		*/
-		VideoOutput(uint8_t *memory);
-
-		/// Produces the next @c cycles of video output.
-		void run_for(const Cycles cycles);
+		VideoOutput(const uint8_t *memory);
 
 		/// Sets the destination for output.
 		void set_scan_target(Outputs::Display::ScanTarget *scan_target);
@@ -47,92 +44,140 @@ class VideoOutput {
 		/// Gets the type of output.
 		Outputs::Display::DisplayType get_display_type() const;
 
+		/// Produces the next @c cycles of video output.
+		///
+		/// @returns a bit mask of all interrupts triggered.
+		uint8_t run_for(const Cycles cycles);
+
+		/// @returns The number of 2Mhz cycles that will pass before completion of an attempted
+		/// IO [/1Mhz] access that is first signalled in the upcoming cycle.
+		Cycles io_delay() {
+			return 2 + ((h_count_ >> 3)&1);
+		}
+
+		/// @returns The number of 2Mhz cycles that will pass before completion of an attempted
+		/// RAM access that is first signalled in the upcoming cycle.
+		Cycles ram_delay() {
+			if(!mode_40_ && !in_blank()) {
+				return 2 + ((h_active - h_count_) >> 3);
+			}
+			return io_delay();
+		}
+
 		/*!
 			Writes @c value to the register at @c address. May mutate the results of @c get_next_interrupt,
 			@c get_cycles_until_next_ram_availability and @c get_memory_access_range.
 		*/
 		void write(int address, uint8_t value);
 
-		/*!
-			@returns the next interrupt that should be generated as a result of the video hardware.
-			The time until signalling returned is the number of cycles after the final one triggered
-			by the most recent call to @c run_for.
-
-			This result may be mutated by calls to @c write.
-		*/
-		Cycles next_sequence_point();
-
-		/*!
-			@returns a bit mask of all interrupts that have been triggered since the last call to get_interrupt().
-		*/
-		Electron::Interrupt get_interrupts();
-
 		/*!
 			@returns the number of cycles after (final cycle of last run_for batch + @c from_time)
 			before the video circuits will allow the CPU to access RAM.
 		*/
 		unsigned int get_cycles_until_next_ram_availability(int from_time);
 
-		struct Range {
-			uint16_t low_address, high_address;
-		};
-		/*!
-			@returns the range of addresses that the video might read from.
-		*/
-		Range get_memory_access_range();
-
 	private:
-		inline void start_pixel_line();
-		inline void end_pixel_line();
-		inline void output_pixels(int number_of_cycles);
-		inline void setup_base_address();
-
-		int output_position_ = 0;
-
-		uint8_t palette_[16];
-		uint8_t screen_mode_ = 6;
-		uint16_t screen_mode_base_address_ = 0;
-		uint16_t start_screen_address_ = 0;
-
-		uint8_t *ram_;
-		struct {
-			uint32_t forty1bpp[256];
-			uint16_t forty2bpp[256];
-			uint64_t eighty1bpp[256];
-			uint32_t eighty2bpp[256];
-			uint16_t eighty4bpp[256];
-		} palette_tables_;
-
-		// Display generation.
-		uint16_t start_line_address_ = 0;
-		uint16_t current_screen_address_ = 0;
-		int current_pixel_line_ = -1;
-		int current_pixel_column_ = 0;
-		int current_character_row_ = 0;
-		uint8_t last_pixel_byte_ = 0;
-		bool is_blank_line_ = false;
+		const uint8_t *ram_ = nullptr;
 
 		// CRT output
+		enum class OutputStage {
+			Sync, Blank, Pixels, ColourBurst,
+		};
+		OutputStage output_ = OutputStage::Blank;
+		int output_length_ = 0;
+		int screen_pitch_ = 0;
+
 		uint8_t *current_output_target_ = nullptr;
 		uint8_t *initial_output_target_ = nullptr;
 		int current_output_divider_ = 1;
 		Outputs::CRT::CRT crt_;
 
-		struct DrawAction {
-			enum Type {
-				Sync, ColourBurst, Blank, Pixels
-			} type;
-			int length;
-			DrawAction(Type type, int length) : type(type), length(length) {}
-		};
-		std::vector<DrawAction> screen_map_;
-		void setup_screen_map();
-		void emplace_blank_line();
-		void emplace_pixel_line();
-		std::size_t screen_map_pointer_ = 0;
-		int cycles_into_draw_action_ = 0;
+		// Palettes.
+		uint8_t palette_[8]{};
+		uint8_t palette1bpp_[2]{};
+		uint8_t palette2bpp_[4]{};
+		uint8_t palette4bpp_[16]{};
 
-		Electron::Interrupt interrupts_ = Electron::Interrupt(0);
+		template <int index, int source_bit, int target_bit>
+		uint8_t channel() {
+			if constexpr (source_bit < target_bit) {
+				return (palette_[index] << (target_bit - source_bit)) & (1 << target_bit);
+			} else {
+				return (palette_[index] >> (source_bit - target_bit)) & (1 << target_bit);
+			}
+		}
+
+		template <int r_index, int r_bit, int g_index, int g_bit, int b_index, int b_bit>
+		uint8_t palette_entry() {
+			return channel<r_index, r_bit, 2>() | channel<g_index, g_bit, 1>() | channel<b_index, b_bit, 0>();
+		}
+
+		// User-selected base address; constrained to a 64-byte boundary by the setter.
+		uint16_t screen_base_ = 0;
+
+		// Parameters implied by mode selection.
+		uint16_t mode_base_ = 0;
+		bool mode_40_ = true;
+		bool mode_text_ = false;
+		enum class Bpp {
+			One = 1, Two = 2, Four = 4
+		} mode_bpp_ = Bpp::One;
+
+		// Frame position.
+		int v_count_ = 0;
+		int h_count_ = 0;
+		bool field_ = true;
+
+		// Current working address.
+		uint16_t row_addr_ = 0;	// Address, sans character row, adopted at the start of a row.
+		uint16_t byte_addr_ = 0;	// Current working address, incremented as the raster moves across the line.
+		int char_row_ = 0;		// Character row; 0–9 in text mode, 0–7 in graphics.
+
+		// Sync states.
+		bool vsync_int_ = false;	// True => vsync active.
+		bool hsync_int_ = false;	// True => hsync active.
+
+		// Horizontal timing parameters; all in terms of the 16Mhz pixel clock but conveniently all
+		// divisible by 8, so it's safe to count time with a 2Mhz input.
+		static constexpr int h_active = 640;
+		static constexpr int hsync_start = 768;
+		static constexpr int hsync_end = 832;
+		static constexpr int h_reset_addr = 1016;
+		static constexpr int h_total = 1024;	// Minor digression from the FPGA original here;
+												// in this implementation the value is tested
+												// _after_ position increment rather than before/instead.
+												// So it needs to be one higher. Which is baked into
+												// the constant to emphasise the all-divisible-by-8 property.
+
+		static constexpr int h_half = h_total / 2;
+		static constexpr int hburst_start = 856;
+		static constexpr int hburst_end = 896;
+
+		// Vertical timing parameters; all in terms of lines. As per the horizontal parameters above,
+		// lines begin with their first visible pixel (or the equivalent position).
+		static constexpr int v_active_gph = 256;
+		static constexpr int v_active_txt = 250;
+		static constexpr int v_disp_gph = v_active_gph - 1;
+		static constexpr int v_disp_txt = v_active_txt - 1;
+		static constexpr int vsync_start = 274;
+		static constexpr int vsync_end = 276;
+		static constexpr int v_rtc = 99;
+
+		// Various signals that it was convenient to factor out.
+		int v_total() const {
+			return field_ ? 312 : 311;
+		}
+
+		bool last_line() const {
+			return char_row_ == (mode_text_ ? 9 : 7);
+		}
+
+		bool in_blank() const {
+			return h_count_ >= h_active || (mode_text_ && v_count_ >= v_active_txt) || (!mode_text_ && v_count_ >= v_active_gph) || char_row_ >= 8;
+		}
+
+		bool is_v_end() const {
+			return v_count_ == v_total();
+		}
 };
-
 }

Machines/AmstradCPC/AmstradCPC.cpp

@@ -752,7 +752,8 @@ class i8255PortHandler : public Intel::i8255::PortHandler {
 /*!
 	The actual Amstrad CPC implementation; tying the 8255, 6845 and AY to the Z80.
 */
-template <bool has_fdc> class ConcreteMachine:
+template <bool has_fdc, bool catches_ssm>
+class ConcreteMachine:
 	public MachineTypes::ScanProducer,
 	public MachineTypes::AudioProducer,
 	public MachineTypes::TimedMachine,
@@ -942,6 +943,39 @@ template <bool has_fdc> class ConcreteMachine:
 						*cycle.value = 0xc9;
 						break;
 					}
+
+					if constexpr (catches_ssm) {
+						ssm_code_ = (ssm_code_ << 8) | read_pointers_[address >> 14][address & 16383];
+						if(ssm_delegate_) {
+							if((ssm_code_ & 0xff00ff00) == 0xed00ed00) {
+								const auto code = uint16_t(
+									((ssm_code_ << 8) & 0xff00) | ((ssm_code_ >> 16) & 0x00ff)
+								);
+
+								const auto is_valid = [](uint8_t digit) {
+									return
+										(digit <= 0x3f) ||
+										(digit >= 0x7f && digit <= 0x9f) ||
+										(digit >= 0xa4 && digit <= 0xa7) ||
+										(digit >= 0xac && digit <= 0xaf) ||
+										(digit >= 0xb4 && digit <= 0xb7) ||
+										(digit >= 0xbc && digit <= 0xbf) ||
+										(digit >= 0xc0 && digit <= 0xfd);
+								};
+
+								if(
+									is_valid(static_cast<uint8_t>(code)) && is_valid(static_cast<uint8_t>(code >> 8))
+								) {
+									ssm_delegate_->perform(code);
+									ssm_code_ = 0;
+								}
+							} else if((ssm_code_ & 0xffff) == 0xedfe) {
+								ssm_delegate_->perform(0xfffe);
+							} else if((ssm_code_ & 0xffff) == 0xedff) {
+								ssm_delegate_->perform(0xffff);
+							}
+						}
+					}
 				[[fallthrough]];
 
 				case CPU::Z80::PartialMachineCycle::Read:
@@ -1115,6 +1149,10 @@ template <bool has_fdc> class ConcreteMachine:
 			tape_player_is_sleeping_ = tape_player_.preferred_clocking() == ClockingHint::Preference::None;
 		}
 
+		void set_ssm_delegate(SSMDelegate *delegate) final {
+			ssm_delegate_ = delegate;
+		}
+
 		// MARK: - Keyboard
 		void type_string(const std::string &string) final {
 			Utility::TypeRecipient<CharacterMapper>::add_typer(string);
@@ -1276,6 +1314,9 @@ template <bool has_fdc> class ConcreteMachine:
 		KeyboardState key_state_;
 		AmstradCPC::KeyboardMapper keyboard_mapper_;
 
+		SSMDelegate *ssm_delegate_ = nullptr;
+		uint32_t ssm_code_ = 0;
+
 		bool has_run_ = false;
 		uint8_t ram_[128 * 1024];
 };
@@ -1284,12 +1325,26 @@ template <bool has_fdc> class ConcreteMachine:
 
 using namespace AmstradCPC;
 
+namespace {
+
+template <bool catch_ssm>
+std::unique_ptr<Machine> machine(const Analyser::Static::AmstradCPC::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) {
+	using Model = Analyser::Static::AmstradCPC::Target::Model;
+	switch(target.model) {
+		default:			return std::make_unique<AmstradCPC::ConcreteMachine<true, catch_ssm>>(target, rom_fetcher);
+		case Model::CPC464:	return std::make_unique<AmstradCPC::ConcreteMachine<false, catch_ssm>>(target, rom_fetcher);
+	}
+}
+
+}
+
 // See header; constructs and returns an instance of the Amstrad CPC.
 std::unique_ptr<Machine> Machine::AmstradCPC(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
 	using Target = Analyser::Static::AmstradCPC::Target;
 	const Target *const cpc_target = dynamic_cast<const Target *>(target);
-	switch(cpc_target->model) {
-		default:					return std::make_unique<AmstradCPC::ConcreteMachine<true>>(*cpc_target, rom_fetcher);
-		case Target::Model::CPC464:	return std::make_unique<AmstradCPC::ConcreteMachine<false>>(*cpc_target, rom_fetcher);
+	if(cpc_target->catch_ssm_codes) {
+		return machine<true>(*cpc_target, rom_fetcher);
+	} else {
+		return machine<false>(*cpc_target, rom_fetcher);
 	}
 }

Machines/AmstradCPC/AmstradCPC.hpp

@@ -25,7 +25,10 @@ class Machine {
 		virtual ~Machine() = default;
 
 		/// Creates and returns an Amstrad CPC.
-		static std::unique_ptr<Machine> AmstradCPC(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher);
+		static std::unique_ptr<Machine> AmstradCPC(
+			const Analyser::Static::Target *target,
+			const ROMMachine::ROMFetcher &rom_fetcher
+		);
 
 		/// Defines the runtime options available for an Amstrad CPC.
 		class Options:
@@ -47,6 +50,11 @@ class Machine {
 					}
 				}
 		};
+
+		struct SSMDelegate {
+			virtual void perform(uint16_t) = 0;
+		};
+		virtual void set_ssm_delegate(SSMDelegate *) = 0;
 };
 
 }

Machines/PCCompatible/CGA.hpp

@@ -254,12 +254,10 @@ class CGA {
 			}
 
 			void serialise_pixels(const Motorola::CRTC::BusState &state) {
-				// This is what I think is happenings:
+				// Refresh address is shifted left and two bytes are fetched, just as if the fetch were for
+				// character code + attributes, but producing two bytes worth of graphics.
 				//
-				// Refresh address is still shifted left one and two bytes are fetched, just as if it were
-				// character code + attributes except that these are two bytes worth of graphics.
-				//
-				// Meanwhile, row address is used to invent a 15th address line.
+				// Meanwhile, row address is used as a substitute 14th address line.
 				const auto base_address =
 					((state.refresh_address & 0xfff) << 1) +
 					((state.row_address & 1) << 13);

OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj

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+				4B1082C12C1A87CA00B07C5D /* CSL.hpp */,
+			);
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+			sourceTree = "<group>";
+		};
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+				4B06AAF82C6460760034D014 /* IntelligentKeyboard.cpp in Sources */,
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+				4B06AAD12C645F130034D014 /* 1770.cpp in Sources */,
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 				4B778F0123A5EBA00000D260 /* MacintoshIMG.cpp in Sources */,
 				4B7752AD28217E770073E2C5 /* AmigaADF.cpp in Sources */,
+				4B06AAEB2C645FE80034D014 /* Keyboard.cpp in Sources */,
 				4BFF1D3D2235C3C100838EA1 /* EmuTOSTests.mm in Sources */,
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+				4B06AAFF2C6460A80034D014 /* ConfidenceCounter.cpp in Sources */,
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 				4BD91D772401C2B8007BDC91 /* PatrikRakTests.swift in Sources */,
+				4B06AAE22C645F970034D014 /* PCBooter.cpp in Sources */,
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 				4B680CE223A5553100451D43 /* 68000ComparativeTests.mm in Sources */,
 				4B778F3723A5F11C0000D260 /* Parser.cpp in Sources */,
+				4B06AAE32C645F9E0034D014 /* StringSerialiser.cpp in Sources */,
+				4B06AADB2C645F6D0034D014 /* DiskROM.cpp in Sources */,
 				4B778F4523A5F1CD0000D260 /* SegmentParser.cpp in Sources */,
 				4B90467422C6FADD000E2074 /* 68000BitwiseTests.mm in Sources */,
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 				4B7962A12819681F008130F9 /* Decoder.cpp in Sources */,
 				4B7752BB28217F1A0073E2C5 /* Copper.cpp in Sources */,
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 				4B778F4B23A5F2030000D260 /* StaticAnalyser.cpp in Sources */,
 				4B778F5023A5F2230000D260 /* StaticAnalyser.cpp in Sources */,
+				4B06AACB2C645ED00034D014 /* AY38910.cpp in Sources */,
+				4B06AB172C6461B30034D014 /* MultiSpeaker.cpp in Sources */,
+				4B06AADE2C645F7E0034D014 /* Video.cpp in Sources */,
 				4B924E991E74D22700B76AF1 /* AtariStaticAnalyserTests.mm in Sources */,
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 				4B778F3423A5F1040000D260 /* DirectAccessDevice.cpp in Sources */,
 				4B7BC7F51F58F27800D1B1B4 /* 6502AllRAM.cpp in Sources */,
+				4B06AAD82C645F370034D014 /* MasterSystem.cpp in Sources */,
 				4BC5C3E022C994CD00795658 /* 68000MoveTests.mm in Sources */,
 				4B778F5923A5F2D00000D260 /* Z80.cpp in Sources */,
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 				4B778F0E23A5EC4F0000D260 /* Tape.cpp in Sources */,
 				4B778F2D23A5EF190000D260 /* MFMDiskController.cpp in Sources */,
 				4B7752C228217F5C0073E2C5 /* Spectrum.cpp in Sources */,
+				4B06AAD92C645F5D0034D014 /* SN76489.cpp in Sources */,
 				423BDC4A2AB24699008E37B6 /* 8088Tests.mm in Sources */,
 				4B778F2723A5EEF60000D260 /* BinaryDump.cpp in Sources */,
 				4BFCA1241ECBDCB400AC40C1 /* AllRAMProcessor.cpp in Sources */,
+				4B06AB042C6460D60034D014 /* 6560.cpp in Sources */,
+				4B06AB002C6460B70034D014 /* Keyboard.cpp in Sources */,
 				4B778F5223A5F22F0000D260 /* StaticAnalyser.cpp in Sources */,
 				4B778F4923A5F1F40000D260 /* StaticAnalyser.cpp in Sources */,
 				4BBF49AF1ED2880200AB3669 /* FUSETests.swift in Sources */,
 				4B778F4D23A5F20F0000D260 /* StaticAnalyser.cpp in Sources */,
+				4B06AAD72C645F330034D014 /* AppleIIgs.cpp in Sources */,
+				4B06AB082C64611F0034D014 /* ColecoVision.cpp in Sources */,
 				4B778F0423A5EBB00000D260 /* OricMFMDSK.cpp in Sources */,
 				4B7752BE28217F220073E2C5 /* MouseJoystick.cpp in Sources */,
 				4B8DF4D825465B7500F3433C /* IIgsMemoryMapTests.mm in Sources */,
 				4B3BA0CE1D318B44005DD7A7 /* C1540Bridge.mm in Sources */,
 				4B4F477C253530B7004245B8 /* Jeek816Tests.swift in Sources */,
+				4B06AB062C6460F40034D014 /* Atari2600.cpp in Sources */,
 				4B7752B928217F140073E2C5 /* Audio.cpp in Sources */,
 				4B778F0F23A5EC560000D260 /* PCMTrack.cpp in Sources */,
 				4B778F1123A5EC650000D260 /* FileHolder.cpp in Sources */,
 				4B778EFC23A5EB8B0000D260 /* AcornADF.cpp in Sources */,
+				4B06AB122C6461910034D014 /* Plus3.cpp in Sources */,
 				4B778F2023A5EDCE0000D260 /* HFV.cpp in Sources */,
 				4B778F3323A5F0FB0000D260 /* MassStorageDevice.cpp in Sources */,
 				4B75F979280D7C5100121055 /* 68000DecoderTests.mm in Sources */,
 				4B778F2C23A5EF0F0000D260 /* ZX8081.cpp in Sources */,
 				4B778F3023A5F0C50000D260 /* Macintosh.cpp in Sources */,
+				4B882F5C2C32199400D84031 /* MachineForTarget.cpp in Sources */,
+				4B06AAD32C645F1F0034D014 /* MSX.cpp in Sources */,
+				4B06AAD02C645F0A0034D014 /* EXDos.cpp in Sources */,
 				4B3BA0D11D318B44005DD7A7 /* TestMachine6502.mm in Sources */,
 				4B778F4623A5F1D80000D260 /* StaticAnalyser.cpp in Sources */,
 				4B778F1323A5EC890000D260 /* Z80Base.cpp in Sources */,
 				4B778F2923A5EF030000D260 /* CommodoreROM.cpp in Sources */,
+				4B06AADC2C645F720034D014 /* BD500.cpp in Sources */,
 				4B778F4823A5F1E70000D260 /* StaticAnalyser.cpp in Sources */,
 				4B92EACA1B7C112B00246143 /* 6502TimingTests.swift in Sources */,
 				4B778F2823A5EEF80000D260 /* Cartridge.cpp in Sources */,
+				4B06AAED2C6460040034D014 /* Sound.cpp in Sources */,
+				4B06AAF12C64602D0034D014 /* 6850.cpp in Sources */,
+				4B06AAF22C6460320034D014 /* MFP68901.cpp in Sources */,
 				4B7752B528217ED30073E2C5 /* SNA.cpp in Sources */,
 				4BEDA3C025B25563000C2DBD /* Decoder.cpp in Sources */,
 				4B2005432B804D6400420C5C /* ARMDecoderTests.mm in Sources */,
 				4B778F4C23A5F2090000D260 /* StaticAnalyser.cpp in Sources */,
 				4B778F2623A5EE350000D260 /* Acorn.cpp in Sources */,
 				4B7752C128217F490073E2C5 /* FAT.cpp in Sources */,
+				4B06AAFE2C6460A40034D014 /* ConfidenceSummary.cpp in Sources */,
 				4B778F5B23A5F2DE0000D260 /* Tape.cpp in Sources */,
 				4BB73EB71B587A5100552FC2 /* AllSuiteATests.swift in Sources */,
 				4B7752B228217EAE0073E2C5 /* StaticAnalyser.cpp in Sources */,
 				4B7752BC28217F1D0073E2C5 /* Disk.cpp in Sources */,
+				4B06AAE42C645FA50034D014 /* DiskIICard.cpp in Sources */,
 				4B04C899285E3DC800AA8FD6 /* 65816ComparativeTests.mm in Sources */,
+				4B06AAF92C64607C0034D014 /* AudioToggle.cpp in Sources */,
 				4B01A6881F22F0DB001FD6E3 /* Z80MemptrTests.swift in Sources */,
 				4B778EFA23A5EB790000D260 /* DMK.cpp in Sources */,
 				4BEE1EC122B5E2FD000A26A6 /* Encoder.cpp in Sources */,
+				4B06AACD2C645EE50034D014 /* Enterprise.cpp in Sources */,
 				4B7752AF28217E890073E2C5 /* DAT.cpp in Sources */,
 				4B121F9B1E06293F00BFDA12 /* PCMSegmentEventSourceTests.mm in Sources */,
 				4B778EFF23A5EB940000D260 /* D64.cpp in Sources */,
@@ -6442,78 +6578,111 @@
 				4B778F2423A5EDEE0000D260 /* PRG.cpp in Sources */,
 				4B778F5A23A5F2D50000D260 /* 6502.cpp in Sources */,
 				4B778F6223A5F35F0000D260 /* File.cpp in Sources */,
+				4B06AB0F2C6461780034D014 /* MultiProducer.cpp in Sources */,
 				4B778F3523A5F1040000D260 /* SCSI.cpp in Sources */,
 				4BD388882239E198002D14B5 /* 68000Tests.mm in Sources */,
 				4B8DF5142550D62A00F3433C /* 65816kromTests.swift in Sources */,
+				4B06AB022C6460CB0034D014 /* Typer.cpp in Sources */,
 				4BA91E1D216D85BA00F79557 /* MasterSystemVDPTests.mm in Sources */,
 				4B98A0611FFADCDE00ADF63B /* MSXStaticAnalyserTests.mm in Sources */,
 				4BE34438238389E10058E78F /* AtariSTVideoTests.mm in Sources */,
 				4BEF6AAC1D35D1C400E73575 /* DPLLTests.swift in Sources */,
 				4BE76CF922641ED400ACD6FA /* QLTests.mm in Sources */,
+				4B06AB0C2C6461590034D014 /* StaticAnalyser.cpp in Sources */,
 				4B43983A29620FC8006B0BFC /* 9918.cpp in Sources */,
 				4B778F0923A5EC150000D260 /* OricTAP.cpp in Sources */,
 				4B3BA0CF1D318B44005DD7A7 /* MOS6522Bridge.mm in Sources */,
 				4B778F6023A5F3460000D260 /* Disk.cpp in Sources */,
+				4B06AB142C64619E0034D014 /* MultiJoystickMachine.cpp in Sources */,
 				4B778F5C23A5F3070000D260 /* MSX.cpp in Sources */,
 				4B7752AA28217E370073E2C5 /* ROMCatalogue.cpp in Sources */,
 				4B778F0323A5EBB00000D260 /* FAT12.cpp in Sources */,
 				4B778F4023A5F1910000D260 /* z8530.cpp in Sources */,
 				4B778EFD23A5EB8E0000D260 /* AppleDSK.cpp in Sources */,
 				4B7752B728217EF40073E2C5 /* Chipset.cpp in Sources */,
+				4B06AAF72C64606E0034D014 /* DiskII.cpp in Sources */,
 				4B778EFB23A5EB7E0000D260 /* HFE.cpp in Sources */,
 				4BC751B21D157E61006C31D9 /* 6522Tests.swift in Sources */,
 				4B0DA67D282DCDF300C12F17 /* Instruction.cpp in Sources */,
+				4B06AAE12C645F8B0034D014 /* Video.cpp in Sources */,
 				4BFCA12B1ECBE7C400AC40C1 /* ZexallTests.swift in Sources */,
+				4B06AAD62C645F2D0034D014 /* AtariST.cpp in Sources */,
+				4B06AB132C6461970034D014 /* MultiConfigurable.cpp in Sources */,
 				4B778F2223A5EDDD0000D260 /* PulseQueuedTape.cpp in Sources */,
+				4B06AB112C64618B0034D014 /* Tape.cpp in Sources */,
 				4B051CB3267D3FF800CA44E8 /* EnterpriseNickTests.mm in Sources */,
 				4B9D0C4D22C7DA1A00DE1AD3 /* 68000ControlFlowTests.mm in Sources */,
 				4BB2A9AF1E13367E001A5C23 /* CRCTests.mm in Sources */,
+				4B06AAEE2C64600C0034D014 /* Vic20.cpp in Sources */,
+				4B06AB0A2C6461350034D014 /* TIASound.cpp in Sources */,
 				4BB0CAA727E51B6300672A88 /* DingusdevPowerPCTests.mm in Sources */,
+				4B06AACC2C645EDF0034D014 /* Archimedes.cpp in Sources */,
 				4B778F5623A5F2AF0000D260 /* CPM.cpp in Sources */,
 				4B778F1C23A5ED3F0000D260 /* TimedEventLoop.cpp in Sources */,
+				4B06AAFA2C6460800034D014 /* KonamiSCC.cpp in Sources */,
 				4B47770D26900685005C2340 /* EnterpriseDaveTests.mm in Sources */,
 				4B3BA0D01D318B44005DD7A7 /* MOS6532Bridge.mm in Sources */,
 				4B778F3823A5F11C0000D260 /* SegmentParser.cpp in Sources */,
 				4B778F0723A5EC150000D260 /* CommodoreTAP.cpp in Sources */,
 				4281683A2A37AFB4008ECD27 /* DispatcherTests.mm in Sources */,
+				4B06AAE52C645FAA0034D014 /* SCSICard.cpp in Sources */,
 				4B778F4123A5F19A0000D260 /* MemoryPacker.cpp in Sources */,
+				4B06AAE02C645F870034D014 /* Video.cpp in Sources */,
 				4B778F4423A5F1BE0000D260 /* CommodoreGCR.cpp in Sources */,
 				4B778EF923A5EB740000D260 /* MSA.cpp in Sources */,
 				4B4DEC07252BFA56004583AC /* 65816Base.cpp in Sources */,
 				4B7752A628217DF80073E2C5 /* Dave.cpp in Sources */,
 				4B778F2323A5EDE40000D260 /* Tape.cpp in Sources */,
 				4B7752A728217E060073E2C5 /* Blitter.cpp in Sources */,
+				4B06AAD22C645F190034D014 /* I2C.cpp in Sources */,
 				4B778F4F23A5F21C0000D260 /* StaticAnalyser.cpp in Sources */,
+				4B06AAE72C645FBC0034D014 /* DMAController.cpp in Sources */,
 				4B8DD3682633B2D400B3C866 /* SpectrumVideoContentionTests.mm in Sources */,
+				4B06AB162C6461AB0034D014 /* Keyboard.cpp in Sources */,
 				4B7752A928217E200073E2C5 /* 65816Storage.cpp in Sources */,
+				4B06AAFB2C6460920034D014 /* Keyboard.cpp in Sources */,
 				4BC62FF228A149300036AE59 /* NSData+dataWithContentsOfGZippedFile.m in Sources */,
+				4B06AB152C6461A20034D014 /* MultiKeyboardMachine.cpp in Sources */,
 				4B7752AC28217E6E0073E2C5 /* StaticAnalyser.cpp in Sources */,
 				4B778F1223A5EC720000D260 /* CRT.cpp in Sources */,
 				4B778EF423A5DB3A0000D260 /* C1540.cpp in Sources */,
 				4B778F3C23A5F16F0000D260 /* FIRFilter.cpp in Sources */,
+				4B06AB092C64612C0034D014 /* TIA.cpp in Sources */,
 				4B778F5423A5F2600000D260 /* UnformattedTrack.cpp in Sources */,
 				4B7752B028217E9A0073E2C5 /* StaticAnalyser.cpp in Sources */,
+				4B06AADA2C645F650034D014 /* MemorySlotHandler.cpp in Sources */,
 				4B778EF823A5EB6E0000D260 /* NIB.cpp in Sources */,
 				4B9D0C4B22C7D70A00DE1AD3 /* 68000BCDTests.mm in Sources */,
 				4B778F5E23A5F3230000D260 /* Oric.cpp in Sources */,
 				4B7752B828217F110073E2C5 /* Amiga.cpp in Sources */,
+				4B06AAEF2C6460180034D014 /* Keyboard.cpp in Sources */,
 				4B3BA0C31D318AEC005DD7A7 /* C1540Tests.swift in Sources */,
 				4BDA8235261E8E000021AA19 /* Z80ContentionTests.mm in Sources */,
+				4B882F592C2F9C6A00D84031 /* CPCShakerTests.mm in Sources */,
 				4B7752C328217F720073E2C5 /* Z80.cpp in Sources */,
+				4B06AACE2C645EEC0034D014 /* PCCompatible.cpp in Sources */,
+				4B06AB072C6461160034D014 /* StaticAnalyser.cpp in Sources */,
 				4B778F1A23A5ED320000D260 /* Video.cpp in Sources */,
 				4B778F3B23A5F1650000D260 /* KeyboardMachine.cpp in Sources */,
 				4B5D497C28513F870076E2F9 /* IPF.cpp in Sources */,
+				4B06AAF32C64603D0034D014 /* Keyboard.cpp in Sources */,
 				4B778F2E23A5F09E0000D260 /* IRQDelegatePortHandler.cpp in Sources */,
 				4B778EF323A5DB230000D260 /* PCMSegment.cpp in Sources */,
+				4B06AB0D2C6461610034D014 /* MultiMachine.cpp in Sources */,
+				4B06AAD52C645F290034D014 /* AppleII.cpp in Sources */,
+				4B06AAFC2C6460970034D014 /* Keyboard.cpp in Sources */,
 				4B778F0D23A5EC150000D260 /* ZX80O81P.cpp in Sources */,
 				4B1414621B58888700E04248 /* KlausDormannTests.swift in Sources */,
 				4B778EFE23A5EB910000D260 /* CPCDSK.cpp in Sources */,
 				4B778F5823A5F2C60000D260 /* Tape.cpp in Sources */,
 				4B7752B328217EB90073E2C5 /* State.cpp in Sources */,
+				4B06AB032C6460D00034D014 /* OPLL.cpp in Sources */,
+				4B06AAFD2C64609D0034D014 /* IMD.cpp in Sources */,
 				4B1414601B58885000E04248 /* WolfgangLorenzTests.swift in Sources */,
 				4BD4A8D01E077FD20020D856 /* PCMTrackTests.mm in Sources */,
 				4B778F2123A5EDD50000D260 /* TrackSerialiser.cpp in Sources */,
 				4B049CDD1DA3C82F00322067 /* BCDTest.swift in Sources */,
+				4B06AADF2C645F830034D014 /* Video.cpp in Sources */,
 				4BC6237226F94BCB00F83DFE /* MintermTests.mm in Sources */,
 				4B7752BF28217F250073E2C5 /* Sprites.cpp in Sources */,
 				4B778F3923A5F11C0000D260 /* Shifter.cpp in Sources */,
@@ -6521,10 +6690,14 @@
 				4B778F3623A5F1040000D260 /* Target.cpp in Sources */,
 				4B1D08061E0F7A1100763741 /* TimeTests.mm in Sources */,
 				4B75EBFE28FF9CA20088AB22 /* MacintoshVolume.cpp in Sources */,
+				4B06AB0B2C64614B0034D014 /* Electron.cpp in Sources */,
+				4B06AAF52C6460600034D014 /* Mouse.cpp in Sources */,
 				4B778F3D23A5F1750000D260 /* ncr5380.cpp in Sources */,
 				4BF701A026FFD32300996424 /* AmigaBlitterTests.mm in Sources */,
 				4B7752B428217ECB0073E2C5 /* ZXSpectrumTAP.cpp in Sources */,
 				4B778F6323A5F3630000D260 /* Tape.cpp in Sources */,
+				4B06AB012C6460C30034D014 /* Video.cpp in Sources */,
+				4B06AADD2C645F790034D014 /* Microdisc.cpp in Sources */,
 				4B778EF523A5DB440000D260 /* StaticAnalyser.cpp in Sources */,
 				4BEE1EC022B5E236000A26A6 /* MacGCRTests.mm in Sources */,
 				4B778F0623A5EC150000D260 /* CAS.cpp in Sources */,
@@ -6532,10 +6705,13 @@
 				4B778F3F23A5F1890000D260 /* MacintoshDoubleDensityDrive.cpp in Sources */,
 				4B778F1623A5ECA00000D260 /* Z80AllRAM.cpp in Sources */,
 				4BEDA40D25B2844B000C2DBD /* Decoder.cpp in Sources */,
+				4B06AAE62C645FB10034D014 /* ADB.cpp in Sources */,
 				4B778EF723A5EB670000D260 /* SSD.cpp in Sources */,
 				4BDA7F8329C4EA28007A10A5 /* 6809OperationMapperTests.mm in Sources */,
 				4B778F5723A5F2BB0000D260 /* ZX8081.cpp in Sources */,
+				4B06AACF2C645EF40034D014 /* i8272.cpp in Sources */,
 				4B778F2F23A5F0B10000D260 /* ScanTarget.cpp in Sources */,
+				4B882F5D2C3219A400D84031 /* AmstradCPC.cpp in Sources */,
 				4B69DEB72AB79E4F0055B217 /* Instruction.cpp in Sources */,
 				4BE90FFD22D5864800FB464D /* MacintoshVideoTests.mm in Sources */,
 				4B4F478A25367EDC004245B8 /* 65816AddressingTests.swift in Sources */,
@@ -6543,16 +6719,23 @@
 				4B778F0C23A5EC150000D260 /* TZX.cpp in Sources */,
 				4B778F1B23A5ED380000D260 /* Video.cpp in Sources */,
 				4B778F4723A5F1DD0000D260 /* StaticAnalyser.cpp in Sources */,
+				4B06AAF62C6460670034D014 /* DiskIIDrive.cpp in Sources */,
 				4B778F1923A5ED1B0000D260 /* 6502Storage.cpp in Sources */,
 				4B7752A828217E110073E2C5 /* Nick.cpp in Sources */,
 				42A5E80C2ABBE04600A0DD5D /* NeskellTests.swift in Sources */,
+				4B06AAE92C645FD30034D014 /* Jasmin.cpp in Sources */,
 				4B7752AE28217E830073E2C5 /* 2MG.cpp in Sources */,
+				4B06AB102C6461810034D014 /* SoundGenerator.cpp in Sources */,
 				4B08A2781EE39306008B7065 /* TestMachine.mm in Sources */,
 				4B778F1E23A5EDC00000D260 /* DriveSpeedAccumulator.cpp in Sources */,
 				4B778F4323A5F1B00000D260 /* ImplicitSectors.cpp in Sources */,
 				4B7752B128217EA30073E2C5 /* StaticAnalyser.cpp in Sources */,
 				4B778F5123A5F2290000D260 /* StaticAnalyser.cpp in Sources */,
+				4B06AB0E2C6461700034D014 /* MultiMediaTarget.cpp in Sources */,
 				42437B332AC70833006DFED1 /* HDV.cpp in Sources */,
+				4B06AAE82C645FCD0034D014 /* RP5C01.cpp in Sources */,
+				4B06AAEC2C645FF50034D014 /* Keyboard.cpp in Sources */,
+				4B06AAF02C6460240034D014 /* ReactiveDevice.cpp in Sources */,
 				4B7752C028217F3D0073E2C5 /* Line.cpp in Sources */,
 				4B7C7A00282C3BCA002D6C0B /* 68000flamewingTests.mm in Sources */,
 				4B778F0223A5EBA40000D260 /* MFMSectorDump.cpp in Sources */,
@@ -6561,6 +6744,7 @@
 				4B778F3E23A5F17C0000D260 /* IWM.cpp in Sources */,
 				4BD91D732401960C007BDC91 /* STX.cpp in Sources */,
 				4B778F1023A5EC5D0000D260 /* Drive.cpp in Sources */,
+				4B06AAF42C6460430034D014 /* ZX8081.cpp in Sources */,
 				4B9D0C4F22C7E0CF00DE1AD3 /* 68000RollShiftTests.mm in Sources */,
 			);
 			runOnlyForDeploymentPostprocessing = 0;

OSBindings/Mac/Clock Signal.xcodeproj/xcshareddata/xcschemes/Clock Signal.xcscheme

@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <Scheme
    LastUpgradeVersion = "1400"
-   version = "1.8">
+   version = "1.3">
    <BuildAction
       parallelizeBuildables = "YES"
       buildImplicitDependencies = "YES">

OSBindings/Mac/Clock Signal.xcodeproj/xcshareddata/xcschemes/Clock SignalTests.xcscheme

@@ -7,7 +7,7 @@
       buildImplicitDependencies = "YES">
    </BuildAction>
    <TestAction
-      buildConfiguration = "Debug"
+      buildConfiguration = "Release"
       selectedDebuggerIdentifier = "Xcode.DebuggerFoundation.Debugger.LLDB"
       selectedLauncherIdentifier = "Xcode.DebuggerFoundation.Launcher.LLDB"
       shouldUseLaunchSchemeArgsEnv = "YES">

OSBindings/Mac/Clock Signal/Info.plist

@@ -769,11 +769,11 @@
 	<key>CFBundlePackageType</key>
 	<string>APPL</string>
 	<key>CFBundleShortVersionString</key>
-	<string>24.05.27</string>
+	<string>24.09.09</string>
 	<key>CFBundleSignature</key>
 	<string>????</string>
 	<key>CFBundleVersion</key>
-	<string>24.05.27</string>
+	<string>24.09.09</string>
 	<key>LSApplicationCategoryType</key>
 	<string>public.app-category.entertainment</string>
 	<key>LSMinimumSystemVersion</key>

OSBindings/Mac/Clock SignalTests/65816ComparativeTests.mm

@@ -29,6 +29,16 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandlerT<type> {
 	std::unordered_map<AddressType, uint8_t> inventions;
 
 	Cycles perform_bus_operation(CPU::MOS6502Esque::BusOperation operation, AddressType address, uint8_t *value) {
+		// Check for a JAM; if one is found then record just five more bus cycles, arbitrarily.
+		if(jam_count) {
+			--jam_count;
+			if(!jam_count) {
+				throw StopException();
+			}
+		} else if(processor.is_jammed()) {
+			jam_count = 5;
+		}
+
 		// Record the basics of the operation.
 		auto &cycle = cycles.emplace_back();
 		cycle.operation = operation;
@@ -110,6 +120,7 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandlerT<type> {
 	int pc_overshoot = 0;
 	std::optional<AddressType> initial_pc;
 	bool allow_pc_repetition = false;
+	int jam_count = 0;
 
 	struct Cycle {
 		CPU::MOS6502Esque::BusOperation operation;

OSBindings/Mac/Clock SignalTests/8088Tests.mm

@@ -16,6 +16,7 @@
 #include <fstream>
 #include <unordered_map>
 #include <unordered_set>
+#include <vector>
 
 #include "NSData+dataWithContentsOfGZippedFile.h"
 

OSBindings/Mac/Clock SignalTests/ARMDecoderTests.mm

@@ -15,6 +15,7 @@
 
 #include <map>
 #include <sstream>
+#include <vector>
 
 using namespace InstructionSet::ARM;
 

OSBindings/Mac/Clock SignalTests/CPCShakerTests.mm

@@ -0,0 +1,332 @@
+//
+//  CPCShakerTests.m
+//  Clock SignalTests
+//
+//  Created by Thomas Harte on 28/06/2024.
+//  Copyright © 2024 Thomas Harte. All rights reserved.
+//
+
+#import <XCTest/XCTest.h>
+
+#include <array>
+#include <cassert>
+
+#include "CSL.hpp"
+#include "AmstradCPC.hpp"
+#include "../../../Analyser/Static/AmstradCPC/Target.hpp"
+#include "../../../Machines/AmstradCPC/Keyboard.hpp"
+#include "../../../Outputs/ScanTarget.hpp"
+#include "CSROMFetcher.hpp"
+#include "TimedMachine.hpp"
+#include "MediaTarget.hpp"
+#include "KeyboardMachine.hpp"
+#include "MachineForTarget.hpp"
+
+struct ScanTarget: public Outputs::Display::ScanTarget {
+	void set_modals(Modals modals) override {
+		modals_ = modals;
+	}
+	Scan *begin_scan() override {
+		return &scan_;
+	}
+	uint8_t *begin_data(size_t, size_t) override {
+		return data_.data();
+	}
+
+
+	void end_scan() override {
+		// Empirical, CPC-specific observation: x positions end up
+		// being multiplied by 61 compared to a 1:1 pixel sampling at
+		// the CPC's highest resolution.
+		const int WidthDivider = 61;
+
+		const int src_pixels = scan_.end_points[1].data_offset - scan_.end_points[0].data_offset;
+		const int dst_pixels = (scan_.end_points[1].x - scan_.end_points[0].x) / WidthDivider;
+
+		const int step = (src_pixels << 16) / dst_pixels;
+		int position = 0;
+
+		const auto x1 = scan_.end_points[0].x / WidthDivider;
+		const auto x2 = scan_.end_points[1].x / WidthDivider;
+
+		uint8_t *const line = &raw_image_[line_ * ImageWidth];
+		if(x_ < x1) {
+			std::fill(&line[x_], &line[x1], 0);
+		}
+		for(int x = x1; x < x2; x++) {
+			line[x] = data_[position >> 16];
+			position += step;
+		}
+		x_ = x2;
+	}
+	void announce(Event event, bool, const Scan::EndPoint &, uint8_t) override {
+		switch(event) {
+			case Event::EndHorizontalRetrace: {
+				if(line_ == ImageHeight - 1) break;
+
+				if(x_ < ImageWidth) {
+					uint8_t *const line = &raw_image_[line_ * ImageWidth];
+					std::fill(&line[x_], &line[ImageWidth], 0);
+				}
+
+				++line_;
+				x_ = 0;
+			} break;
+			case Event::EndVerticalRetrace:
+				std::fill(&raw_image_[line_ * ImageWidth], &raw_image_[ImageHeight * ImageWidth], 0);
+				line_ = 0;
+				x_ = 0;
+			break;
+			default: break;
+		}
+	}
+
+	NSBitmapImageRep *image_representation() {
+		NSBitmapImageRep *const result =
+			[[NSBitmapImageRep alloc]
+				initWithBitmapDataPlanes:NULL
+				pixelsWide:ImageWidth
+				pixelsHigh:ImageHeight
+				bitsPerSample:8
+				samplesPerPixel:4
+				hasAlpha:YES
+				isPlanar:NO
+				colorSpaceName:NSDeviceRGBColorSpace
+				bytesPerRow:4 * ImageWidth
+				bitsPerPixel:0];
+		uint8_t *const data = result.bitmapData;
+
+		for(int c = 0; c < ImageWidth * ImageHeight; c++) {
+			data[c * 4 + 0] = ((raw_image_[c] >> 4) & 3) * 127;
+			data[c * 4 + 1] = ((raw_image_[c] >> 2) & 3) * 127;
+			data[c * 4 + 2] = ((raw_image_[c] >> 0) & 3) * 127;
+			data[c * 4 + 3] = 0xff;
+		}
+
+		return result;
+	}
+
+
+private:
+	Modals modals_;
+	Scan scan_;
+	std::array<uint8_t, 2048> data_;
+	int line_ = 0;
+	int x_ = 0;
+
+	static constexpr int ImageWidth = 914;
+	static constexpr int ImageHeight = 312;
+	std::array<uint8_t, ImageWidth*ImageHeight> raw_image_;
+};
+
+struct SSMDelegate: public AmstradCPC::Machine::SSMDelegate {
+	SSMDelegate(ScanTarget &scan_target) : scan_target_(scan_target) {
+		temp_dir_ = NSTemporaryDirectory();
+		NSLog(@"Outputting to %@", temp_dir_);
+	}
+
+	void set_crtc(int number) {
+		crtc_ = number;
+	}
+
+	void perform(uint16_t code) {
+		if(!code) {
+			// A code of 0000 is supposed to end a wait0000 command; at present
+			// there seem to be no wait0000 commands to unblock.
+			return;
+		}
+
+		NSData *const data =
+			[scan_target_.image_representation() representationUsingType:NSPNGFileType properties:@{}];
+		NSString *const name = [temp_dir_ stringByAppendingPathComponent:[NSString stringWithFormat:@"CLK_%d_%04x.png", crtc_, code]];
+		[data
+			writeToFile:name
+			atomically:NO];
+		NSLog(@"Wrote %@", name);
+	}
+
+private:
+	ScanTarget &scan_target_;
+	NSString *temp_dir_;
+	int crtc_ = 0;
+};
+
+//
+// Runs a local capture of the test cases found at https://shaker.logonsystem.eu
+//
+@interface CPCShakerTests : XCTestCase
+@end
+
+@implementation CPCShakerTests {}
+
+- (void)testCSLPath:(NSString *)path name:(NSString *)name {
+	using namespace Storage::Automation;
+	const auto steps = CSL::parse([[path stringByAppendingPathComponent:name] UTF8String]);
+
+	ScanTarget scan_target;
+	SSMDelegate ssm_delegate(scan_target);
+
+	std::unique_ptr<Machine::DynamicMachine> lazy_machine;
+	CSL::KeyDelay key_delay;
+	using Target = Analyser::Static::AmstradCPC::Target;
+	Target target;
+	target.catch_ssm_codes = true;
+	target.model = Target::Model::CPC6128;
+
+	NSString *diskPath;
+	const auto machine = [&]() -> Machine::DynamicMachine& {
+		if(!lazy_machine) {
+			Machine::Error error;
+			lazy_machine = Machine::MachineForTarget(&target, CSROMFetcher(), error);
+			static_cast<AmstradCPC::Machine *>(lazy_machine->raw_pointer())
+				->set_ssm_delegate(&ssm_delegate);
+			lazy_machine->scan_producer()->set_scan_target(&scan_target);
+
+			if(diskPath) {
+				const auto media = Analyser::Static::GetMedia(diskPath.UTF8String);
+				lazy_machine->media_target()->insert_media(media);
+			}
+		}
+		return *lazy_machine;
+	};
+	const auto delay = [&](uint64_t micros) {
+		machine().timed_machine()->run_for((double)micros / 1'000'000.0);
+	};
+
+	using Type = CSL::Instruction::Type;
+	for(const auto &step: steps) {
+		switch(step.type) {
+			case Type::Version:
+				if(std::get<std::string>(step.argument) != "1.0") {
+					XCTAssert(false, "Unrecognised file version");
+				}
+			break;
+
+			case Type::CRTCSelect: {
+				const auto argument = static_cast<int>(std::get<uint64_t>(step.argument));
+				switch(argument) {
+					default:
+						NSLog(@"Unrecognised CRTC type %d", argument);
+					break;
+					case 0:	target.crtc_type = Target::CRTCType::Type0;	break;
+					case 1:	target.crtc_type = Target::CRTCType::Type1;	break;
+					case 2:	target.crtc_type = Target::CRTCType::Type2;	break;
+					case 3:	target.crtc_type = Target::CRTCType::Type3;	break;
+				}
+				ssm_delegate.set_crtc(argument);
+			} break;
+
+			case Type::Reset:
+				lazy_machine.reset();
+			break;
+
+			case Type::Wait:
+				delay(std::get<uint64_t>(step.argument));
+			break;
+
+			case Type::DiskInsert: {
+				const auto &disk = std::get<CSL::DiskInsert>(step.argument);
+				XCTAssertEqual(disk.drive, 0);	// Only drive 0 is supported for now.
+
+				NSString *diskName = [NSString stringWithUTF8String:disk.file.c_str()];
+				diskPath =
+					[[NSBundle bundleForClass:[self class]]
+						pathForResource:diskName ofType:nil inDirectory:@"Shaker"];
+				XCTAssertNotNil(diskPath);
+
+				if(lazy_machine) {
+					const auto media = Analyser::Static::GetMedia(diskPath.UTF8String);
+					machine().media_target()->insert_media(media);
+				}
+			} break;
+
+			case Type::KeyDelay:
+				key_delay = std::get<CSL::KeyDelay>(step.argument);
+			break;
+
+			case Type::KeyOutput: {
+				auto &key_target = *machine().keyboard_machine();
+
+				const auto &events = std::get<std::vector<CSL::KeyEvent>>(step.argument);
+				bool last_down = false;
+				for(const auto &event: events) {
+					// Apply the interpress delay before if this is a second consecutive press;
+					// if this is a release then apply the regular key delay.
+					if(event.down && !last_down) {
+						delay(key_delay.interpress_delay);
+					} else if(!event.down) {
+						delay(key_delay.press_delay);
+					}
+
+					key_target.set_key_state(event.key, event.down);
+					last_down = event.down;
+
+					// If this was the release of a carriage return, wait some more after release.
+					if(key_delay.carriage_return_delay && (event.key == AmstradCPC::Key::KeyEnter || event.key == AmstradCPC::Key::KeyReturn)) {
+						delay(*key_delay.carriage_return_delay);
+					}
+				}
+			} break;
+
+			case Type::LoadCSL:
+				// Quick fix: just recurse.
+				[self
+					testCSLPath:path
+					name:
+						[NSString stringWithUTF8String:
+							(std::get<std::string>(step.argument) + ".csl").c_str()
+						]];
+			break;
+
+			default:
+				XCTAssert(false, "Unrecognised command: %d", step.type);
+			break;
+		}
+	}
+}
+
+- (void)testModulePath:(NSString *)path name:(NSString *)name {
+	NSString *basePath =
+		[[NSBundle bundleForClass:[self class]]
+			pathForResource:@"Shaker"
+			ofType:nil];
+	[self testCSLPath:[basePath stringByAppendingPathComponent:path] name:name];
+}
+
+- (void)testModuleA {
+	[self testModulePath:@"MODULE A" name:@"SHAKE26A-0.CSL"];
+//	[self testModulePath:@"MODULE A" name:@"SHAKE26A-1.CSL"];
+//	[self testModulePath:@"MODULE A" name:@"SHAKE26A-2.CSL"];
+//	[self testModulePath:@"MODULE A" name:@"SHAKE26A-3.CSL"];
+//	[self testModulePath:@"MODULE A" name:@"SHAKE26A-4.CSL"];
+}
+- (void)testModuleB {
+	[self testModulePath:@"MODULE B" name:@"SHAKE26B-0.CSL"];
+//	[self testModulePath:@"MODULE B" name:@"SHAKE26B-1.CSL"];
+//	[self testModulePath:@"MODULE B" name:@"SHAKE26B-2.CSL"];
+//	[self testModulePath:@"MODULE B" name:@"SHAKE26B-3.CSL"];
+//	[self testModulePath:@"MODULE B" name:@"SHAKE26B-4.CSL"];
+}
+- (void)testModuleC {
+	[self testModulePath:@"MODULE C" name:@"SHAKE26C-0.CSL"];
+//	[self testModulePath:@"MODULE C" name:@"SHAKE26C-1.CSL"];
+//	[self testModulePath:@"MODULE C" name:@"SHAKE26C-2.CSL"];
+//	[self testModulePath:@"MODULE C" name:@"SHAKE26C-3.CSL"];
+//	[self testModulePath:@"MODULE C" name:@"SHAKE26C-4.CSL"];
+}
+- (void)testModuleD {
+	[self testModulePath:@"MODULE D" name:@"SHAKE26D-0.CSL"];
+//	[self testModulePath:@"MODULE D" name:@"SHAKE26D-1.CSL"];
+//	[self testModulePath:@"MODULE D" name:@"SHAKE26D-2.CSL"];
+//	[self testModulePath:@"MODULE D" name:@"SHAKE26D-3.CSL"];
+//	[self testModulePath:@"MODULE D" name:@"SHAKE26D-4.CSL"];
+}
+- (void)testModuleE {
+	[self testModulePath:@"MODULE E" name:@"SHAKE26E-0.CSL"];
+//	[self testModulePath:@"MODULE E" name:@"SHAKE26E-1.CSL"];
+//	[self testModulePath:@"MODULE E" name:@"SHAKE26E-2.CSL"];
+//	[self testModulePath:@"MODULE E" name:@"SHAKE26E-3.CSL"];
+//	[self testModulePath:@"MODULE E" name:@"SHAKE26E-4.CSL"];
+}
+
+@end

OSBindings/Mac/Clock SignalTests/Shaker/MODULE A/SHAKE26A-0.CSL

@@ -0,0 +1,297 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26A du DSK SHAKER26.DSK en CRTC 0
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 0
+reset
+wait 3000000 
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26A"\(RET)'
+wait 10000000
+;
+; test 1
+key_output '1'		
+wait 800000			; fin affichage 1er ecran & ssm 595215
+key_output ' ' 
+wait 800000			; fin affichage 2nd ecran & ssm 659451
+key_output ' '
+wait 800000			; fin affichage 3eme ecran & ssm 627963
+key_output ' '
+wait 800000			; fin affichage 4eme ecran & ssm 698883
+key_output ' '
+wait 800000			; fin affichage 5eme ecran & ssm 551415
+key_output ' '
+wait 1000000		; retour menu
+; 
+; test 2
+key_output '2'	
+wait 800000			; 519961 crt 0 1 ecran 
+key_output ' '  
+wait 800000			; 2 ecrans 
+wait 800000			;
+key_output ' '  
+wait 800000			; 723923
+key_output ' '
+wait 800000			; 599040
+key_output ' '
+wait 1000000		; retour menu
+;
+; test 3
+key_output '3'
+wait 800000		; 596058
+wait 1500000	; 1337856
+key_output ' ' 
+wait 800000		; 730624
+wait 1500000	; 1337856
+key_output ' ' 
+wait 800000		; 750685
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 710656
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 726016
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 726952
+wait 800000	  ; 698880
+key_output ' ' 
+wait 1000000	; 845824
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 666112
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 666112
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 706048
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 730624
+wait 800000	  ; 698880
+key_output ' ' 
+wait 900000		; 745984
+wait 800000	  ; 698880
+key_output ' ' 
+wait 900000		; 805888
+wait 800000	  ; 698880
+key_output ' ' 
+wait 1000000	; 865792
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 686080
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 686080
+wait 800000	  ; 698880
+key_output ' ' 
+wait 10000000
+;
+key_output '4' 
+wait 9000000	; 6743019
+key_output ' ' 
+wait 1000000
+;
+key_output '5'
+wait 800000		; 434016
+key_output ' ' 
+wait 800000		; 547328
+key_output ' ' 
+wait 800000		; 567296
+key_output ' ' 
+wait 800000		; 587264
+key_output ' ' 
+wait 800000		; 607232
+key_output ' ' 
+wait 1000000
+;
+key_output '6'
+wait 800000	; 473960
+key_output ' ' 
+wait 800000	; 607232
+key_output ' ' 
+wait 800000	; 627200
+key_output ' ' 
+wait 800000	; 647168
+key_output ' ' 
+wait 800000	; 667136
+key_output ' ' 
+wait 1000000
+;
+key_output '7'
+wait 800000		; 473957
+key_output ' ' 
+wait 800000		; 667072
+key_output ' ' 
+wait 800000		; 527296
+key_output ' ' 
+wait 800000		; 547264
+key_output ' ' 
+wait 800000		; 567232
+key_output ' ' 
+wait 1000000
+;
+key_output '8'
+wait 800000		; 431083
+key_output ' ' 
+wait 1000000
+;
+key_output '9'
+wait 800000		; 474048
+key_output ' ' 
+wait 800000		; 559104
+key_output ' ' 
+wait 800000		; 598363
+key_output ' ' 
+wait 1000000
+;
+key_output 'E'
+wait 800000		; 514468
+key_output ' ' 
+wait 1000000
+;
+key_output 'R'
+wait 800000		; 592695
+wait 1200000	; 998400
+key_output ' ' 
+wait 800000		; 599040
+wait 1200000  ; 998400
+key_output ' ' 
+wait 800000		; 658944
+wait 1200000  ; 998400
+key_output ' ' 
+wait 1000000
+;
+key_output 'T'
+wait 800000		; 531832
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 638976
+key_output ' ' 
+wait 1000000
+;
+key_output 'Y'
+wait 800000		; 511931
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000	; ???
+key_output ' ' 
+wait 1000000
+;
+key_output 'U'
+wait 14000000	; 11803953+1007210
+key_output ' '
+wait 1000000
+;
+key_output 'I'
+wait 2200000	; 2013010
+key_output ' '
+wait 2200000	; 2315008
+key_output ' '
+wait 5000000	; 4233216
+key_output ' '
+wait 35000000	; 31301630
+key_output ' '
+wait 2000000	; 1557507
+key_output ' '
+wait 1000000
+;
+key_output 'O'
+wait 800000		; 576098
+key_output ' '
+wait 800000		; 698880
+key_output ' '
+wait 800000		; 698880
+key_output ' '
+wait 800000		; 599040
+key_output ' '
+wait 800000		; 497671
+key_output ' '
+wait 800000		; 469504
+key_output ' '
+wait 800000		; 522696
+key_output ' '
+wait 800000		; 547978
+key_output ' '
+wait 800000		; 579072
+; crtc 1
+;key_output ' '
+;wait 800000		; 482251
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 519680
+key_output ' '
+wait 1000000
+;
+key_output 'P'
+wait 450000		; 427222
+wait 5200000	; 5111808
+key_output ' '
+wait 800000		; 529408
+key_output ' '
+wait 800000		; 489472
+key_output ' '
+wait 800000		; 449536
+key_output ' '
+wait 800000		; 509440
+key_output ' '
+wait 800000		; 587307
+key_output ' '
+wait 800000		; 479104
+key_output ' '
+wait 800000		; 479360
+key_output ' '
+wait 800000		; 490944
+key_output ' '
+wait 800000		; 638464
+key_output ' '
+wait 800000		; 619008
+key_output ' '
+wait 1000000
+;
+csl_load 'SHAKE26A-1'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE A/SHAKE26A-1.CSL

@@ -0,0 +1,297 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26A du DSK SHAKER26.DSK en CRTC 1
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 1
+reset
+wait 3000000 
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26A"\(RET)'
+wait 10000000
+;
+; test 1
+key_output '1'		
+wait 800000			; fin affichage 1er ecran & ssm 595215
+key_output ' ' 
+wait 800000			; fin affichage 2nd ecran & ssm 659451
+key_output ' '
+wait 800000			; fin affichage 3eme ecran & ssm 627963
+key_output ' '
+wait 800000			; fin affichage 4eme ecran & ssm 698883
+key_output ' '
+wait 800000			; fin affichage 5eme ecran & ssm 551415
+key_output ' '
+wait 1000000		; retour menu
+; 
+; test 2
+key_output '2'	
+wait 800000			; 519961 crt 0 1 ecran 
+wait 800000 		; 2 ecrans 
+key_output ' '  
+wait 800000			;
+key_output ' '  
+wait 800000			; 723923
+key_output ' '
+wait 800000			; 599040
+key_output ' '
+wait 1000000		; retour menu
+;
+; test 3
+key_output '3'
+wait 800000		; 596058
+wait 1500000	; 1337856
+key_output ' ' 
+wait 800000		; 730624
+wait 1500000	; 1337856
+key_output ' ' 
+wait 800000		; 750685
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 710656
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 726016
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 726952
+wait 800000	  ; 698880
+key_output ' ' 
+wait 1000000	; 845824
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 666112
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 666112
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 706048
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 730624
+wait 800000	  ; 698880
+key_output ' ' 
+wait 900000		; 745984
+wait 800000	  ; 698880
+key_output ' ' 
+wait 900000		; 805888
+wait 800000	  ; 698880
+key_output ' ' 
+wait 1000000	; 865792
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 686080
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 686080
+wait 800000	  ; 698880
+key_output ' ' 
+wait 10000000
+;
+key_output '4' 
+wait 8000000	; 6743019
+key_output ' ' 
+wait 1000000
+;
+key_output '5'
+wait 800000		; 434016
+key_output ' ' 
+wait 800000		; 547328
+key_output ' ' 
+wait 800000		; 567296
+key_output ' ' 
+wait 800000		; 587264
+key_output ' ' 
+wait 800000		; 607232
+key_output ' ' 
+wait 1000000
+;
+key_output '6'
+wait 800000	; 473960
+key_output ' ' 
+wait 800000	; 607232
+key_output ' ' 
+wait 800000	; 627200
+key_output ' ' 
+wait 800000	; 647168
+key_output ' ' 
+wait 800000	; 667136
+key_output ' ' 
+wait 1000000
+;
+key_output '7'
+wait 800000		; 473957
+key_output ' ' 
+wait 800000		; 667072
+key_output ' ' 
+wait 800000		; 527296
+key_output ' ' 
+wait 800000		; 547264
+key_output ' ' 
+wait 800000		; 567232
+key_output ' ' 
+wait 1000000
+;
+key_output '8'
+wait 800000		; 431083
+key_output ' ' 
+wait 1000000
+;
+key_output '9'
+wait 800000		; 474048
+key_output ' ' 
+wait 800000		; 559104
+key_output ' ' 
+wait 800000		; 598363
+key_output ' ' 
+wait 1000000
+;
+key_output 'E'
+wait 800000		; 514468
+key_output ' ' 
+wait 1000000
+;
+key_output 'R'
+wait 800000		; 592695
+wait 1200000	; 998400
+key_output ' ' 
+wait 800000		; 599040
+wait 1200000  ; 998400
+key_output ' ' 
+wait 800000		; 658944
+wait 1200000  ; 998400
+key_output ' ' 
+wait 1000000
+;
+key_output 'T'
+wait 800000		; 531832
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 638976
+key_output ' ' 
+wait 1000000
+;
+key_output 'Y'
+wait 800000		; 511931
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000	; ???
+key_output ' ' 
+wait 1000000
+;
+key_output 'U'
+wait 14000000	; 11803953+1007210
+key_output ' '
+wait 1000000
+;
+key_output 'I'
+wait 2200000	; 2013010
+key_output ' '
+wait 2200000	; 2315008
+key_output ' '
+wait 5000000	; 4233216
+key_output ' '
+wait 35000000	; 31301630
+key_output ' '
+wait 2000000	; 1557507
+key_output ' '
+wait 1000000
+;
+key_output 'O'
+wait 800000		; 576098
+key_output ' '
+wait 800000		; 698880
+key_output ' '
+wait 800000		; 698880
+key_output ' '
+wait 800000		; 599040
+key_output ' '
+wait 800000		; 497671
+key_output ' '
+wait 800000		; 469504
+key_output ' '
+wait 800000		; 522696
+key_output ' '
+wait 800000		; 547978
+key_output ' '
+wait 800000		; 579072
+; crtc 1
+;key_output ' '
+;wait 800000		; 482251
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 519680
+key_output ' '
+wait 1000000
+;
+key_output 'P'
+wait 450000		; 427222
+wait 5200000	; 5111808
+key_output ' '
+wait 800000		; 529408
+key_output ' '
+wait 800000		; 489472
+key_output ' '
+wait 800000		; 449536
+key_output ' '
+wait 800000		; 509440
+key_output ' '
+wait 800000		; 587307
+key_output ' '
+wait 800000		; 479104
+key_output ' '
+wait 800000		; 479360
+key_output ' '
+wait 800000		; 490944
+key_output ' '
+wait 800000		; 638464
+key_output ' '
+wait 800000		; 619008
+key_output ' '
+wait 1000000
+
+csl_load 'SHAKE26A-2'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE A/SHAKE26A-2.CSL

@@ -0,0 +1,267 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26A du DSK SHAKER26.DSK en CRTC 2
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 2
+reset
+wait 3000000 
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26A"\(RET)'
+wait 10000000
+;
+; test 1
+key_output '1'		
+wait 800000			; fin affichage 1er ecran & ssm 595215
+key_output ' ' 
+wait 800000			; fin affichage 2nd ecran & ssm 659451
+key_output ' '
+wait 800000			; fin affichage 3eme ecran & ssm 627963
+key_output ' '
+wait 800000			; fin affichage 4eme ecran & ssm 698883
+key_output ' '
+wait 800000			; fin affichage 5eme ecran & ssm 551415
+key_output ' '
+wait 1000000		; retour menu
+; 
+; test 2
+key_output '2'	
+wait 800000			; 519961 crt 0 1 ecran 
+key_output ' '  
+wait 800000			; 2 ecrans 
+wait 800000			;
+key_output ' '  
+wait 800000			; 723923
+key_output ' '
+wait 800000			; 599040
+key_output ' '
+wait 1000000		; retour menu
+;
+; test 3
+key_output '3'
+wait 800000		; 596058
+wait 1500000	; 1337856
+key_output ' ' 
+wait 800000		; 730624
+wait 1500000	; 1337856
+key_output ' ' 
+wait 800000		; 750685
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 710656
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 726016
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 726952
+wait 800000	  ; 698880
+key_output ' ' 
+wait 1000000	; 845824
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 666112
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 666112
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 706048
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 730624
+wait 800000	  ; 698880
+key_output ' ' 
+wait 900000		; 745984
+wait 800000	  ; 698880
+key_output ' ' 
+wait 900000		; 805888
+wait 800000	  ; 698880
+key_output ' ' 
+wait 1000000	; 865792
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 686080
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 686080
+wait 800000	  ; 698880
+key_output ' ' 
+wait 10000000
+;
+key_output '4' 
+wait 8000000	; 6743019
+key_output ' ' 
+wait 1000000
+;
+key_output '8'
+wait 800000		; 431083
+key_output ' ' 
+wait 1000000
+;
+key_output '9'
+wait 800000		; 474048
+key_output ' ' 
+wait 800000		; 559104
+key_output ' ' 
+wait 800000		; 598363
+key_output ' ' 
+wait 1000000
+;
+key_output 'E'
+wait 800000		; 514468
+key_output ' ' 
+wait 1000000
+;
+key_output 'R'
+wait 800000		; 592695
+wait 1200000	; 998400
+key_output ' ' 
+wait 800000		; 599040
+wait 1200000  ; 998400
+key_output ' ' 
+wait 800000		; 658944
+wait 1200000  ; 998400
+key_output ' ' 
+wait 1000000
+;
+key_output 'T'
+wait 800000		; 531832
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 638976
+key_output ' ' 
+wait 1000000
+;
+key_output 'Y'
+wait 800000		; 511931
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000	; ???
+key_output ' ' 
+wait 1000000
+;
+key_output 'U'
+wait 14000000	; 11803953+1007210
+key_output ' '
+wait 1000000
+;
+key_output 'I'
+wait 2200000	; 2013010
+key_output ' '
+wait 2200000	; 2315008
+key_output ' '
+wait 5000000	; 4233216
+key_output ' '
+wait 35000000	; 31301630
+key_output ' '
+wait 2000000	; 1557507
+key_output ' '
+wait 1000000
+;
+key_output 'O'
+wait 800000		; 576098
+key_output ' '
+wait 800000		; 698880
+key_output ' '
+wait 800000		; 698880
+key_output ' '
+wait 800000		; 599040
+key_output ' '
+wait 800000		; 497671
+key_output ' '
+wait 800000		; 469504
+key_output ' '
+wait 800000		; 522696
+key_output ' '
+wait 800000		; 547978
+key_output ' '
+wait 800000		; 579072
+; crtc 1
+;key_output ' '
+;wait 800000		; 482251
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 519680
+key_output ' '
+wait 1000000
+;
+key_output 'P'
+wait 450000		; 427222
+wait 5200000	; 5111808
+key_output ' '
+wait 800000		; 529408
+key_output ' '
+wait 800000		; 489472
+key_output ' '
+wait 800000		; 449536
+key_output ' '
+wait 800000		; 509440
+key_output ' '
+wait 800000		; 587307
+key_output ' '
+wait 800000		; 479104
+key_output ' '
+wait 800000		; 479360
+key_output ' '
+wait 800000		; 490944
+key_output ' '
+wait 800000		; 638464
+key_output ' '
+wait 800000		; 619008
+key_output ' '
+wait 1000000
+;
+; crtc 2
+;
+key_output '\(COP)'
+wait 8500000		; 8313240
+wait 500000		; 319488
+key_output ' '
+wait 1000000
+;
+;
+csl_load 'SHAKE26A-4'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE A/SHAKE26A-3.CSL

@@ -0,0 +1,296 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26A du DSK SHAKER26.DSK en CRTC 3
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 3
+reset
+wait 3000000 
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26A"\(RET)'
+wait 10000000
+;
+; test 1
+key_output '1'		
+wait 800000			; fin affichage 1er ecran & ssm 595215
+key_output ' ' 
+wait 800000			; fin affichage 2nd ecran & ssm 659451
+key_output ' '
+wait 800000			; fin affichage 3eme ecran & ssm 627963
+key_output ' '
+wait 800000			; fin affichage 4eme ecran & ssm 698883
+key_output ' '
+wait 800000			; fin affichage 5eme ecran & ssm 551415
+key_output ' '
+wait 1000000		; retour menu
+; 
+; test 2
+key_output '2'	
+wait 800000			; 519961 crt 0 1 ecran 
+key_output ' '  
+wait 800000			; 2 ecrans 
+wait 800000			;
+key_output ' '  
+wait 800000			; 723923
+key_output ' '
+wait 800000			; 599040
+key_output ' '
+wait 1000000		; retour menu
+;
+; test 3
+key_output '3'
+wait 800000		; 596058
+wait 1500000	; 1337856
+key_output ' ' 
+wait 800000		; 730624
+wait 1500000	; 1337856
+key_output ' ' 
+wait 800000		; 750685
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 710656
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 726016
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 726952
+wait 800000	  ; 698880
+key_output ' ' 
+wait 1000000	; 845824
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 666112
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 666112
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 706048
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 730624
+wait 800000	  ; 698880
+key_output ' ' 
+wait 900000		; 745984
+wait 800000	  ; 698880
+key_output ' ' 
+wait 900000		; 805888
+wait 800000	  ; 698880
+key_output ' ' 
+wait 1000000	; 865792
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 686080
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 686080
+wait 800000	  ; 698880
+key_output ' ' 
+wait 10000000
+;
+key_output '4' 
+wait 8000000	; 6743019
+key_output ' ' 
+wait 1000000
+;
+key_output '5'
+wait 800000		; 434016
+key_output ' ' 
+wait 800000		; 547328
+key_output ' ' 
+wait 800000		; 567296
+key_output ' ' 
+wait 800000		; 587264
+key_output ' ' 
+wait 800000		; 607232
+key_output ' ' 
+wait 1000000
+;
+key_output '6'
+wait 800000	; 473960
+key_output ' ' 
+wait 800000	; 607232
+key_output ' ' 
+wait 800000	; 627200
+key_output ' ' 
+wait 800000	; 647168
+key_output ' ' 
+wait 800000	; 667136
+key_output ' ' 
+wait 1000000
+;
+key_output '7'
+wait 800000		; 473957
+key_output ' ' 
+wait 800000		; 667072
+key_output ' ' 
+wait 800000		; 527296
+key_output ' ' 
+wait 800000		; 547264
+key_output ' ' 
+wait 800000		; 567232
+key_output ' ' 
+wait 1000000
+;
+key_output '8'
+wait 800000		; 431083
+key_output ' ' 
+wait 1000000
+;
+key_output '9'
+wait 800000		; 474048
+key_output ' ' 
+wait 800000		; 559104
+key_output ' ' 
+wait 800000		; 598363
+key_output ' ' 
+wait 1000000
+;
+key_output 'E'
+wait 800000		; 514468
+key_output ' ' 
+wait 1000000
+;
+key_output 'R'
+wait 800000		; 592695
+wait 1200000	; 998400
+key_output ' ' 
+wait 800000		; 599040
+wait 1200000  ; 998400
+key_output ' ' 
+wait 800000		; 658944
+wait 1200000  ; 998400
+key_output ' ' 
+wait 1000000
+;
+key_output 'T'
+wait 800000		; 531832
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 638976
+key_output ' ' 
+wait 1000000
+;
+key_output 'Y'
+wait 800000		; 511931
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000	; ???
+key_output ' ' 
+wait 1000000
+;
+key_output 'U'
+wait 14000000	; 11803953+1007210
+key_output ' '
+wait 1000000
+;
+key_output 'I'
+wait 2200000	; 2013010
+key_output ' '
+wait 2200000	; 2315008
+key_output ' '
+wait 5000000	; 4233216
+key_output ' '
+wait 35000000	; 31301630
+key_output ' '
+wait 2000000	; 1557507
+key_output ' '
+wait 1000000
+;
+key_output 'O'
+wait 800000		; 576098
+key_output ' '
+wait 800000		; 698880
+key_output ' '
+wait 800000		; 698880
+key_output ' '
+wait 800000		; 599040
+key_output ' '
+wait 800000		; 497671
+key_output ' '
+wait 800000		; 469504
+key_output ' '
+wait 800000		; 522696
+key_output ' '
+wait 800000		; 547978
+key_output ' '
+wait 800000		; 579072
+; crtc 1
+;key_output ' '
+;wait 800000		; 482251
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 519680
+key_output ' '
+wait 1000000
+;
+key_output 'P'
+wait 450000		; 427222
+wait 5200000	; 5111808
+key_output ' '
+wait 800000		; 529408
+key_output ' '
+wait 800000		; 489472
+key_output ' '
+wait 800000		; 449536
+key_output ' '
+wait 800000		; 509440
+key_output ' '
+wait 800000		; 587307
+key_output ' '
+wait 800000		; 479104
+key_output ' '
+wait 800000		; 479360
+key_output ' '
+wait 800000		; 490944
+key_output ' '
+wait 800000		; 638464
+key_output ' '
+wait 800000		; 619008
+key_output ' '
+wait 1000000
+reset

OSBindings/Mac/Clock SignalTests/Shaker/MODULE A/SHAKE26A-4.CSL

@@ -0,0 +1,297 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26A du DSK SHAKER26.DSK en CRTC 4
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 4
+reset
+wait 3000000 
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26A"\(RET)'
+wait 10000000
+;
+; test 1
+key_output '1'		
+wait 800000			; fin affichage 1er ecran & ssm 595215
+key_output ' ' 
+wait 800000			; fin affichage 2nd ecran & ssm 659451
+key_output ' '
+wait 800000			; fin affichage 3eme ecran & ssm 627963
+key_output ' '
+wait 800000			; fin affichage 4eme ecran & ssm 698883
+key_output ' '
+wait 800000			; fin affichage 5eme ecran & ssm 551415
+key_output ' '
+wait 1000000		; retour menu
+; 
+; test 2
+key_output '2'	
+wait 800000			; 519961 crt 0 1 ecran 
+key_output ' '  
+wait 800000			; 2 ecrans 
+wait 800000			;
+key_output ' '  
+wait 800000			; 723923
+key_output ' '
+wait 800000			; 599040
+key_output ' '
+wait 1000000		; retour menu
+;
+; test 3
+key_output '3'
+wait 800000		; 596058
+wait 1500000	; 1337856
+key_output ' ' 
+wait 800000		; 730624
+wait 1500000	; 1337856
+key_output ' ' 
+wait 800000		; 750685
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 750592
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 710656
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 726016
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 726952
+wait 800000	  ; 698880
+key_output ' ' 
+wait 1000000	; 845824
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 666112
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 666112
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 706048
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 610816
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 730624
+wait 800000	  ; 698880
+key_output ' ' 
+wait 900000		; 745984
+wait 800000	  ; 698880
+key_output ' ' 
+wait 900000		; 805888
+wait 800000	  ; 698880
+key_output ' ' 
+wait 1000000	; 865792
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 686080
+wait 800000	  ; 698880
+key_output ' ' 
+wait 800000		; 686080
+wait 800000	  ; 698880
+key_output ' ' 
+wait 10000000
+;
+key_output '4' 
+wait 12000000	; 6743019
+key_output ' ' 
+wait 1000000
+;
+key_output '5'
+wait 800000		; 434016
+key_output ' ' 
+wait 800000		; 547328
+key_output ' ' 
+wait 800000		; 567296
+key_output ' ' 
+wait 800000		; 587264
+key_output ' ' 
+wait 800000		; 607232
+key_output ' ' 
+wait 1000000
+;
+key_output '6'
+wait 800000	; 473960
+key_output ' ' 
+wait 800000	; 607232
+key_output ' ' 
+wait 800000	; 627200
+key_output ' ' 
+wait 800000	; 647168
+key_output ' ' 
+wait 800000	; 667136
+key_output ' ' 
+wait 1000000
+;
+key_output '7'
+wait 800000		; 473957
+key_output ' ' 
+wait 800000		; 667072
+key_output ' ' 
+wait 800000		; 527296
+key_output ' ' 
+wait 800000		; 547264
+key_output ' ' 
+wait 800000		; 567232
+key_output ' ' 
+wait 1000000
+;
+key_output '8'
+wait 800000		; 431083
+key_output ' ' 
+wait 1000000
+;
+key_output '9'
+wait 800000		; 474048
+key_output ' ' 
+wait 800000		; 559104
+key_output ' ' 
+wait 800000		; 598363
+key_output ' ' 
+wait 1000000
+;
+key_output 'E'
+wait 800000		; 514468
+key_output ' ' 
+wait 1000000
+;
+key_output 'R'
+wait 800000		; 592695
+wait 1200000	; 998400
+key_output ' ' 
+wait 800000		; 599040
+wait 1200000  ; 998400
+key_output ' ' 
+wait 800000		; 658944
+wait 1200000  ; 998400
+key_output ' ' 
+wait 1000000
+;
+key_output 'T'
+wait 800000		; 531832
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 579072
+key_output ' ' 
+wait 800000		; 638976
+key_output ' ' 
+wait 1000000
+;
+key_output 'Y'
+wait 800000		; 511931
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000		; 619008
+key_output ' ' 
+wait 800000	; ???
+key_output ' ' 
+wait 1000000
+;
+key_output 'U'
+wait 14000000	; 11803953+1007210
+key_output ' '
+wait 1000000
+;
+key_output 'I'
+wait 2200000	; 2013010
+key_output ' '
+wait 2200000	; 2315008
+key_output ' '
+wait 5000000	; 4233216
+key_output ' '
+wait 35000000	; 31301630
+key_output ' '
+wait 2000000	; 1557507
+key_output ' '
+wait 1000000
+;
+key_output 'O'
+wait 800000		; 576098
+key_output ' '
+wait 800000		; 698880
+key_output ' '
+wait 800000		; 698880
+key_output ' '
+wait 800000		; 599040
+key_output ' '
+wait 800000		; 497671
+key_output ' '
+wait 800000		; 469504
+key_output ' '
+wait 800000		; 522696
+key_output ' '
+wait 800000		; 547978
+key_output ' '
+wait 800000		; 579072
+; crtc 1
+;key_output ' '
+;wait 800000		; 482251
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 599552
+;key_output ' '
+;wait 800000		; 519680
+key_output ' '
+wait 1000000
+;
+key_output 'P'
+wait 450000		; 427222
+wait 5200000	; 5111808
+key_output ' '
+wait 800000		; 529408
+key_output ' '
+wait 800000		; 489472
+key_output ' '
+wait 800000		; 449536
+key_output ' '
+wait 800000		; 509440
+key_output ' '
+wait 800000		; 587307
+key_output ' '
+wait 800000		; 479104
+key_output ' '
+wait 800000		; 479360
+key_output ' '
+wait 800000		; 490944
+key_output ' '
+wait 800000		; 638464
+key_output ' '
+wait 800000		; 619008
+key_output ' '
+wait 1000000
+
+csl_load 'SHAKE26A-3'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE B/SHAKE26B-0.CSL

@@ -0,0 +1,390 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26B du DSK SHAKER26.DSK en CRTC 0
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 0
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26B"\(RET)'
+wait 10000000
+;
+; test 1 interlace c4/c9 counters R9 base=07 Parity Odd
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+key_output 'Y'	; bascule sur parity Even (R9 Base=7)
+wait 300000
+;
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+key_output 'Z'	; Passe sur R9 BASE=6 (parity Even)
+wait 300000
+;
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+;
+key_output 'Y'	; bascule sur parity Odd (R9 base=6)
+wait 300000
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+;
+; test 9 (garder la foi tu dois, mecreant)
+key_output '9'		; En Odd
+wait 20000000		; 
+key_output ' ' 
+wait 20000000
+key_output ' '
+wait 1000000
+;
+key_output 'Y'		; Repasser en Even
+wait 100000
+key_output '9'		; En even
+wait 20000000		; 
+key_output ' ' 
+wait 20000000
+key_output ' '
+wait 1000000
+;
+key_output '0' ; vertical sub pixel scroll
+wait 1000000	; 816677 1/8
+key_output ' '
+wait 1000000	; 890842 1/16
+key_output ' '
+wait 1000000	; 830950 1/32
+key_output ' '
+wait 1000000	; 870899 1/64
+key_output ' '
+wait 1000000	; 830965 1/128
+key_output ' '
+wait 1000000 ; menu
+;
+;
+key_output '4' ; 
+wait 2000000	; 1913669
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 1000000	; 
+key_output ' '
+wait 1000000	; menu
+;
+key_output '5' ; rlal crtc 2 (tous crtc)
+wait 900000
+key_output ' '
+wait 2000000
+key_output ' '	; Menu
+wait 1000000
+;
+;
+key_output '\(RET)'
+wait 800000		; 632429
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 800000		; 647344
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 800000		; 667312
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 1000000
+;
+;Test Bounga 
+key_output '\(FN0)'
+wait 30000000		; ???	
+key_output ' '
+wait 1000000
+;
+; Test RVNI LTD
+;
+key_output '\(CAP)'
+wait 6000000	; 753563	
+key_output ' '
+wait 6000000	; 727728
+key_output ' '
+wait 6000000	; 728880
+key_output ' '
+wait 6000000
+;	
+; Shaker Killer Don't be afraid
+;
+key_output 'R'	
+wait 5000000	; 2615301 z80aintb
+key_output ' '
+wait 6000000	; 4692484 r52Reset
+key_output ' '
+wait 9000000	; 7867387 Inter Test IM1
+key_output ' '
+wait 9000000	; 6888966 Inter Test IM2
+key_output ' '
+wait 3000000	; 1711766 R52 Incr
+key_output ' '
+wait 900000	; 486262 Otir Zone
+key_output ' '
+wait 1000000 ; menu 
+;
+; R3 JIT
+key_output 'I'	
+wait 1000000	; 474622
+key_output ' '	
+wait 1000000	; 519168
+key_output ' '	
+wait 1000000	; 519168
+key_output ' '	
+wait 1000000	; 499200
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 599040
+key_output ' '	
+wait 1000000	; Menu
+;
+; test crtc 0,1 only
+;
+key_output '\(COP)'
+wait 1000000	; 787700
+key_output ' '	
+wait 1000000	; 778752
+key_output ' '	
+wait 2000000	; 702326+19968
+key_output ' '	
+wait 2000000  ; 835656
+key_output ' '	
+wait 2000000  ; 924826
+key_output ' '	
+wait 4000000
+;
+;
+; test crtc 1 , ouvert aux autres CRTCs
+;
+key_output '6'
+wait 10000000	; 1676617
+key_output ' '	
+wait 1000000
+;
+; test crtc 0 only
+; 
+key_output '7'	 ; resultat a verifier
+wait 800000		; 613742
+wait 600000		; 511808
+wait 2000000	; 1277952
+wait 5000000	; 3833856
+wait 2000000	; 1277952
+wait 5000000	; 3833856
+wait 2000000	; 1277952
+key_output ' '	
+wait 800000		; 533680
+wait 6000000	; 5111808
+wait 2000000	; 1277952
+wait 6000000	; 3833856
+wait 2000000	; 1277952
+wait 6000000	; 3833856
+wait 2000000	; 1277952
+key_output ' '	
+wait 800000		; 565936
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 2000000	; 1277952
+wait 6000000	; 3833856
+wait 2000000	; 1277952
+key_output ' '
+key_output ' '	
+wait 800000		; 565936
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 2000000	; 1277952
+wait 6000000	; 3833856
+wait 2000000	; 1277952
+key_output ' '
+wait 1000000	; menu
+;
+; test crtc 0 only
+; 
+key_output 'U'	 
+wait 1200000		; 
+key_output ' '		; A
+wait 1200000		; 
+key_output ' '		; B
+wait 1200000		; 
+key_output ' '		; C
+wait 1200000		; 
+key_output ' '		; D
+wait 1200000		; 
+key_output ' '		; E
+wait 1200000		; 
+key_output ' '		; F
+wait 1200000		; 
+key_output ' '		; G
+wait 1200000		; 
+key_output ' '		; H
+wait 1200000		; 
+key_output ' '		; I
+wait 1200000		; 
+key_output ' '		; J
+wait 1200000		; 
+key_output ' '		; K
+wait 1200000		; 
+key_output ' '		; L
+wait 1200000		; 
+key_output ' '		; M
+wait 1200000		; 
+key_output ' '		; N
+wait 1200000		; 
+key_output ' '		; O
+wait 1200000		; 
+key_output ' '		; P
+wait 1200000		; 
+key_output ' '		; Q
+wait 1200000		; 
+key_output ' '		; R
+wait 1200000		; 
+key_output ' '		; S
+wait 1200000		; 
+;
+; Test Analyzer des premieres heures
+;
+key_output 'P'
+wait 100000000	; 12828735+638976
+key_output ' '
+wait 100000000	; 5440000+638976
+key_output ' '
+wait 100000000	; 11637760+638976
+key_output ' '
+wait 100000000	; 13560624+638976
+key_output ' '
+wait 1000000
+
+csl_load 'SHAKE26B-1'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE B/SHAKE26B-1.CSL

@@ -0,0 +1,278 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26B du DSK SHAKER26.DSK en CRTC 1
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 1A
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26B"\(RET)'
+wait 10000000
+;
+; test 1 interlace c4/c9 counters R9 base=07 
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+;
+key_output 'Z'	; Passe sur R9 BASE=6
+wait 300000
+;
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+;
+; test 9 (garder la foi tu dois, mecreant)
+key_output '9'	
+wait 20000000		; 
+key_output ' ' 
+wait 20000000
+key_output ' '
+wait 1000000
+;
+key_output '0' ; vertical sub pixel scroll
+wait 1000000	; 816677 1/8
+key_output ' '
+wait 1000000	; 890842 1/16
+key_output ' '
+wait 1000000	; 830950 1/32
+key_output ' '
+wait 1000000	; 870899 1/64
+key_output ' '
+wait 1000000	; 830965 1/128
+key_output ' '
+wait 1000000 ; menu
+;
+key_output '4' ; 
+wait 2000000	; 1913669
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 1000000	; 
+key_output ' '
+wait 1000000	; menu
+;
+key_output '5' ; rlal crtc 2 (tous crtc)
+wait 900000
+key_output ' '
+wait 2000000
+key_output ' '	; Menu
+wait 1000000
+;
+;
+key_output '\(RET)'
+wait 800000		; 632429
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 800000		; 647344
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 800000		; 667312
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 1000000
+;
+;Test Bounga 
+key_output '\(FN0)'
+wait 30000000		; ???	
+key_output ' '
+wait 1000000
+;
+; Test RVNI LTD
+;
+key_output '\(CAP)'
+wait 6000000	; 753563	
+key_output ' '
+wait 6000000	; 727728
+key_output ' '
+wait 6000000	; 728880
+key_output ' '
+wait 6000000
+;	
+; Shaker Killer Don't be afraid
+;
+key_output 'R'	
+wait 5000000	; 2615301 z80aintb
+key_output ' '
+wait 6000000	; 4692484 r52Reset
+key_output ' '
+wait 9000000	; 7867387 Inter Test IM1
+key_output ' '
+wait 9000000	; 6888966 Inter Test IM2
+key_output ' '
+wait 3000000	; 1711766 R52 Incr
+key_output ' '
+wait 900000	; 486262 Otir Zone
+key_output ' '
+wait 1000000 ; menu 
+;
+; R3 JIT
+key_output 'I'	
+wait 1000000	; 474622
+key_output ' '	
+wait 1000000	; 519168
+key_output ' '	
+wait 1000000	; 519168
+key_output ' '	
+wait 1000000	; 499200
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 599040
+key_output ' '	
+wait 1000000	; Menu
+;
+; test crtc 0,1 only
+;
+key_output '\(COP)'
+wait 1000000	; 787700
+key_output ' '	
+wait 1000000	; 778752
+key_output ' '	
+wait 2000000	; 702326+19968
+key_output ' '	
+wait 2000000  ; 835656
+key_output ' '	
+wait 2000000  ; 924826
+key_output ' '	
+wait 4000000
+;
+;
+; test crtc 1 , ouvert aux autres CRTCs
+;
+key_output '6'
+wait 10000000	; 1676617
+key_output ' '	
+wait 1000000
+;
+; test crtc 1 only : identification crtc 1A/1B
+; pour le 1A
+key_output 'O'
+wait 500000	; 336980
+key_output ' '	
+wait 1000000
+;
+;
+; test crtc 1 only : BE00 check
+;
+key_output 'S'
+wait 5000000	; 1976392
+key_output ' '	
+wait 1000000
+;
+;
+; Test Analyzer des premieres heures
+;
+key_output 'P'
+wait 100000000	; 12828735+638976
+key_output ' '
+wait 100000000	; 5440000+638976
+key_output ' '
+wait 100000000	; 11637760+638976
+key_output ' '
+wait 100000000	; 13560624+638976
+key_output ' '
+wait 1000000
+;
+; Test RFD
+;
+key_output '\(CTR)'
+wait 10000000
+;
+; Si la selection de crtc en cours de route pose prb sortir ce test
+;
+crtc_select 1B
+;
+; test crtc 1 only : identification crtc 1A/1B
+; pour le 1B
+key_output 'E'
+wait 500000	; 336980
+key_output ' '	
+wait 1000000
+;
+csl_load 'SHAKE26B-2'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE B/SHAKE26B-2.CSL

@@ -0,0 +1,306 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26B du DSK SHAKER26.DSK en CRTC 2
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 2
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26B"\(RET)'
+wait 10000000
+;
+; test 1 interlace c4/c9 counters R9 base=07 Parity Odd
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+key_output 'Y'	; bascule sur parity Even (R9 Base=7)
+wait 300000
+;
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+key_output 'Z'	; Passe sur R9 BASE=6 (parity Even)
+wait 300000
+;
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+;
+key_output 'Y'	; bascule sur parity Odd (R9 base=6)
+wait 300000
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+;
+; test 9 (garder la foi tu dois, mecreant)
+key_output '9'		; En Odd
+wait 20000000		; 
+key_output ' ' 
+wait 20000000
+key_output ' '
+wait 1000000
+;
+key_output 'Y'		; Repasser en Even
+wait 100000
+key_output '9'		; En even
+wait 20000000		; 
+key_output ' ' 
+wait 20000000
+key_output ' '
+wait 1000000
+;
+key_output '0' ; vertical sub pixel scroll
+wait 1000000	; 816677 1/8
+key_output ' '
+wait 1000000	; 890842 1/16
+key_output ' '
+wait 1000000	; 830950 1/32
+key_output ' '
+wait 1000000	; 870899 1/64
+key_output ' '
+wait 1000000	; 830965 1/128
+key_output ' '
+wait 1000000 ; menu
+;
+; ** crtc 2 only   Even mode 1 ecran
+key_output '2' ; 
+wait 3000000	; 1245718
+key_output ' ' ; 
+wait 1000000 ; menu
+key_output 'Y'		; repasser en Odd
+key_output '2'
+wait 3000000	; 1245718
+key_output ' ' ; 
+wait 3000000	; 1245718 2 ecrans
+;
+key_output '4' ; 
+wait 2000000	; 1913669
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 1000000	; 
+key_output ' '
+wait 1000000	; menu
+;
+key_output '5' ; rlal crtc 2 (tous crtc)
+wait 900000
+key_output ' '
+wait 2000000
+key_output ' '	; Menu
+wait 1000000
+;
+;
+key_output '\(RET)'
+wait 800000		; 632429
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 800000		; 647344
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 800000		; 667312
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 1000000
+;
+;Test Bounga 
+key_output '\(FN0)'
+wait 30000000		; ???	
+key_output ' '
+wait 1000000
+;
+; Test RVNI LTD
+;
+key_output '\(CAP)'
+wait 6000000	; 753563	
+key_output ' '
+wait 6000000	; 727728
+key_output ' '
+wait 6000000	; 728880
+key_output ' '
+wait 6000000
+;	
+; Shaker Killer Don't be afraid
+;
+key_output 'R'	
+wait 5000000	; 2615301 z80aintb
+key_output ' '
+wait 6000000	; 4692484 r52Reset
+key_output ' '
+wait 9000000	; 7867387 Inter Test IM1
+key_output ' '
+wait 9000000	; 6888966 Inter Test IM2
+key_output ' '
+wait 3000000	; 1711766 R52 Incr
+key_output ' '
+wait 900000	; 486262 Otir Zone
+key_output ' '
+wait 1000000 ; menu 
+;
+; R3 JIT
+key_output 'I'	
+wait 1000000	; 474622
+key_output ' '	
+wait 1000000	; 519168
+key_output ' '	
+wait 1000000	; 519168
+key_output ' '	
+wait 1000000	; 499200
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 599040
+key_output ' '	
+wait 1000000	; Menu
+;
+; test crtc 1 , ouvert aux autres CRTCs
+;
+key_output '6'
+wait 20000000	; 1676617
+key_output ' '	
+wait 1000000
+;
+;
+; Test Analyzer des premieres heures
+;
+key_output 'P'
+wait 100000000	; 12828735+638976
+key_output ' '
+wait 100000000	; 5440000+638976
+key_output ' '
+wait 100000000	; 11637760+638976
+key_output ' '
+wait 100000000	; 13560624+638976
+key_output ' '
+wait 1000000
+
+csl_load 'SHAKE26B-4'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE B/SHAKE26B-3.CSL

@@ -0,0 +1,242 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26B du DSK SHAKER26.DSK en CRTC 3
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 3
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26B"\(RET)'
+wait 10000000
+;
+; test 1 interlace c4/c9 counters R9 base=07 
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+;
+key_output 'Z'	; Passe sur R9 BASE=6
+wait 300000
+;
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+;
+; test 9 (garder la foi tu dois, mecreant)
+key_output '9'	
+wait 20000000		; 
+key_output ' ' 
+wait 20000000
+key_output ' '
+wait 1000000
+;
+key_output 'Y'		; Repasser en Even
+wait 100000
+key_output '9'		; En even
+wait 20000000		; 
+key_output ' ' 
+wait 20000000
+key_output ' '
+wait 1000000
+;
+key_output '0' ; vertical sub pixel scroll
+wait 1000000	; 816677 1/8
+key_output ' '
+wait 1000000	; 890842 1/16
+key_output ' '
+wait 1000000	; 830950 1/32
+key_output ' '
+wait 1000000	; 870899 1/64
+key_output ' '
+wait 1000000	; 830965 1/128
+key_output ' '
+wait 1000000 ; menu
+;
+key_output '4' ; 
+wait 2000000	; 1913669
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 1000000	; 
+key_output ' '
+wait 1000000	; menu
+;
+key_output '5' ; rlal crtc 2 (tous crtc)
+wait 900000
+key_output ' '
+wait 2000000
+key_output ' '	; Menu
+wait 1000000
+;
+;
+key_output '\(RET)'
+wait 800000		; 632429
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 800000		; 647344
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 800000		; 667312
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 1000000
+;
+;Test Bounga 
+key_output '\(FN0)'
+wait 30000000		; ???	
+key_output ' '
+wait 1000000
+;
+; Test RVNI LTD
+;
+key_output '\(CAP)'
+wait 6000000	; 753563	
+key_output ' '
+wait 6000000	; 727728
+key_output ' '
+wait 6000000	; 728880
+key_output ' '
+wait 6000000
+;	
+; Shaker Killer Don't be afraid
+;
+key_output 'R'	
+wait 5000000	; 2615301 z80aintb
+key_output ' '
+wait 6000000	; 4692484 r52Reset
+key_output ' '
+wait 9000000	; 7867387 Inter Test IM1
+key_output ' '
+wait 9000000	; 6888966 Inter Test IM2
+key_output ' '
+wait 3000000	; 1711766 R52 Incr
+key_output ' '
+wait 900000	; 486262 Otir Zone
+key_output ' '
+wait 1000000 ; menu 
+;
+; R3 JIT
+key_output 'I'	
+wait 1000000	; 474622
+key_output ' '	
+wait 1000000	; 519168
+key_output ' '	
+wait 1000000	; 519168
+key_output ' '	
+wait 1000000	; 499200
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 599040
+key_output ' '	
+wait 1000000	; Menu
+;
+;
+; test crtc 1 , ouvert aux autres CRTCs
+;
+key_output '6'
+wait 2000000	; 1676617
+key_output ' '	
+wait 1000000
+
+;
+; Test Analyzer des premieres heures
+;
+key_output 'P'
+wait 100000000	; 12828735+638976
+key_output ' '
+wait 100000000	; 5440000+638976
+key_output ' '
+wait 100000000	; 11637760+638976
+key_output ' '
+wait 100000000	; 13560624+638976
+key_output ' '
+wait 1000000
+;
+reset
+;

OSBindings/Mac/Clock SignalTests/Shaker/MODULE B/SHAKE26B-4.CSL

@@ -0,0 +1,241 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26B du DSK SHAKER26.DSK en CRTC 4
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 4
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26B"\(RET)'
+wait 10000000
+;
+; test 1 interlace c4/c9 counters R9 base=06
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+;
+key_output 'X'	; Passe sur R9 BASE=7
+wait 300000
+;
+key_output '1'
+wait 5000000		; Ecran settings, ecran intermediaire
+wait 7000000		; 1er ecran
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000	; 5251584
+key_output ' ' 
+wait 7000000		; menu
+;
+; test 9 (garder la foi tu dois, mecreant)
+key_output '9'	
+wait 20000000		; 
+key_output ' ' 
+wait 20000000
+key_output ' '
+wait 1000000
+;
+key_output 'Y'		; Repasser en Even
+wait 100000
+key_output '9'		; En even
+wait 20000000		; 
+key_output ' ' 
+wait 20000000
+key_output ' '
+wait 1000000
+;
+key_output '0' ; vertical sub pixel scroll
+wait 1000000	; 816677 1/8
+key_output ' '
+wait 1000000	; 890842 1/16
+key_output ' '
+wait 1000000	; 830950 1/32
+key_output ' '
+wait 1000000	; 870899 1/64
+key_output ' '
+wait 1000000	; 830965 1/128
+key_output ' '
+wait 1000000 ; menu
+;
+key_output '4' ; 
+wait 2000000	; 1913669
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 900000		; 730624
+key_output ' '
+wait 1000000	; 
+key_output ' '
+wait 1000000	; menu
+;
+key_output '5' ; rlal crtc 2 (tous crtc)
+wait 900000
+key_output ' '
+wait 2000000
+key_output ' '	; Menu
+wait 1000000
+;
+;
+key_output '\(RET)'
+wait 800000		; 632429
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 800000		; 647344
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 800000		; 667312
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+wait 6000000	; 5111808
+key_output ' '
+wait 1000000
+;
+;Test Bounga 
+key_output '\(FN0)'
+wait 50000000		; ???	
+key_output ' '
+wait 1000000
+;
+; Test RVNI LTD
+;
+key_output '\(CAP)'
+wait 6000000	; 753563	
+key_output ' '
+wait 6000000	; 727728
+key_output ' '
+wait 6000000	; 728880
+key_output ' '
+wait 6000000
+;	
+; Shaker Killer Don't be afraid
+;
+key_output 'R'	
+wait 5000000	; 2615301 z80aintb
+key_output ' '
+wait 6000000	; 4692484 r52Reset
+key_output ' '
+wait 9000000	; 7867387 Inter Test IM1
+key_output ' '
+wait 9000000	; 6888966 Inter Test IM2
+key_output ' '
+wait 3000000	; 1711766 R52 Incr
+key_output ' '
+wait 900000	; 486262 Otir Zone
+key_output ' '
+wait 1000000 ; menu 
+;
+; R3 JIT
+key_output 'I'	
+wait 1000000	; 474622
+key_output ' '	
+wait 1000000	; 519168
+key_output ' '	
+wait 1000000	; 519168
+key_output ' '	
+wait 1000000	; 499200
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 619008
+key_output ' '	
+wait 1000000	; 599040
+key_output ' '	
+wait 1000000	; Menu
+;
+;
+; test crtc 1 , ouvert aux autres CRTCs
+;
+key_output '6'
+wait 12000000	; 1676617
+key_output ' '	
+wait 1000000
+
+;
+; Test Analyzer des premieres heures
+;
+key_output 'P'
+wait 100000000	; 12828735+638976
+key_output ' '
+wait 100000000	; 5440000+638976
+key_output ' '
+wait 100000000	; 11637760+638976
+key_output ' '
+wait 100000000	; 13560624+638976
+key_output ' '
+wait 1000000
+;
+csl_load 'SHAKE26B-3'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE C/SHAKE26C-0.CSL

@@ -0,0 +1,96 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26C du DSK SHAKER26.DSK en CRTC 0
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 0
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26C"\(RET)'
+wait 10000000
+;
+; test 5 Parity Check Select CRTC 0, 2
+key_output '5'
+wait 10000000		
+key_output ' ' 
+wait 1000000 ; menu
+
+; test prevu pour CRTC 2 mais disp autre crc  Last Line cond
+key_output '7'
+wait 64000000
+key_output ' ' 
+wait 1000000 ; menu
+
+; test crtc 2 vma' sur R1=0
+key_output 'T'
+wait 1100000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1000000 ; menu
+
+; crtc 2 ghost vsync vs Last Line (others crtc welcome)
+key_output '\(RET)'
+wait 5000000
+key_output ' '
+wait 2000000
+key_output ' '
+wait 1000000 ; menu
+
+; Add Line R5 on last line
+key_output 'E'
+wait 10000000
+key_output ' '
+wait 5000000
+key_output ' '
+wait 1000000 ; menu
+
+; Add line R8
+key_output 'P'
+wait 12000000
+key_output ' '
+wait 1000000 ; menu
+
+; r5 additional line in interlace mode
+key_output 'S'
+wait 2000000
+key_output ' '
+wait 1000000 ; menu
+
+; CRTC 0,3,4 Interlace vsync nightmare (2 1er test uniqu CRTC1)
+key_output 'O'
+wait 4000000
+key_output ' '
+wait 6000000
+key_output ' '
+wait 1000000
+wait 8000000
+key_output ' '
+wait 9000000
+key_output ' '
+wait 9000000
+key_output ' '
+wait 10000000
+key_output ' '
+wait 9000000
+key_output ' '
+wait 10000000
+key_output ' '
+wait 10000000
+key_output ' '
+wait 1000000 ; menu
+
+; R9/R4 UPD LAST LIMIT
+key_output 'R'
+wait 5000000
+key_output ' '
+wait 10000000	; menu
+
+csl_load 'SHAKE26C-1'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE C/SHAKE26C-1.CSL

@@ -0,0 +1,187 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26C du DSK SHAKER26.DSK en CRTC 1
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 1
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26C"\(RET)'
+wait 10000000
+;
+; R8 IVM ODD C9
+key_output '2'
+wait 1000000
+key_output ' '
+wait 1000000
+key_output ' '
+wait 1000000
+key_output ' '
+wait 1000000
+key_output ' '
+wait 1000000
+key_output ' '
+wait 1000000
+key_output ' '
+wait 1000000
+key_output ' '
+wait 1000000
+key_output ' '
+wait 1000000
+key_output ' '
+wait 1000000 ; menu
+
+; Parity Switch Status
+key_output '3'
+wait 5000000
+key_output ' '
+wait 1000000 ; menu
+
+; Ivm On/Off
+key_output '4'
+wait 800000			; 23D
+key_output ' '
+wait 1000000		; 23E
+key_output ' '
+wait 1000000	  ; 23F
+key_output ' '
+wait 1000000		; 27F
+key_output ' '
+wait 1000000		; 280
+key_output ' '
+wait 1000000		; 281
+key_output ' '    
+wait 1000000		; 282
+key_output ' '
+wait 1000000		; 283
+key_output ' '
+wait 1000000		; 284
+key_output ' '
+wait 1000000		; 285, 286
+key_output ' '
+wait 1000000		; 287, 288
+key_output ' '
+wait 1000000		; 289
+key_output ' '
+wait 1000000		; 28A
+key_output ' '
+wait 1000000		; 28B
+key_output ' '
+wait 1000000		; 28c
+key_output ' '
+wait 1000000		; 28d
+key_output ' '
+wait 1000000		; 28e
+key_output ' '
+wait 1000000		; 28f
+key_output ' '
+wait 1000000		; 290
+key_output ' '
+wait 1000000		; 291
+key_output ' '
+wait 1000000		; 292
+key_output ' '
+wait 1000000		; 293
+key_output ' '
+wait 1000000		; 294
+key_output ' '
+wait 1000000		; 295
+key_output ' '
+wait 1000000		; 296, 297
+key_output ' '
+wait 1000000		; 298, 299
+key_output ' '
+wait 1000000		; 29a
+key_output ' '
+wait 1000000		; 29b
+key_output ' '
+wait 1000000		; 29c
+key_output ' '
+wait 1000000		; 29d
+key_output ' '
+
+; test prevu pour CRTC 2 mais disp autre crc  Last Line cond
+key_output '7'
+wait 64000000
+key_output ' '
+wait 1000000 ; menu 
+
+; test crtc 2 vma' sur R1=0
+key_output 'T'
+wait 1100000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1000000 ; menu
+
+; crtc 2 ghost vsync vs Last Line (others crtc welcome)
+key_output '\(RET)'
+wait 5000000
+key_output ' '
+wait 2000000
+key_output ' '
+wait 1000000 ; menu
+
+; Add Line R5 on last line
+key_output 'E'
+wait 20000000
+key_output ' '
+wait 10000000
+key_output ' '
+wait 1000000 ; menu
+
+; Add line R8
+key_output 'P'
+wait 20000000
+key_output ' '
+wait 1000000 ; menu
+
+; r5 additional line in interlace mode
+key_output 'S'
+wait 4000000
+key_output ' '
+wait 1000000 ; menu
+
+; CRTC 1 Interlace vsync nightmare (2 1er test uniqu CRTC1)
+key_output 'O'
+wait 12000000  ; cvsct1_a
+key_output ' '
+wait 6000000  ; cvsct1_b
+key_output ' '
+wait 3500000	; cvstot
+key_output ' '
+wait 2000000	; parity00
+wait 8000000
+key_output ' '
+wait 6000000	; cvms_a
+key_output ' '
+wait 6000000	; cvms_b
+key_output ' '
+wait 6000000	; cvms_b
+key_output ' '
+wait 6000000	; cvms_c
+key_output ' '
+wait 6000000	; cvms_c
+key_output ' '
+wait 3000000		; parity01a
+key_output ' '
+wait 3000000		; parity01b
+key_output ' '
+wait 3000000		; parity01c
+key_output ' '
+wait 3000000		; parity01d
+key_output ' '
+wait 3000000		; parity01e
+key_output ' '
+wait 3000000		; parity01f
+key_output ' '
+wait 1000000
+
+csl_load 'SHAKE26C-2'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE C/SHAKE26C-2.CSL

@@ -0,0 +1,154 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26C du DSK SHAKER26.DSK en CRTC 2
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 2
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26C"\(RET)'
+wait 10000000
+;
+; test 5 Parity Check Select CRTC 0, 2
+key_output '5'
+wait 10000000		
+key_output ' '
+wait 1000000 ; menu  
+
+; C9 IVM Switch
+key_output '6'
+wait 1200000		; 29f
+key_output ' '
+wait 1200000		; 2a4
+key_output ' '
+wait 1200000		; 2a5
+key_output ' '
+wait 1200000		; 2a6
+key_output ' '
+wait 1200000		; 2a7
+key_output ' '
+wait 1200000		; 2ac
+key_output ' '
+wait 1200000		; 2ad
+key_output ' '
+wait 1200000		; 2ae
+key_output ' '
+wait 1200000		; 2af
+key_output ' '
+wait 1200000		; 2b4
+key_output ' '
+wait 1200000		; 2b5
+key_output ' '
+wait 1200000		; 2b6
+key_output ' '
+wait 1200000		; 2b7
+key_output ' '
+wait 1200000		; 2bc
+key_output ' '
+wait 1200000		; 2bd
+key_output ' '
+wait 1200000		; 2be
+key_output ' ' 
+wait 1000000 ; menu 
+
+
+; test prevu pour CRTC 2 mais disp autre crc  Last Line cond
+key_output '7'
+wait 64000000
+key_output ' ' 
+wait 1000000 ; menu 
+;
+; add line on parity bug
+key_output '8'
+wait 2000000		; 2c0
+key_output ' '
+wait 2000000		; 2c1
+key_output ' '
+wait 2000000		; 2c2
+key_output ' '
+wait 2000000		; 2c3
+key_output ' '
+wait 2000000		; 2c4
+key_output ' '
+wait 2000000		; 2c5
+key_output ' '
+wait 2000000		; 2c6
+key_output ' '
+wait 1000000 ; menu 
+
+; add line rq & trigger
+key_output '9'
+wait 2000000		; 2c7
+key_output ' '
+wait 300000000
+key_output ' '
+
+; test crtc 2 vma' sur R1=0
+key_output 'T'
+wait 1100000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1000000 ; menu
+
+; crtc 2 ghost vsync vs Last Line (others crtc welcome)
+key_output '\(RET)'
+wait 5000000
+key_output ' '
+wait 2000000
+key_output ' '
+wait 1000000 ; menu
+
+; Add Line R5 on last line
+key_output 'E'
+wait 20000000
+key_output ' '
+wait 10000000
+key_output ' '
+wait 1000000 ; menu
+
+; Add line R8
+key_output 'P'
+wait 20000000
+key_output ' '
+wait 1000000 ; menu
+
+; r5 additional line in interlace mode
+key_output 'S'
+wait 2000000
+key_output ' '
+wait 1000000 ; menu
+
+; CRTC 2 Interlace vsync nightmare (2 1er test uniqu CRTC1)
+key_output 'O'
+wait 6000000	; cvstot
+key_output ' '
+wait 2000000	; parity00 2d8
+wait 8000000	; 2d9
+key_output ' '
+wait 10000000	; cvms_a	; 2da
+key_output ' '
+wait 10000000	; cvms_b  ; 2db
+key_output ' '
+wait 10000000	; cvms_b  ; 2dc
+key_output ' '
+wait 10000000	; cvms_c  ; 2dd
+key_output ' '
+wait 10000000	; cvms_c  ; 2de
+key_output ' '
+wait 10000000	; menu
+
+; R9/R4 UPD LAST LIMIT
+key_output 'R'
+wait 5000000		; 3ad
+key_output ' '
+wait 10000000	; menu
+
+csl_load 'SHAKE26C-4'	; corrected from cls_load

OSBindings/Mac/Clock SignalTests/Shaker/MODULE C/SHAKE26C-3.CSL

@@ -0,0 +1,94 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26C du DSK SHAKER26.DSK en CRTC 3
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 3
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26C"\(RET)'
+wait 10000000
+
+; test prevu pour CRTC 2 mais disp autre crc  Last Line cond
+key_output '7'
+wait 64000000
+key_output ' ' 
+wait 1000000 ; menu 
+;
+; test crtc 2 vma' sur R1=0
+key_output 'T'
+wait 1100000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1000000 ; menu
+
+; crtc 2 ghost vsync vs Last Line (others crtc welcome)
+key_output '\(RET)'
+wait 5000000		; 2cd
+key_output ' '
+wait 2000000		; 2ce
+key_output ' '
+wait 1000000 ; menu
+
+; Add Line R5 on last line
+key_output 'E'
+wait 10000000	; 2c9
+key_output ' '
+wait 5000000	; 2ca
+key_output ' '
+wait 1000000 ; menu
+
+; r5 additional line in interlace mode
+key_output 'S'
+wait 2000000		; 2d3
+key_output ' '
+wait 1000000 ; menu
+
+; CRTC 2 Interlace vsync nightmare (2 1er test uniqu CRTC1)
+key_output 'O'
+wait 6000000	; cvstot 2d6
+key_output ' '
+wait 3500000	; cvstot 2d7
+key_output ' '
+wait 2000000	; parity00
+wait 8000000
+key_output ' '
+wait 10000000	; cvms_a 2d8
+key_output ' '
+wait 10000000	; cvms_b
+key_output ' '
+wait 10000000	; cvms_b
+key_output ' '
+wait 10000000	; cvms_c
+key_output ' '
+wait 10000000	; cvms_c
+key_output ' '
+wait 10000000	; menu
+
+; Y crtc 3/4 parity
+key_output 'Y'
+wait 4500000	; 2df
+key_output ' '
+wait 1000000	; 2e0
+key_output ' '
+wait 1000000	; 2e1
+key_output ' '
+wait 1000000	; 2e2
+key_output ' '
+wait 10000000	; menu
+
+; R9/R4 UPD LAST LIMIT
+key_output 'R'
+wait 5000000
+key_output ' '
+wait 10000000	; menu
+
+reset

OSBindings/Mac/Clock SignalTests/Shaker/MODULE C/SHAKE26C-4.CSL

@@ -0,0 +1,94 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26C du DSK SHAKER26.DSK en CRTC 4
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 4
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26C"\(RET)'
+wait 10000000
+
+; test prevu pour CRTC 2 mais disp autre crc  Last Line cond
+key_output '7'
+wait 64000000
+key_output ' ' 
+wait 1000000 ; menu 
+;
+; test crtc 2 vma' sur R1=0
+key_output 'T'
+wait 1100000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1200000
+key_output ' ' 
+wait 1000000 ; menu
+
+; crtc 2 ghost vsync vs Last Line (others crtc welcome)
+key_output '\(RET)'
+wait 5000000		; 2cd
+key_output ' '
+wait 2000000		; 2ce
+key_output ' '
+wait 1000000 ; menu
+
+; Add Line R5 on last line
+key_output 'E'
+wait 10000000	; 2c9
+key_output ' '
+wait 5000000	; 2ca
+key_output ' '
+wait 1000000 ; menu
+
+; r5 additional line in interlace mode
+key_output 'S'
+wait 2000000		; 2d3
+key_output ' '
+wait 1000000 ; menu
+
+; CRTC 2 Interlace vsync nightmare (2 1er test uniqu CRTC1)
+key_output 'O'
+wait 6000000	; cvstot 2d6
+key_output ' '
+wait 3500000	; cvstot 2d7
+key_output ' '
+wait 2000000	; parity00
+wait 8000000
+key_output ' '
+wait 10000000	; cvms_a 2d8
+key_output ' '
+wait 10000000	; cvms_b
+key_output ' '
+wait 10000000	; cvms_b
+key_output ' '
+wait 10000000	; cvms_c
+key_output ' '
+wait 10000000	; cvms_c
+key_output ' '
+wait 10000000	; menu
+
+; Y crtc 3/4 parity
+key_output 'Y'
+wait 4500000	; 2df
+key_output ' '
+wait 1000000	; 2e0
+key_output ' '
+wait 1000000	; 2e1
+key_output ' '
+wait 1000000	; 2e2
+key_output ' '
+wait 10000000	; menu
+
+; R9/R4 UPD LAST LIMIT
+key_output 'R'
+wait 5000000
+key_output ' '
+wait 10000000	; menu
+
+csl_load 'SHAKE26C-3'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE D/SHAKE26D-0.CSL

@@ -0,0 +1,201 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26D du DSK SHAKER26.DSK en CRTC 0
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 0
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26D"\(RET)'
+wait 10000000
+;
+; SHAKER KILLER 2 
+key_output 'I'
+wait 2000000		; 2e3 ecran bleu
+key_output ' ' 
+wait 2000000		; 2e4
+key_output ' ' 
+wait 2000000		; 2e5
+key_output ' ' 
+wait 2000000		; 2e6
+key_output ' ' 
+wait 2000000		; 2e7
+key_output ' ' 
+wait 2000000		; 2e8
+key_output ' '
+wait 2000000		; 2e9
+key_output ' '
+wait 1000000 ; menu
+
+; VSYNC TORTURE (LOCK MECHANISM)
+; Eventuellement ajouter des SS sur les 3 tests desync crtc 0
+key_output 'R'
+wait 22000000		; 2ea
+key_output ' '
+wait 1000000 ; menu
+
+; VSYNC/CSYNC GATE ARRAY
+key_output 'T'
+wait 800000		; 2eb
+key_output ' '
+wait 2000000	; 2ec
+key_output ' '
+wait 2000000	; 2ed
+key_output ' '
+wait 2000000	; 2ee
+key_output ' '
+wait 2000000	; 2ef
+key_output ' '
+wait 2000000	; 2ef
+key_output ' '
+wait 2000000	; 2f0
+key_output ' '
+wait 2000000	; 2f1
+key_output ' '
+wait 2000000	; 2f2
+key_output ' '
+wait 2000000	; 2f3
+key_output ' '
+wait 2000000	; 2f4
+key_output ' '
+wait 2000000	; 2f5
+key_output ' '
+wait 2000000	; 2fb
+key_output ' '
+wait 8000000	; 2fc 2fd
+key_output ' '
+wait 4000000	; 2fe
+key_output ' '
+wait 4000000	; 2ff
+key_output ' '
+wait 4000000	; 300
+key_output ' '
+wait 4000000	; 301
+key_output ' '
+wait 1000000
+key_delay 90000
+key_output '                                                '
+key_output '                                                '
+wait 1000000 ; menu
+
+
+; HSYNC CSYNC GATE ARRAY
+key_output 'H'
+wait 1000000		; 306
+key_output ' '
+wait 1200000		; 307
+key_output ' '
+wait 1200000		; 308
+key_output ' '
+wait 1200000		; 309
+key_output ' '
+wait 1200000		; 30A
+key_output ' '
+wait 1200000		; 30B
+key_output ' '
+wait 1200000		; 30C
+key_output ' '
+wait 1200000		; 30D
+key_output ' '
+wait 1200000		; 30E
+key_output ' '
+wait 1200000		; 30F
+key_output ' '
+wait 1000000 ; menu
+
+; CSYNC4 VS 2XCSYNC2
+;
+key_output '1'
+wait 4600000 ; 310
+wait 4000000 ; 311
+wait 8000000
+key_output ' '
+wait 1000000 ; menu
+
+; R2JIT >> NO CSYNC UPD
+;
+key_output '2'
+wait 4500000		; 312
+wait 4000000		; 313
+wait 4000000
+key_output ' '
+wait 10000000
+key_output ' '
+wait 1000000
+
+; 2 CSYNC RELATIVE; 
+key_output '3'
+wait 1000000  
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+
+; CSYNC MULTIPLES
+key_output '4'
+wait 1000000		; 37f
+key_output ' '
+wait 3000000	; 380
+key_output ' '
+wait 1000000
+
+; Hardware scroll 1 pixel mode 1/0 (no buffering)
+key_output '6'
+wait 10000000	; 381
+key_output ' '
+wait 10000000	; 382
+key_output ' '
+wait 1000000
+
+;
+; R2 oscillation story;
+key_output '7'
+wait 10000000	; 383
+key_output ' '
+wait 4000000	; 384
+key_output ' '
+wait 4000000	; 385
+key_output ' '
+wait 4000000	; 386
+key_output ' '
+wait 4000000	; 387
+key_output ' '
+wait 4000000	; 388
+key_output ' '
+wait 4000000	; 389
+key_output ' '
+wait 4000000	; 38a
+key_output ' '
+wait 4000000	; 38b
+key_output ' '
+wait 4000000	; 38c
+key_output ' '
+wait 1000000		; menu
+;
+; no hsync for xx line
+key_output '8'
+wait 3000000		; 38d
+key_output ' '
+wait 3000000		; 38e
+key_output ' '
+wait 3000000		; 38f
+key_output ' '
+wait 3000000		; 390
+key_output ' '
+wait 3000000		; 391
+key_output ' '
+wait 3000000		; 392
+key_output ' '
+wait 1000000		; menu
+
+
+csl_load 'SHAKE26D-1'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE D/SHAKE26D-1.CSL

@@ -0,0 +1,238 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26D du DSK SHAKER26.DSK en CRTC 1
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 1
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26D"\(RET)'
+wait 10000000
+;
+; SHAKER KILLER 2 
+key_output 'I'
+wait 2000000		; 2e3 ecran bleu
+key_output ' ' 
+wait 2000000		; 2e4
+key_output ' ' 
+wait 2000000		; 2e5
+key_output ' ' 
+wait 2000000		; 2e6
+key_output ' ' 
+wait 2000000		; 2e7
+key_output ' ' 
+wait 2000000		; 2e8
+key_output ' '
+wait 2000000		; 2e9
+key_output ' '
+wait 1000000 ; menu
+
+; VSYNC TORTURE (LOCK MECHANISM)
+; Eventuellement ajouter des SS sur les 3 tests desync crtc 0
+key_output 'R'
+wait 22000000		; 2ea
+key_output ' '
+wait 1000000 ; menu
+
+; VSYNC/CSYNC GATE ARRAY
+key_output 'T'
+wait 800000		; 2eb
+key_output ' '
+wait 2000000	; 2ec
+key_output ' '
+wait 2000000	; 2ed
+key_output ' '
+wait 2000000	; 2ee
+key_output ' '
+wait 2000000	; 2ef
+key_output ' '
+wait 2000000	; 2ef
+key_output ' '
+wait 2000000	; 2f0
+key_output ' '
+wait 2000000	; 2f1
+key_output ' '
+wait 2000000	; 2f2
+key_output ' '
+wait 2000000	; 2f3
+key_output ' '
+wait 2000000	; 2f4
+key_output ' '
+wait 2000000	; 2f5
+key_output ' '
+wait 2000000	; 2fb
+key_output ' '
+wait 8000000	; 2fc 2fd
+key_output ' '
+wait 4000000	; 2fe
+key_output ' '
+wait 4000000	; 2ff
+key_output ' '
+wait 4000000	; 300
+key_output ' '
+wait 4000000	; 301
+key_output ' '
+wait 1000000
+key_delay 90000
+key_output '                                                '
+key_output '                                                '
+wait 1000000 ; menu
+
+; HSYNC CSYNC GATE ARRAY
+key_output 'H'
+wait 1000000		; 306
+key_output ' '
+wait 1200000		; 307
+key_output ' '
+wait 1200000		; 308
+key_output ' '
+wait 1200000		; 309
+key_output ' '
+wait 1200000		; 30A
+key_output ' '
+wait 1200000		; 30B
+key_output ' '
+wait 1200000		; 30C
+key_output ' '
+wait 1200000		; 30D
+key_output ' '
+wait 1200000		; 30E
+key_output ' '
+wait 1200000		; 30F
+key_output ' '
+wait 1000000 ; menu
+
+; CSYNC4 VS 2XCSYNC2
+;
+key_output '1'
+wait 4600000 ; 310
+wait 4000000 ; 311
+wait 8000000
+key_output ' '
+wait 1000000 ; menu
+
+; R2JIT >> NO CSYNC UPD
+;
+key_output '2'
+wait 4500000		; 312
+wait 4000000		; 313
+wait 4000000
+key_output ' '
+wait 10000000
+key_output ' '
+wait 1000000
+
+; 2 CSYNC RELATIVE; 
+key_output '3'
+wait 1000000  
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+
+; CSYNC MULTIPLES
+key_output '4'
+wait 1000000		; 37f
+key_output ' '
+wait 3000000	; 380
+key_output ' '
+wait 1000000
+
+; Hardware scroll 1 pixel mode 1/0 (no buffering)
+key_output '6'
+wait 10000000	; 381
+key_output ' '
+wait 10000000	; 382
+key_output ' '
+wait 1000000
+
+;
+; R2 oscillation story;
+key_output '7'
+wait 10000000	; 383
+key_output ' '
+wait 4000000	; 384
+key_output ' '
+wait 4000000	; 385
+key_output ' '
+wait 4000000	; 386
+key_output ' '
+wait 4000000	; 387
+key_output ' '
+wait 4000000	; 388
+key_output ' '
+wait 4000000	; 389
+key_output ' '
+wait 4000000	; 38a
+key_output ' '
+wait 4000000	; 38b
+key_output ' '
+wait 4000000	; 38c
+key_output ' '
+wait 1000000		; menu
+;
+; no hsync for xx line
+key_output '8'
+wait 3000000		; 38d
+key_output ' '
+wait 3000000		; 38e
+key_output ' '
+wait 3000000		; 38f
+key_output ' '
+wait 3000000		; 390
+key_output ' '
+wait 3000000		; 391
+key_output ' '
+wait 3000000		; 392
+key_output ' '
+
+; rfd round 2
+;
+key_output '9'
+wait 2000000	; 393, 3f7
+key_output ' '
+wait 2000000	; 394, 3f8
+key_output ' '
+wait 2000000	; 395, 3f9
+key_output ' '
+wait 2000000	; 396
+key_output ' '
+wait 2000000	; 397
+key_output ' '
+wait 2000000	; 398
+key_output ' '
+wait 2000000	; 399
+key_output ' '
+wait 2000000	; 39a
+key_output ' '
+wait 2000000	; 39b
+key_output ' '
+wait 1000000  ; menu
+
+; ofs upd in add managment
+;
+key_output 'E'
+wait 1000000	; 3ae
+key_output ' '
+wait 1000000	; 3af
+key_output ' '
+wait 1000000	; 3b4
+key_output ' '
+wait 1000000	; 3b5
+key_output ' '
+wait 1000000	; 3b6
+key_output ' '
+wait 1000000	; 3b7
+key_output ' '
+wait 1000000  ; menu
+
+csl_load 'SHAKE26D-2'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE D/SHAKE26D-2.CSL

@@ -0,0 +1,199 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26D du DSK SHAKER26.DSK en CRTC 2
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 2
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26D"\(RET)'
+wait 10000000
+;
+; SHAKER KILLER 2 
+key_output 'I'
+wait 2000000		; 2e3 ecran bleu
+key_output ' ' 
+wait 2000000		; 2e4
+key_output ' ' 
+wait 2000000		; 2e5
+key_output ' ' 
+wait 2000000		; 2e6
+key_output ' ' 
+wait 2000000		; 2e7
+key_output ' ' 
+wait 2000000		; 2e8
+key_output ' '
+wait 2000000		; 2e9
+key_output ' '
+wait 1000000 ; menu
+
+; VSYNC TORTURE (LOCK MECHANISM)
+; Eventuellement ajouter des SS sur les 3 tests desync crtc 0
+key_output 'R'
+wait 22000000		; 2ea
+key_output ' '
+wait 1000000 ; menu
+
+; VSYNC/CSYNC GATE ARRAY
+key_output 'T'
+wait 800000		; 2eb
+key_output ' '
+wait 2000000	; 2ec
+key_output ' '
+wait 2000000	; 2ed
+key_output ' '
+wait 2000000	; 2ee
+key_output ' '
+wait 2000000	; 2ef
+key_output ' '
+wait 2000000	; 2ef
+key_output ' '
+wait 2000000	; 2f0
+key_output ' '
+wait 2000000	; 2f1
+key_output ' '
+wait 2000000	; 2f2
+key_output ' '
+wait 2000000	; 2f3
+key_output ' '
+wait 2000000	; 2f4
+key_output ' '
+wait 2000000	; 2f5
+key_output ' '
+wait 2000000	; 2fb
+key_output ' '
+wait 8000000	; 2fc 2fd
+key_output ' '
+wait 4000000	; 2fe
+key_output ' '
+wait 4000000	; 2ff
+key_output ' '
+wait 4000000	; 300
+key_output ' '
+wait 4000000	; 301
+key_output ' '
+wait 1000000
+key_delay 90000
+key_output '                                                '
+key_output '                                                '
+wait 1000000 ; menu
+
+; HSYNC CSYNC GATE ARRAY
+key_output 'H'
+wait 1000000		; 306
+key_output ' '
+wait 1200000		; 307
+key_output ' '
+wait 1200000		; 308
+key_output ' '
+wait 1200000		; 309
+key_output ' '
+wait 1200000		; 30A
+key_output ' '
+wait 1200000		; 30B
+key_output ' '
+wait 1200000		; 30C
+key_output ' '
+wait 1200000		; 30D
+key_output ' '
+wait 1200000		; 30E
+key_output ' '
+wait 1200000		; 30F
+key_output ' '
+wait 1000000 ; menu
+
+; CSYNC4 VS 2XCSYNC2
+;
+key_output '1'
+wait 4600000 ; 310
+wait 4000000 ; 311
+wait 8000000
+key_output ' '
+wait 1000000 ; menu
+
+; R2JIT >> NO CSYNC UPD
+;
+key_output '2'
+wait 4500000		; 312
+wait 4000000		; 313
+wait 4000000
+key_output ' '
+wait 10000000
+key_output ' '
+wait 1000000
+
+; 2 CSYNC RELATIVE; 
+key_output '3'
+wait 1000000  
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+
+; CSYNC MULTIPLES
+key_output '4'
+wait 1000000		; 37f
+key_output ' '
+wait 3000000	; 380
+key_output ' '
+wait 1000000
+
+; Hardware scroll 1 pixel mode 1/0 (no buffering)
+key_output '6'
+wait 10000000	; 381
+key_output ' '
+wait 10000000	; 382
+key_output ' '
+wait 1000000
+;
+; R2 oscillation story;
+key_output '7'
+wait 10000000	; 383
+key_output ' '
+wait 4000000	; 384
+key_output ' '
+wait 4000000	; 385
+key_output ' '
+wait 4000000	; 386
+key_output ' '
+wait 4000000	; 387
+key_output ' '
+wait 4000000	; 388
+key_output ' '
+wait 4000000	; 389
+key_output ' '
+wait 4000000	; 38a
+key_output ' '
+wait 4000000	; 38b
+key_output ' '
+wait 4000000	; 38c
+key_output ' '
+wait 1000000		; menu
+;
+; no hsync for xx line
+key_output '8'
+wait 3000000		; 38d
+key_output ' '
+wait 3000000		; 38e
+key_output ' '
+wait 3000000		; 38f
+key_output ' '
+wait 3000000		; 390
+key_output ' '
+wait 3000000		; 391
+key_output ' '
+wait 3000000		; 392
+key_output ' '
+wait 1000000		; menu
+
+
+csl_load 'SHAKE26D-4'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE D/SHAKE26D-3.CSL

@@ -0,0 +1,285 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26D du DSK SHAKER26.DSK en CRTC 4
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 3
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26D"\(RET)'
+wait 10000000
+;
+; SHAKER KILLER 2 
+key_output 'I'
+wait 2000000		; 2e3 ecran bleu
+key_output ' ' 
+wait 2000000		; 2e4
+key_output ' ' 
+wait 2000000		; 2e5
+key_output ' ' 
+wait 2000000		; 2e6
+key_output ' ' 
+wait 2000000		; 2e7
+key_output ' ' 
+wait 2000000		; 2e8
+key_output ' '
+wait 2000000		; 2e9
+key_output ' '
+wait 1000000 ; menu
+
+; VSYNC TORTURE (LOCK MECHANISM)
+; Eventuellement ajouter des SS sur les 3 tests desync crtc 0
+key_output 'R'
+wait 22000000		; 2ea
+key_output ' '
+wait 1000000 ; menu
+
+; VSYNC/CSYNC GATE ARRAY
+key_output 'T'
+wait 800000		; 2eb
+key_output ' '
+wait 2000000	; 2ec
+key_output ' '
+wait 2000000	; 2ed
+key_output ' '
+wait 2000000	; 2ee
+key_output ' '
+wait 2000000	; 2ef
+key_output ' '
+wait 2000000	; 2ef
+key_output ' '
+wait 2000000	; 2f0
+key_output ' '
+wait 2000000	; 2f1
+key_output ' '
+wait 2000000	; 2f2
+key_output ' '
+wait 2000000	; 2f3
+key_output ' '
+wait 2000000	; 2f4
+key_output ' '
+wait 2000000	; 2f5
+key_output ' '
+wait 2000000	; 2fb
+key_output ' '
+wait 8000000	; 2fc 2fd
+key_output ' '
+wait 4000000	; 2fe
+key_output ' '
+wait 4000000	; 2ff
+key_output ' '
+wait 4000000	; 300
+key_output ' '
+wait 4000000	; 301
+key_output ' '
+wait 1000000
+key_delay 90000
+key_output '                                                '
+key_output '                                                '
+wait 1000000 ; menu
+
+; HSYNC CSYNC GATE ARRAY
+key_output 'H'
+wait 1000000		; 306
+key_output ' '
+wait 1200000		; 307
+key_output ' '
+wait 1200000		; 308
+key_output ' '
+wait 1200000		; 309
+key_output ' '
+wait 1200000		; 30A
+key_output ' '
+wait 1200000		; 30B
+key_output ' '
+wait 1200000		; 30C
+key_output ' '
+wait 1200000		; 30D
+key_output ' '
+wait 1200000		; 30E
+key_output ' '
+wait 1200000		; 30F
+key_output ' '
+wait 1000000 ; menu
+
+; CSYNC4 VS 2XCSYNC2
+;
+key_output '1'
+wait 4600000 ; 310
+wait 4000000 ; 311
+wait 8000000
+key_output ' '
+wait 1000000 ; menu
+
+; R2JIT >> NO CSYNC UPD
+;
+key_output '2'
+wait 4500000		; 312
+wait 4000000		; 313
+wait 4000000
+key_output ' '
+wait 10000000
+key_output ' '
+wait 1000000
+
+; 2 CSYNC RELATIVE; 
+key_output '3'
+wait 1000000  
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+
+; CSYNC MULTIPLES
+key_output '4'
+wait 1000000		; 37f
+key_output ' '
+wait 3000000	; 380
+key_output ' '
+wait 1000000
+
+; Hardware scroll 1 pixel mode 1/0 (no buffering)
+key_output '6'
+wait 10000000	; 381
+key_output ' '
+wait 10000000	; 382
+key_output ' '
+wait 1000000
+
+;
+; R2 oscillation story;
+key_output '7'
+wait 10000000	; 383
+key_output ' '
+wait 4000000	; 384
+key_output ' '
+wait 4000000	; 385
+key_output ' '
+wait 4000000	; 386
+key_output ' '
+wait 4000000	; 387
+key_output ' '
+wait 4000000	; 388
+key_output ' '
+wait 4000000	; 389
+key_output ' '
+wait 4000000	; 38a
+key_output ' '
+wait 4000000	; 38b
+key_output ' '
+wait 4000000	; 38c
+key_output ' '
+wait 1000000		; menu
+;
+; no hsync for xx line
+key_output '8'
+wait 3000000		; 38d
+key_output ' '
+wait 3000000		; 38e
+key_output ' '
+wait 3000000		; 38f
+key_output ' '
+wait 3000000		; 390
+key_output ' '
+wait 3000000		; 391
+key_output ' '
+wait 3000000		; 392
+key_output ' '
+wait 1000000		; menu
+
+;
+; CRTC 3/4 STATUS
+key_output 'U'
+wait 10000000	; 3bc
+key_output ' '
+wait 10000000	; 3bd
+key_output ' '
+wait 10000000	; 3be
+key_output ' '
+wait 15000000 ; 3bf
+key_output ' '
+wait 45000000 ; 3c0
+key_output ' '
+wait 10000000 ; 3c1
+key_output ' '
+wait 4000000 ; 3c2
+key_output ' '
+wait 4000000 ; 3c3
+key_output ' '
+wait 4000000 ; 3c4
+key_output ' '
+wait 4000000 ; 3c5
+key_output ' '
+wait 4000000 ; 3c6
+key_output ' '
+wait 4000000 ; 3c7
+key_output ' '
+wait 4000000 ; 3c8
+key_output ' '
+wait 4000000 ; 3c9
+key_output ' '
+wait 4000000 ; 3ca
+key_output ' '
+wait 4000000 ; 3cb
+key_output ' '
+wait 4000000 ; 3cc
+key_output ' '
+wait 4000000 ; 3cd
+key_output ' '
+wait 4000000 ; 3ce
+key_output ' '
+wait 4000000 ; 3cf
+key_output ' '
+wait 4000000 ; 3d0
+key_output ' '
+wait 4000000 ; 3d1
+key_output ' '
+wait 4000000 ; 3d2
+key_output ' '
+wait 4000000 ; 3d3
+key_output ' '
+wait 4000000 ; 3d4
+key_output ' '
+wait 4000000 ; 3d5
+key_output ' '
+wait 4000000 ; 3d6
+key_output ' '
+wait 4000000 ; 3d7
+key_output ' '
+wait 4000000 ; 3d8
+key_output ' '
+wait 4000000 ; 3d9
+key_output ' '
+wait 4000000 ; 3da
+key_output ' '
+wait 4000000 ; 3db
+key_output ' '
+wait 4000000 ; 3dc
+key_output ' '
+wait 4000000 ; 3dd
+key_output ' '
+wait 4000000 ; 3de
+key_output ' '
+wait 4000000 ; 3df
+key_output ' '
+wait 4000000 ; 3e0
+key_output ' '
+wait 4000000 ; 3e1
+key_output ' '
+wait 4000000 ; 3e2
+key_output ' '
+wait 4000000 ; 3e3
+key_output ' '
+wait 4000000 ; 3e4
+key_output ' '
+wait 4000000		; menu
+reset

OSBindings/Mac/Clock SignalTests/Shaker/MODULE D/SHAKE26D-4.CSL

@@ -0,0 +1,286 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26D du DSK SHAKER26.DSK en CRTC 4
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 4
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26D"\(RET)'
+wait 10000000
+;
+; SHAKER KILLER 2 
+key_output 'I'
+wait 2000000		; 2e3 ecran bleu
+key_output ' ' 
+wait 2000000		; 2e4
+key_output ' ' 
+wait 2000000		; 2e5
+key_output ' ' 
+wait 2000000		; 2e6
+key_output ' ' 
+wait 2000000		; 2e7
+key_output ' ' 
+wait 2000000		; 2e8
+key_output ' '
+wait 2000000		; 2e9
+key_output ' '
+wait 1000000 ; menu
+
+; VSYNC TORTURE (LOCK MECHANISM)
+; Eventuellement ajouter des SS sur les 3 tests desync crtc 0
+key_output 'R'
+wait 22000000		; 2ea
+key_output ' '
+wait 1000000 ; menu
+
+; VSYNC/CSYNC GATE ARRAY
+key_output 'T'
+wait 800000		; 2eb
+key_output ' '
+wait 2000000	; 2ec
+key_output ' '
+wait 2000000	; 2ed
+key_output ' '
+wait 2000000	; 2ee
+key_output ' '
+wait 2000000	; 2ef
+key_output ' '
+wait 2000000	; 2ef
+key_output ' '
+wait 2000000	; 2f0
+key_output ' '
+wait 2000000	; 2f1
+key_output ' '
+wait 2000000	; 2f2
+key_output ' '
+wait 2000000	; 2f3
+key_output ' '
+wait 2000000	; 2f4
+key_output ' '
+wait 2000000	; 2f5
+key_output ' '
+wait 2000000	; 2fb
+key_output ' '
+wait 8000000	; 2fc 2fd
+key_output ' '
+wait 4000000	; 2fe
+key_output ' '
+wait 4000000	; 2ff
+key_output ' '
+wait 4000000	; 300
+key_output ' '
+wait 4000000	; 301
+key_output ' '
+wait 1000000
+key_delay 90000
+key_output '                                                '
+key_output '                                                '
+wait 1000000 ; menu
+
+; HSYNC CSYNC GATE ARRAY
+key_output 'H'
+wait 1000000		; 306
+key_output ' '
+wait 1200000		; 307
+key_output ' '
+wait 1200000		; 308
+key_output ' '
+wait 1200000		; 309
+key_output ' '
+wait 1200000		; 30A
+key_output ' '
+wait 1200000		; 30B
+key_output ' '
+wait 1200000		; 30C
+key_output ' '
+wait 1200000		; 30D
+key_output ' '
+wait 1200000		; 30E
+key_output ' '
+wait 1200000		; 30F
+key_output ' '
+wait 1000000 ; menu
+
+; CSYNC4 VS 2XCSYNC2
+;
+key_output '1'
+wait 4600000 ; 310
+wait 4000000 ; 311
+wait 8000000
+key_output ' '
+wait 1000000 ; menu
+
+; R2JIT >> NO CSYNC UPD
+;
+key_output '2'
+wait 4500000		; 312
+wait 4000000		; 313
+wait 4000000
+key_output ' '
+wait 10000000
+key_output ' '
+wait 1000000
+
+; 2 CSYNC RELATIVE; 
+key_output '3'
+wait 1000000  
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+key_output '                                                  '	
+wait 1000000
+
+; CSYNC MULTIPLES
+key_output '4'
+wait 1000000		; 37f
+key_output ' '
+wait 3000000	; 380
+key_output ' '
+wait 1000000
+
+; Hardware scroll 1 pixel mode 1/0 (no buffering)
+key_output '6'
+wait 10000000	; 381
+key_output ' '
+wait 10000000	; 382
+key_output ' '
+wait 1000000
+
+;
+; R2 oscillation story;
+key_output '7'
+wait 10000000	; 383
+key_output ' '
+wait 4000000	; 384
+key_output ' '
+wait 4000000	; 385
+key_output ' '
+wait 4000000	; 386
+key_output ' '
+wait 4000000	; 387
+key_output ' '
+wait 4000000	; 388
+key_output ' '
+wait 4000000	; 389
+key_output ' '
+wait 4000000	; 38a
+key_output ' '
+wait 4000000	; 38b
+key_output ' '
+wait 4000000	; 38c
+key_output ' '
+wait 1000000		; menu
+;
+; no hsync for xx line
+key_output '8'
+wait 3000000		; 38d
+key_output ' '
+wait 3000000		; 38e
+key_output ' '
+wait 3000000		; 38f
+key_output ' '
+wait 3000000		; 390
+key_output ' '
+wait 3000000		; 391
+key_output ' '
+wait 3000000		; 392
+key_output ' '
+wait 1000000		; menu
+
+;
+; CRTC 3/4 STATUS
+key_output 'U'
+wait 10000000	; 3bc
+key_output ' '
+wait 10000000	; 3bd
+key_output ' '
+wait 10000000	; 3be
+key_output ' '
+wait 15000000 ; 3bf
+key_output ' '
+wait 45000000 ; 3c0
+key_output ' '
+wait 10000000 ; 3c1
+key_output ' '
+wait 4000000 ; 3c2
+key_output ' '
+wait 4000000 ; 3c3
+key_output ' '
+wait 4000000 ; 3c4
+key_output ' '
+wait 4000000 ; 3c5
+key_output ' '
+wait 4000000 ; 3c6
+key_output ' '
+wait 4000000 ; 3c7
+key_output ' '
+wait 4000000 ; 3c8
+key_output ' '
+wait 4000000 ; 3c9
+key_output ' '
+wait 4000000 ; 3ca
+key_output ' '
+wait 4000000 ; 3cb
+key_output ' '
+wait 4000000 ; 3cc
+key_output ' '
+wait 4000000 ; 3cd
+key_output ' '
+wait 4000000 ; 3ce
+key_output ' '
+wait 4000000 ; 3cf
+key_output ' '
+wait 4000000 ; 3d0
+key_output ' '
+wait 4000000 ; 3d1
+key_output ' '
+wait 4000000 ; 3d2
+key_output ' '
+wait 4000000 ; 3d3
+key_output ' '
+wait 4000000 ; 3d4
+key_output ' '
+wait 4000000 ; 3d5
+key_output ' '
+wait 4000000 ; 3d6
+key_output ' '
+wait 4000000 ; 3d7
+key_output ' '
+wait 4000000 ; 3d8
+key_output ' '
+wait 4000000 ; 3d9
+key_output ' '
+wait 4000000 ; 3da
+key_output ' '
+wait 4000000 ; 3db
+key_output ' '
+wait 4000000 ; 3dc
+key_output ' '
+wait 4000000 ; 3dd
+key_output ' '
+wait 4000000 ; 3de
+key_output ' '
+wait 4000000 ; 3df
+key_output ' '
+wait 4000000 ; 3e0
+key_output ' '
+wait 4000000 ; 3e1
+key_output ' '
+wait 4000000 ; 3e2
+key_output ' '
+wait 4000000 ; 3e3
+key_output ' '
+wait 4000000 ; 3e4
+key_output ' '
+wait 4000000		; menu
+
+csl_load 'SHAKE26D-3'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE E/SHAKE26E-0.CSL

@@ -0,0 +1,37 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26E du DSK SHAKER26.DSK en CRTC 0
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 0
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26E"\(RET)'
+wait 10000000
+;
+; R5 STORIES 2ND ROUND 
+key_output '1'
+wait 2000000		; 3fa
+key_output ' ' 
+wait 2000000		; 3fb
+key_output ' ' 
+wait 2000000		; 3fc
+key_output ' ' 
+wait 2000000		; 3fd
+key_output ' ' 
+;
+;
+; CRTC 0 : C4/C9 COUNTER LOGIC
+key_output '3'
+wait 2000000		; 403
+key_output ' ' 
+wait 2000000		; 404
+key_output ' '
+wait 2000000		; 405
+key_output ' '
+;
+;
+csl_load 'SHAKE26E-1'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE E/SHAKE26E-1.CSL

@@ -0,0 +1,38 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26E du DSK SHAKER26.DSK en CRTC 1
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 1
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26E"\(RET)'
+wait 10000000
+;
+; R5 STORIES 2ND ROUND 
+key_output '1'
+wait 2000000		; 3fa
+key_output ' ' 
+wait 2000000		; 3fb
+key_output ' ' 
+wait 2000000		; 3fc
+key_output ' ' 
+wait 2000000		; 3fd
+key_output ' ' 
+;
+;
+; CRTC 1 : VMA TRT C4=R4=0 ON ADJ LINE
+;
+key_output '2'
+wait 2000000		; 400
+key_output ' ' 
+wait 2000000		; 401
+key_output ' '
+wait 2000000		; 402
+key_output ' '
+;
+;
+csl_load 'SHAKE26E-2'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE E/SHAKE26E-2.CSL

@@ -0,0 +1,28 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26E du DSK SHAKER26.DSK en CRTC 2
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 2
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26E"\(RET)'
+wait 10000000
+;
+; R5 STORIES 2ND ROUND 
+key_output '1'
+wait 2000000		; 3fa
+key_output ' ' 
+wait 2000000		; 3fb
+key_output ' ' 
+wait 2000000		; 3fc
+key_output ' ' 
+wait 2000000		; 3fd
+key_output ' ' 
+;
+;
+;
+csl_load 'SHAKE26E-4'

OSBindings/Mac/Clock SignalTests/Shaker/MODULE E/SHAKE26E-3.CSL

@@ -0,0 +1,27 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26E du DSK SHAKER26.DSK en CRTC 3
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 3
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26E"\(RET)'
+wait 10000000
+;
+; R5 STORIES 2ND ROUND 
+key_output '1'
+wait 2000000		; 3fa
+key_output ' ' 
+wait 2000000		; 3fb
+key_output ' ' 
+wait 2000000		; 3fc
+key_output ' ' 
+wait 2000000		; 3fd
+key_output ' ' 
+;
+;
+;

OSBindings/Mac/Clock SignalTests/Shaker/MODULE E/SHAKE26E-4.CSL

@@ -0,0 +1,28 @@
+;
+; Fichier de script CSL 
+; Execution du module SHAKE26E du DSK SHAKER26.DSK en CRTC 4
+; Le module genere des instructions au format SSM
+;
+csl_version 1.0
+crtc_select 4
+reset
+wait 3000000
+disk_insert 'shaker26.dsk'
+key_delay 70000 70000 400000
+key_output 'RUN"SHAKE26E"\(RET)'
+wait 10000000
+;
+; R5 STORIES 2ND ROUND 
+key_output '1'
+wait 2000000		; 3fa
+key_output ' ' 
+wait 2000000		; 3fb
+key_output ' ' 
+wait 2000000		; 3fc
+key_output ' ' 
+wait 2000000		; 3fd
+key_output ' ' 
+;
+;
+;
+csl_load 'SHAKE26E-3'

Outputs/CRT/CRT.cpp

@@ -444,9 +444,9 @@ void CRT::set_immediate_default_phase(float phase) {
 
 void CRT::output_data(int number_of_cycles, size_t number_of_samples) {
 #ifndef NDEBUG
-	assert(number_of_samples > 0);
-	assert(number_of_samples <= allocated_data_length_);
-	allocated_data_length_ = std::numeric_limits<size_t>::min();
+//	assert(number_of_samples > 0);
+//	assert(number_of_samples <= allocated_data_length_);
+//	allocated_data_length_ = std::numeric_limits<size_t>::min();
 #endif
 	scan_target_->end_data(number_of_samples);
 	Scan scan;

Processors/6502/Implementation/6502Implementation.hpp

@@ -59,10 +59,7 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
 	};
 
 	const auto throwaway_read = [&](uint16_t address) {
-		next_bus_operation_ = BusOperation::Read;
-		bus_address_ = address;
-		bus_value_ = &bus_throwaway_;
-		bus_throwaway_ = 0xff;
+		read_mem(bus_throwaway_, address);
 	};
 
 	const auto write_mem = [&](uint8_t &val, uint16_t address) {
@@ -232,10 +229,13 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
 
 // MARK: - JAM, WAI, STP
 
-					case OperationScheduleJam: {
+					case OperationSetJAMmed:
 						is_jammed_ = true;
-						scheduled_program_counter_ = operations_[CPU::MOS6502::JamOpcode];
-					} continue;
+						scheduled_program_counter_ -= 2;
+					continue;
+
+					case CycleFetchFFFE:	read_mem(bus_throwaway_, 0xfffe);	break;
+					case CycleFetchFFFF:	read_mem(bus_throwaway_, 0xffff);	break;
 
 					case OperationScheduleStop:
 						stop_is_active_ = true;
@@ -708,12 +708,23 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
 					continue;
 
 					case CycleFetchFromHalfUpdatedPC: {
-						uint16_t halfUpdatedPc = uint16_t(((pc_.halves.low + int8_t(operand_)) & 0xff) | (pc_.halves.high << 8));
-						throwaway_read(halfUpdatedPc);
+						uint16_t half_updated_pc = uint16_t(((pc_.halves.low + int8_t(operand_)) & 0xff) | (pc_.halves.high << 8));
+						throwaway_read(half_updated_pc);
 					} break;
 
+					case CycleFetchFromNextAddress:
+						throwaway_read(next_address_.full);
+					break;
+
 					case OperationAddSignedOperandToPC16:
+						next_address_ = pc_.full;
 						pc_.full = uint16_t(pc_.full + int8_t(operand_));
+
+						// Skip a step if 8-bit arithmetic would have been sufficient;
+						// in practise this operation is used only by BBS/BBR.
+						if(pc_.halves.high == next_address_.halves.high) {
+							++scheduled_program_counter_;
+						}
 					continue;
 
 					case OperationBBRBBS: {
@@ -725,7 +736,7 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
 						} else {
 							scheduled_program_counter_ = operations_[size_t(OperationsSlot::DoNotBBRBBS)];
 						}
-					} break;
+					} continue;
 
 // MARK: - Transfers
 
@@ -793,6 +804,9 @@ template <Personality personality, typename T, bool uses_ready_line> void Proces
 
 void ProcessorBase::set_reset_line(bool active) {
 	interrupt_requests_ = (interrupt_requests_ & ~InterruptRequestFlags::Reset) | (active ? InterruptRequestFlags::Reset : 0);
+	if(is_jammed_) {
+		restart_operation_fetch();
+	}
 }
 
 bool ProcessorBase::get_is_resetting() const {
@@ -859,6 +873,7 @@ void ProcessorBase::set_value_of(Register r, uint16_t value) {
 }
 
 void ProcessorBase::restart_operation_fetch() {
+	is_jammed_ = false;
 	scheduled_program_counter_ = nullptr;
 	next_bus_operation_ = BusOperation::None;
 }

Processors/6502/Implementation/6502Storage.cpp

@@ -73,7 +73,7 @@ using namespace CPU::MOS6502;
 #define ImpliedNop()						{OperationMoveToNextProgram}
 #define ImmediateNop()						Program(OperationIncrementPC)
 
-#define JAM									{CycleFetchOperand, OperationScheduleJam}
+#define JAM									{CycleFetchFFFF, CycleFetchFFFE, CycleFetchFFFE, CycleFetchFFFF, OperationSetJAMmed}
 
 ProcessorStorage::ProcessorStorage(Personality personality) {
 	const InstructionList operations_6502[] = {
@@ -269,18 +269,35 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
 
 		/* 0x105: Do BBR or BBS. */
 		Program(
-			CycleFetchOperand,				// Fetch offset.
+			CycleFetchOperand,					// Fetch offset, and increment PC.
 			OperationIncrementPC,
-			CycleFetchFromHalfUpdatedPC,
-			OperationAddSignedOperandToPC16
+
+			OperationAddSignedOperandToPC16,	// Calculate target PC, leaving old PC in next_address_
+												// and possibly skipping the next instruction.
+
+			CycleFetchFromNextAddress,
+			CycleFetchFromNextAddress
 		),
+		// Six or seven cycles total are:
+		//	(1) operation;
+		//	(2) zero page address as operand;
+		//	(3) zero page address;
+		//	(4) duplicate of (3);
+		//	(5) further operand;
+		//	(6) read from next PC;
+		//	(7) repeat read from next PC if 16-bit arithmetic was required.
 
 		/* 0x106: Complete BBR or BBS without branching. */
 		Program(
-			CycleFetchOperand,
-			OperationIncrementPC,
-			CycleFetchFromHalfUpdatedPC
+			CycleFetchOperand,				// Fetch offset.
+			OperationIncrementPC
 		)
+		// Five cycles total are:
+		//	(1) operation;
+		//	(2) zero page address as operand;
+		//	(3) zero page address;
+		//	(4) duplicate of (3);
+		//	(5) further operand, which goes unused.
 	};
 
 	static_assert(sizeof(operations_6502) == sizeof(operations_));
@@ -408,15 +425,25 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
 		// 0xc7, 0xcb, 0xcf, 0xd7, 0xdb, 0xdf,
 		// 0xe7, 0xef, 0xf7, 0xff
 		if(has_bbrbbsrmbsmb(personality)) {
-			// Add BBS and BBR. These take five cycles. My guessed breakdown is:
+			// Add BBS and BBR. These take five, six or seven cycles. First five:
 			// 1. read opcode
-			// 2. read operand
+			// 2. read first operand (i.e. zero-page address)
 			// 3. read zero page
-			// 4. read second operand
-			// 5. read from PC without top byte fixed yet
-			// ... with the caveat that (3) and (4) could be the other way around.
+			// 4. reread zero page	(presumably as a stall, to make a decision on the above)
+			// 5. read second operand (i.e. branch offset)
+			//
+			// ... and then, if the branch is taken:
+			//
+			// 6. read from where next instruction would have been
+			// 7. reread, if a further stall is necessary to cover up for a 16-bit address change.
 			for(int location = 0x0f; location <= 0xff; location += 0x10) {
-				Install(location, Program(OperationLoadAddressZeroPage, CycleFetchOperandFromAddress, OperationBBRBBS));
+				Install(location, Program(
+					OperationLoadAddressZeroPage,
+					CycleFetchOperandFromAddress,	// (cycle 3)
+					CycleFetchOperandFromAddress,	// (cycle 4)
+					OperationBBRBBS	// Branches to either OperationsSlot::DoBBRBBS, or to
+									// OperationSlot::DoNotBBRBBS, depending on data read.
+				));
 			}
 
 			// Add RMB and SMB.

Processors/6502/Implementation/6502Storage.hpp

@@ -186,7 +186,9 @@ class ProcessorStorage {
 
 			CycleFetchFromHalfUpdatedPC,		// performs a throwaway read from (PC + (signed)operand).l combined with PC.h
 			CycleAddSignedOperandToPC,			// sets next_address to PC + (signed)operand. If the high byte of next_address differs from the PC, schedules a throwaway read from the half-updated PC. 65C02 specific: if the top two bytes are the same, proceeds directly to fetch-decode-execute, ignoring any pending interrupts.
-			OperationAddSignedOperandToPC16,	// adds (signed)operand into the PC
+			OperationAddSignedOperandToPC16,	// adds (signed)operand into the PC, leaving old PC in next_address_ and skipping a program step if there was no carry from low to high byte
+
+			CycleFetchFromNextAddress, 			// performs a throwaway fetch from next_address_
 
 			OperationSetFlagsFromOperand,			// sets all flags based on operand_
 			OperationSetOperandFromFlagsWithBRKSet,	// sets operand_ to the value of all flags, with the break flag set
@@ -196,9 +198,12 @@ class ProcessorStorage {
 			OperationSetFlagsFromX,		// sets the zero and negative flags based on the value of x
 			OperationSetFlagsFromY,		// sets the zero and negative flags based on the value of y
 
-			OperationScheduleJam,		// schedules the program for operation F2
-			OperationScheduleWait,		// puts the processor into WAI mode (i.e. it'll do nothing until an interrupt is received)
-			OperationScheduleStop,		// puts the processor into STP mode (i.e. it'll do nothing until a reset is received)
+			OperationScheduleWait,			// puts the processor into WAI mode (i.e. it'll do nothing until an interrupt is received)
+			OperationScheduleStop,			// puts the processor into STP mode (i.e. it'll do nothing until a reset is received)
+
+			CycleFetchFFFE,			// perform a throwaway read from $FFFE
+			CycleFetchFFFF,			// perform a throwaway read from $FFFF
+			OperationSetJAMmed,		// decrements the micro-operation program counter back to the operation before this one, marking the CPU as jammed
 		};
 
 		using InstructionList = MicroOp[12];

Storage/Automation/CSL.cpp

@@ -0,0 +1,382 @@
+//
+//  CSL.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 12/06/2024.
+//  Copyright © 2024 Thomas Harte. All rights reserved.
+//
+
+#include "CSL.hpp"
+
+#include <cctype>
+#include <fstream>
+#include <sstream>
+#include <unordered_map>
+#include <set>
+
+#include "../../Machines/AmstradCPC/Keyboard.hpp"
+
+using namespace Storage::Automation;
+
+namespace {
+
+bool append_typed(std::vector<Storage::Automation::CSL::KeyEvent> &down, std::vector<Storage::Automation::CSL::KeyEvent> &up, std::istringstream &stream) {
+	const auto press = [&](uint16_t key) {
+		CSL::KeyEvent event;
+		event.key = key;
+		event.down = true;
+		down.push_back(event);
+		event.down = false;
+		up.push_back(event);
+	};
+
+	const auto shift = [&](uint16_t key) {
+		CSL::KeyEvent event;
+		event.key = AmstradCPC::Key::KeyShift;
+		event.down = true;
+		down.push_back(event);
+		press(key);
+		event.down = false;
+		up.push_back(event);
+	};
+
+	const auto next = stream.get();
+	if(stream.eof()) return false;
+
+	switch(next) {
+		default: throw CSL::InvalidArgument;
+		case '\'': return false;
+		case '}': return false;
+
+		case 'A':	press(AmstradCPC::Key::KeyA);		break;
+		case 'B':	press(AmstradCPC::Key::KeyB);		break;
+		case 'C':	press(AmstradCPC::Key::KeyC);		break;
+		case 'D':	press(AmstradCPC::Key::KeyD);		break;
+		case 'E':	press(AmstradCPC::Key::KeyE);		break;
+		case 'F':	press(AmstradCPC::Key::KeyF);		break;
+		case 'G':	press(AmstradCPC::Key::KeyG);		break;
+		case 'H':	press(AmstradCPC::Key::KeyH);		break;
+		case 'I':	press(AmstradCPC::Key::KeyI);		break;
+		case 'J':	press(AmstradCPC::Key::KeyJ);		break;
+		case 'K':	press(AmstradCPC::Key::KeyK);		break;
+		case 'L':	press(AmstradCPC::Key::KeyL);		break;
+		case 'M':	press(AmstradCPC::Key::KeyM);		break;
+		case 'N':	press(AmstradCPC::Key::KeyN);		break;
+		case 'O':	press(AmstradCPC::Key::KeyO);		break;
+		case 'P':	press(AmstradCPC::Key::KeyP);		break;
+		case 'Q':	press(AmstradCPC::Key::KeyQ);		break;
+		case 'R':	press(AmstradCPC::Key::KeyR);		break;
+		case 'S':	press(AmstradCPC::Key::KeyS);		break;
+		case 'T':	press(AmstradCPC::Key::KeyT);		break;
+		case 'U':	press(AmstradCPC::Key::KeyU);		break;
+		case 'V':	press(AmstradCPC::Key::KeyV);		break;
+		case 'W':	press(AmstradCPC::Key::KeyW);		break;
+		case 'X':	press(AmstradCPC::Key::KeyX);		break;
+		case 'Y':	press(AmstradCPC::Key::KeyY);		break;
+		case 'Z':	press(AmstradCPC::Key::KeyZ);		break;
+		case ' ':	press(AmstradCPC::Key::KeySpace);	break;
+		case '0':	press(AmstradCPC::Key::Key0);		break;
+		case '1':	press(AmstradCPC::Key::Key1);		break;
+		case '2':	press(AmstradCPC::Key::Key2);		break;
+		case '3':	press(AmstradCPC::Key::Key3);		break;
+		case '4':	press(AmstradCPC::Key::Key4);		break;
+		case '5':	press(AmstradCPC::Key::Key5);		break;
+		case '6':	press(AmstradCPC::Key::Key6);		break;
+		case '7':	press(AmstradCPC::Key::Key7);		break;
+		case '8':	press(AmstradCPC::Key::Key8);		break;
+		case '9':	press(AmstradCPC::Key::Key9);		break;
+
+		case '"':	shift(AmstradCPC::Key::Key2);		break;
+
+		case '\\': {
+			if(stream.peek() != '(') {
+				press(AmstradCPC::Key::KeyBackSlash);
+				break;
+			}
+			stream.get();
+
+			std::string name;
+			while(stream.peek() != ')') {
+				name.push_back(char(stream.get()));
+			}
+			stream.get();
+
+			static const std::unordered_map<std::string, uint16_t> names = {
+				{"ESC", AmstradCPC::Key::KeyEscape},
+				{"TAB", AmstradCPC::Key::KeyTab},
+				{"CAP", AmstradCPC::Key::KeyCapsLock},
+				{"SHI", AmstradCPC::Key::KeyShift},
+				{"CTR", AmstradCPC::Key::KeyControl},
+				{"COP", AmstradCPC::Key::KeyCopy},
+				{"CLR", AmstradCPC::Key::KeyClear},
+				{"DEL", AmstradCPC::Key::KeyDelete},
+				{"RET", AmstradCPC::Key::KeyReturn},
+				{"ENT", AmstradCPC::Key::KeyEnter},
+				{"ARL", AmstradCPC::Key::KeyLeft},
+				{"ARR", AmstradCPC::Key::KeyRight},
+				{"ARU", AmstradCPC::Key::KeyUp},
+				{"ARD", AmstradCPC::Key::KeyDown},
+				{"FN0", AmstradCPC::Key::KeyF0},
+				{"FN1", AmstradCPC::Key::KeyF1},
+				{"FN2", AmstradCPC::Key::KeyF2},
+				{"FN3", AmstradCPC::Key::KeyF3},
+				{"FN4", AmstradCPC::Key::KeyF4},
+				{"FN5", AmstradCPC::Key::KeyF5},
+				{"FN6", AmstradCPC::Key::KeyF6},
+				{"FN7", AmstradCPC::Key::KeyF7},
+				{"FN8", AmstradCPC::Key::KeyF8},
+				{"FN9", AmstradCPC::Key::KeyF9},
+				//TODO: { } \ ' KOF
+			};
+			const auto name_pair = names.find(name);
+			if(name_pair == names.end()) {
+				throw CSL::InvalidArgument;
+			}
+			press(name_pair->second);
+		} break;
+
+		case '{':
+			while(append_typed(down, up, stream));
+		break;
+	}
+
+	return true;
+}
+
+}
+
+std::vector<CSL::Instruction> CSL::parse(const std::string &file_name) {
+	std::vector<Instruction> instructions;
+	std::ifstream file;
+	file.open(file_name);
+
+	using Type = Instruction::Type;
+	static const std::unordered_map<std::string, Type> keywords = {
+		{"csl_version", Type::Version},
+		{"reset", Type::Reset},
+		{"crtc_select", Type::CRTCSelect},
+		{"disk_insert", Type::DiskInsert},
+		{"disk_dir", Type::SetDiskDir},
+		{"tape_insert", Type::TapeInsert},
+		{"tape_dir", Type::SetTapeDir},
+		{"tape_play", Type::TapeInsert},
+		{"tape_stop", Type::TapeStop},
+		{"tape_rewind", Type::TapeRewind},
+		{"snapshot_load", Type::LoadSnapshot},
+		{"snapshot_dir", Type::SetSnapshotDir},
+		{"key_delay", Type::KeyDelay},
+		{"key_output", Type::KeyOutput},
+		{"key_from_file", Type::KeyFromFile},
+		{"wait", Type::Wait},
+		{"wait_driveonoff", Type::WaitDriveOnOff},
+		{"wait_ssm0000", Type::WaitSSM0000},
+		{"screenshot_name", Type::SetScreenshotName},
+		{"screenshot_dir", Type::SetScreenshotDir},
+		{"screenshot", Type::Screenshot},
+		{"snapshot_name", Type::SetSnapshotDir},
+		{"csl_load", Type::LoadCSL},
+	};
+
+	for(std::string line; std::getline(file, line); ) {
+		// Ignore comments and empty lines.
+		if(line.empty() || line[0] == ';') {
+			continue;
+		}
+
+		std::istringstream stream(line);
+		std::string keyword;
+		stream >> keyword;
+
+		// Second way for a line to be empty: purely whitespace.
+		if(keyword.empty()) {
+			continue;
+		}
+
+		const auto key_pair = keywords.find(keyword);
+		if(key_pair == keywords.end()) {
+			throw InvalidKeyword;
+		}
+
+		Instruction instruction;
+		instruction.type = key_pair->second;
+
+		// TODO: strings are encoded specially in order to capture whitespace.
+		// They're surrounded in single quotes with some special keys escaped.
+		const auto require = [&](auto &&target) {
+			stream >> target;
+			if(stream.fail()) {
+				throw InvalidArgument;
+			}
+		};
+
+		switch(instruction.type) {
+			// Keywords with no argument.
+			case Type::TapePlay:
+			case Type::TapeStop:
+			case Type::TapeRewind:
+			case Type::WaitVsyncOnOff:
+			case Type::WaitSSM0000:
+			break;
+
+			// Keywords with a single string mandatory argument
+			// that can be directly captured as a string.
+			case Type::Version: {
+				std::string argument;
+				require(argument);
+				instruction.argument = argument;
+			} break;
+
+			// Keywords with a single string mandatory argument
+			// that is within quotes but otherwise directly usable
+			// as a string.
+			case Type::LoadCSL:
+			case Type::SetScreenshotDir:
+			case Type::SetScreenshotName:
+			case Type::SetSnapshotDir:
+			case Type::SetSnapshotName:
+			case Type::LoadSnapshot:
+			case Type::SetTapeDir:
+			case Type::TapeInsert:
+			case Type::SetDiskDir:
+			case Type::KeyFromFile: {
+				std::string argument;
+
+				char next;
+				stream >> next;
+				if(next != '\'') {
+					throw InvalidArgument;
+				}
+
+				while(true) {
+					next = static_cast<char>(stream.get());
+					if(stream.eof()) break;
+
+					// Take a bit of a random guess about what's escaped
+					// in regular string arguments.
+					if(next == '\\' && stream.peek() == '(') {
+						stream.get();
+						if(stream.peek() != '\'') {
+							argument.push_back('\\');
+							argument.push_back('(');
+							continue;
+						}
+					}
+
+					if(next == '\'') {
+						break;
+					}
+					argument.push_back(next);
+				}
+				instruction.argument = argument;
+			} break;
+
+			// Keywords with a single number mandatory argument.
+			case Type::WaitDriveOnOff:
+			case Type::Wait: {
+				uint64_t argument;
+				require(argument);
+				instruction.argument = argument;
+			} break;
+
+			// Miscellaneous:
+			case Type::Snapshot:
+			case Type::Screenshot: {
+				std::string vsync;
+				stream >> vsync;
+				if(stream.fail()) {
+					instruction.argument = ScreenshotOrSnapshot::Now;
+					break;
+				}
+				if(vsync != "vsync") {
+					throw InvalidArgument;
+				}
+				instruction.argument = ScreenshotOrSnapshot::WaitForVSync;
+			} break;
+
+			case Type::Reset: {
+				std::string type;
+				stream >> type;
+				if(!stream.fail()) {
+					if(type != "soft" && type != "hard") {
+						throw InvalidArgument;
+					}
+					instruction.argument = (type == "soft") ? Reset::Soft : Reset::Hard;
+				}
+			} break;
+
+			case Type::CRTCSelect: {
+				std::string type;
+				require(type);
+
+				static const std::set<std::string> allowed_types = {
+					"0", "1", "1A", "1B", "2", "3", "4",
+				};
+				if(allowed_types.find(type) == allowed_types.end()) {
+					throw InvalidArgument;
+				}
+
+				instruction.argument = static_cast<uint64_t>(std::stoi(type));
+			} break;
+
+			case Type::DiskInsert: {
+				std::string name;
+				require(name);
+
+				// Crop the assumed opening and closing quotes.
+				name.erase(name.end() - 1);
+				name.erase(name.begin());
+
+				DiskInsert argument;
+				if(name.size() == 1) {
+					argument.drive = toupper(name[0]) - 'A';
+					require(name);
+				}
+
+				argument.file = name;
+				instruction.argument = argument;
+			} break;
+
+			case Type::KeyOutput: {
+				std::vector<KeyEvent> argument;
+
+				char next;
+				stream >> next;
+				if(next != '\'') {
+					throw InvalidArgument;
+				}
+
+				std::vector<KeyEvent> down;
+				std::vector<KeyEvent> up;
+				while(append_typed(down, up, stream)) {
+					std::copy(down.begin(), down.end(), std::back_inserter(argument));
+					std::copy(up.begin(), up.end(), std::back_inserter(argument));
+					down.clear();
+					up.clear();
+				}
+				instruction.argument = argument;
+			} break;
+
+			case Type::KeyDelay: {
+				KeyDelay argument;
+				require(argument.press_delay);
+
+				uint64_t interpress_delay;
+				stream >> interpress_delay;
+				if(!stream.fail()) {
+					argument.interpress_delay = argument.press_delay;
+				}
+
+				uint64_t carriage_return_delay;
+				stream >> carriage_return_delay;
+				if(!stream.fail()) {
+					argument.carriage_return_delay = carriage_return_delay;
+				}
+				instruction.argument = argument;
+			} break;
+		}
+
+		instructions.push_back(std::move(instruction));
+	}
+
+	return instructions;
+}

Storage/Automation/CSL.hpp

@@ -0,0 +1,93 @@
+//
+//  CSL.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 12/06/2024.
+//  Copyright © 2024 Thomas Harte. All rights reserved.
+//
+
+#pragma once
+
+#include <cstdint>
+#include <optional>
+#include <string>
+#include <variant>
+#include <vector>
+
+namespace Storage::Automation::CSL {
+
+enum Reset {
+	Hard, Soft
+};
+struct DiskInsert {
+	int drive = 0;
+	std::string file;
+};
+enum ScreenshotOrSnapshot {
+	WaitForVSync, Now,
+};
+struct KeyDelay {
+	uint64_t press_delay;
+	uint64_t interpress_delay;
+	std::optional<uint64_t> carriage_return_delay;
+};
+struct KeyEvent {
+	bool down;
+	uint16_t key;
+};
+
+struct Instruction {
+	enum class Type {
+		Version,
+		Reset,
+		CRTCSelect,
+		LoadCSL,
+
+		DiskInsert,
+		SetDiskDir,
+
+		TapeInsert,
+		SetTapeDir,
+		TapePlay,
+		TapeStop,
+		TapeRewind,
+
+		SetSnapshotDir,
+		LoadSnapshot,
+		SetSnapshotName,
+		Snapshot,
+
+		KeyDelay,
+		KeyOutput,
+		KeyFromFile,
+
+		Wait,
+		WaitDriveOnOff,
+		WaitVsyncOnOff,
+		WaitSSM0000,
+
+		SetScreenshotName,
+		SetScreenshotDir,
+		Screenshot,
+	} type;
+
+	std::variant<
+		std::monostate,
+		DiskInsert,
+		Reset,
+		ScreenshotOrSnapshot,
+		KeyDelay,
+		std::string,
+		std::vector<KeyEvent>,
+		uint64_t
+	> argument;
+};
+
+
+enum Errors {
+	InvalidKeyword,
+	InvalidArgument,
+};
+std::vector<Instruction> parse(const std::string &file_name);
+
+}

Storage/Disk/Encodings/MFM/Parser.cpp

@@ -71,3 +71,15 @@ const Sector *Parser::sector(int head, int track, uint8_t sector) {
 
 	return &stored_sector->second;
 }
+
+const Sector *Parser::any_sector(int head, int track) {
+	const Disk::Track::Address address(head, Storage::Disk::HeadPosition(track));
+	install_track(address);
+
+	const auto sectors = sectors_by_address_by_track_.find(address);
+	if(sectors == sectors_by_address_by_track_.end()) {
+		return nullptr;
+	}
+
+	return &sectors->second.begin()->second;
+}

Storage/Disk/Encodings/MFM/Parser.hpp

@@ -37,6 +37,14 @@ class Parser {
 		*/
 		const Storage::Encodings::MFM::Sector *sector(int head, int track, uint8_t sector);
 
+
+		/*!
+			Seeks to the physical track at @c head and @c track. Searches on it for any sector.
+
+			@returns a sector if one was found; @c nullptr otherwise.
+		*/
+		const Storage::Encodings::MFM::Sector *any_sector(int head, int track);
+
 		// TODO: set_sector.
 
 	private:

Storage/Disk/Parsers/CPM.cpp

@@ -158,3 +158,13 @@ std::unique_ptr<Storage::Disk::CPM::Catalogue> Storage::Disk::CPM::GetCatalogue(
 
 	return result;
 }
+
+bool Catalogue::is_zx_spectrum_booter() {
+	// Check for a file called 'DISK'.
+	const auto file = std::find_if(files.begin(), files.end(), [](const auto &file) { return file.name == "DISK    "; });
+	if(file == files.end()) return false;
+
+	// TODO: check the file is valid ZX Spectrum BASIC.
+
+	return true;
+}

Storage/Disk/Parsers/CPM.hpp

@@ -24,6 +24,29 @@ struct ParameterBlock {
 	int first_sector;
 	uint16_t catalogue_allocation_bitmap;
 	int reserved_tracks;
+
+	// Some well-known formats.
+	static ParameterBlock cpc_data_format() {
+		Storage::Disk::CPM::ParameterBlock data_format;
+		data_format.sectors_per_track = 9;
+		data_format.tracks = 40;
+		data_format.block_size = 1024;
+		data_format.first_sector = 0xc1;
+		data_format.catalogue_allocation_bitmap = 0xc000;
+		data_format.reserved_tracks = 0;
+		return data_format;
+	}
+
+	static ParameterBlock cpc_system_format() {
+		Storage::Disk::CPM::ParameterBlock system_format;
+		system_format.sectors_per_track = 9;
+		system_format.tracks = 40;
+		system_format.block_size = 1024;
+		system_format.first_sector = 0x41;
+		system_format.catalogue_allocation_bitmap = 0xc000;
+		system_format.reserved_tracks = 2;
+		return system_format;
+	}
 };
 
 struct File {
@@ -37,6 +60,8 @@ struct File {
 
 struct Catalogue {
 	std::vector<File> files;
+
+	bool is_zx_spectrum_booter();
 };
 
 std::unique_ptr<Catalogue> GetCatalogue(const std::shared_ptr<Storage::Disk::Disk> &disk, const ParameterBlock &parameters);