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627 lines
24 KiB
C++
627 lines
24 KiB
C++
//
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// Decoder.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 20/10/2025.
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// Copyright © 2025 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "Model.hpp"
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#include <type_traits>
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namespace CPU::MOS6502Mk2 {
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enum class Operation {
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BRK,
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NOP, FastNOP,
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ORA, AND, EOR,
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INS, ADC, SBC,
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CMP, CPX, CPY,
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BIT, BITNoNV,
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LDA, LDX, LDY, LAX,
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STA, STX, STY, STZ, SAX, SHA, SHX, SHY, SHS,
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ASL, ASO, ROL, RLA, LSR, LSE, ASR, ROR, RRA,
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CLC, CLI, CLV, CLD, SEC, SEI, SED,
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RMB, SMB, TRB, TSB,
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INC, DEC, INX, DEX, INY, DEY, INA, DEA, DCP,
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BPL, BMI, BVC, BVS, BCC, BCS, BNE, BEQ, BRA,
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BBRBBS,
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TXA, TYA, TXS, TAY, TAX, TSX,
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ARR, SBX, LXA, ANE, ANC, LAS,
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JSR, RTI, RTS,
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PHP, PLP, JMP,
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JAM, STP, WAI,
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};
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enum class AddressingMode {
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Implied,
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Immediate,
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Accumulator,
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Relative,
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Push,
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Pull,
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Absolute,
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AbsoluteIndexed,
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FastAbsoluteIndexedModify,
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Zero,
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ZeroIndexed,
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ZeroIndirect,
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IndexedIndirect,
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IndirectIndexed,
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// Irregular flow control.
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BRK, JSR, RTI, RTS,
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BBRBBS,
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JMPAbsolute,
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JMPAbsoluteIndirect,
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JMPAbsoluteIndexedIndirect,
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// Irregular unintended, undocumented and unreliable.
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SHxIndirectIndexed,
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SHxAbsoluteXY,
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// Terminal or semi-terminal.
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STP,
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WAI,
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JAM,
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Max,
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};
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enum class Index {
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X, Y
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};
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constexpr Index index_of(const Operation operation) {
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switch(operation) {
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default: return Index::X;
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case Operation::STX: case Operation::LDX:
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case Operation::SAX: case Operation::LAX:
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return Index::Y;
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}
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}
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enum class Type {
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Read, Modify, Write
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};
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constexpr Type type_of(const Operation operation) {
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switch(operation) {
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// All of these don't really fit the type orthodoxy.
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case Operation::BRK: case Operation::JAM:
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case Operation::SHA: case Operation::SHX: case Operation::SHY:
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case Operation::SHS: case Operation::CLC: case Operation::CLI:
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case Operation::CLV: case Operation::CLD: case Operation::SEC:
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case Operation::SEI: case Operation::SED:
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case Operation::INX: case Operation::DEX: case Operation::INY:
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case Operation::DEY: case Operation::INA: case Operation::DEA:
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case Operation::BPL: case Operation::BMI: case Operation::BVC:
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case Operation::BVS: case Operation::BCC: case Operation::BCS:
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case Operation::BNE: case Operation::BEQ: case Operation::BRA:
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case Operation::TXA: case Operation::TYA: case Operation::TXS:
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case Operation::TAY: case Operation::TAX: case Operation::TSX:
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case Operation::JSR: case Operation::RTI: case Operation::RTS:
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case Operation::PHP: case Operation::PLP: case Operation::JMP:
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case Operation::BBRBBS:
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case Operation::STP: case Operation::WAI:
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case Operation::FastNOP:
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return Type::Modify;
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case Operation::ORA: case Operation::AND: case Operation::EOR:
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case Operation::ADC: case Operation::SBC:
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case Operation::CMP: case Operation::CPX: case Operation::CPY:
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case Operation::BIT: case Operation::BITNoNV:
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case Operation::LDA: case Operation::LDX:
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case Operation::LDY: case Operation::LAX:
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case Operation::ARR: case Operation::SBX: case Operation::LXA:
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case Operation::ANE: case Operation::ANC: case Operation::LAS:
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case Operation::NOP:
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return Type::Read;
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case Operation::STA: case Operation::STX: case Operation::STY:
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case Operation::STZ: case Operation::SAX:
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return Type::Write;
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case Operation::INS:
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case Operation::ASL: case Operation::ASO: case Operation::ROL:
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case Operation::RLA: case Operation::LSR: case Operation::LSE:
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case Operation::ASR: case Operation::ROR: case Operation::RRA:
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case Operation::RMB: case Operation::SMB:
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case Operation::TRB: case Operation::TSB:
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case Operation::INC: case Operation::DEC: case Operation::DCP:
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return Type::Modify;
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}
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return Type::Read;
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}
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struct Instruction {
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consteval Instruction(const AddressingMode mode, const Operation operation) noexcept :
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operation(operation), mode(mode), index(index_of(operation)), type(type_of(operation)) {}
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consteval Instruction(const AddressingMode mode, const Index index, const Operation operation) noexcept :
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operation(operation), mode(mode), index(index), type(type_of(operation)) {}
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Instruction() = default;
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Operation operation;
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AddressingMode mode;
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Index index;
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Type type;
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};
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template <Model model, typename Enable = void> struct Decoder;
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template <Model model>
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struct Decoder<model, std::enable_if_t<is_6502(model)>> {
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static constexpr Instruction decode(const uint8_t opcode) {
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using enum AddressingMode;
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switch(opcode) {
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case 0x00: return {BRK, Operation::BRK};
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case 0x20: return {JSR, Operation::JSR};
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case 0x40: return {RTI, Operation::RTI};
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case 0x60: return {RTS, Operation::RTS};
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case 0x80: return {Immediate, Operation::NOP};
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case 0xa0: return {Immediate, Operation::LDY};
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case 0xc0: return {Immediate, Operation::CPY};
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case 0xe0: return {Immediate, Operation::CPX};
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case 0x01: return {IndexedIndirect, Operation::ORA};
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case 0x21: return {IndexedIndirect, Operation::AND};
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case 0x41: return {IndexedIndirect, Operation::EOR};
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case 0x61: return {IndexedIndirect, Operation::ADC};
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case 0x81: return {IndexedIndirect, Operation::STA};
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case 0xa1: return {IndexedIndirect, Operation::LDA};
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case 0xc1: return {IndexedIndirect, Operation::CMP};
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case 0xe1: return {IndexedIndirect, Operation::SBC};
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case 0x02: return {JAM, Operation::JAM};
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case 0x22: return {JAM, Operation::JAM};
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case 0x42: return {JAM, Operation::JAM};
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case 0x62: return {JAM, Operation::JAM};
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case 0x82: return {Immediate, Operation::NOP};
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case 0xa2: return {Immediate, Operation::LDX};
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case 0xc2: return {Immediate, Operation::NOP};
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case 0xe2: return {Immediate, Operation::NOP};
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case 0x03: return {IndexedIndirect, Operation::ASO};
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case 0x23: return {IndexedIndirect, Operation::RLA};
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case 0x43: return {IndexedIndirect, Operation::LSE};
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case 0x63: return {IndexedIndirect, Operation::RRA};
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case 0x83: return {IndexedIndirect, Operation::SAX};
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case 0xa3: return {IndexedIndirect, Operation::LAX};
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case 0xc3: return {IndexedIndirect, Operation::DCP};
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case 0xe3: return {IndexedIndirect, Operation::INS};
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case 0x04: return {Zero, Operation::NOP};
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case 0x24: return {Zero, Operation::BIT};
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case 0x44: return {Zero, Operation::NOP};
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case 0x64: return {Zero, Operation::NOP};
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case 0x84: return {Zero, Operation::STY};
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case 0xa4: return {Zero, Operation::LDY};
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case 0xc4: return {Zero, Operation::CPY};
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case 0xe4: return {Zero, Operation::CPX};
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case 0x05: return {Zero, Operation::ORA};
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case 0x25: return {Zero, Operation::AND};
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case 0x45: return {Zero, Operation::EOR};
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case 0x65: return {Zero, Operation::ADC};
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case 0x85: return {Zero, Operation::STA};
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case 0xa5: return {Zero, Operation::LDA};
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case 0xc5: return {Zero, Operation::CMP};
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case 0xe5: return {Zero, Operation::SBC};
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case 0x06: return {Zero, Operation::ASL};
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case 0x26: return {Zero, Operation::ROL};
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case 0x46: return {Zero, Operation::LSR};
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case 0x66: return {Zero, Operation::ROR};
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case 0x86: return {Zero, Operation::STX};
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case 0xa6: return {Zero, Operation::LDX};
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case 0xc6: return {Zero, Operation::DEC};
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case 0xe6: return {Zero, Operation::INC};
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case 0x07: return {Zero, Operation::ASO};
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case 0x27: return {Zero, Operation::RLA};
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case 0x47: return {Zero, Operation::LSE};
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case 0x67: return {Zero, Operation::RRA};
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case 0x87: return {Zero, Operation::SAX};
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case 0xa7: return {Zero, Operation::LAX};
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case 0xc7: return {Zero, Operation::DCP};
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case 0xe7: return {Zero, Operation::INS};
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case 0x08: return {Push, Operation::PHP};
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case 0x28: return {Pull, Operation::PLP};
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case 0x48: return {Push, Operation::STA};
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case 0x68: return {Pull, Operation::LDA};
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case 0x88: return {Implied, Operation::DEY};
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case 0xa8: return {Implied, Operation::TAY};
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case 0xc8: return {Implied, Operation::INY};
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case 0xe8: return {Implied, Operation::INX};
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case 0x09: return {Immediate, Operation::ORA};
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case 0x29: return {Immediate, Operation::AND};
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case 0x49: return {Immediate, Operation::EOR};
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case 0x69: return {Immediate, Operation::ADC};
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case 0x89: return {Immediate, Operation::NOP};
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case 0xa9: return {Immediate, Operation::LDA};
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case 0xc9: return {Immediate, Operation::CMP};
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case 0xe9: return {Immediate, Operation::SBC};
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case 0x0a: return {Accumulator, Operation::ASL};
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case 0x2a: return {Accumulator, Operation::ROL};
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case 0x4a: return {Accumulator, Operation::LSR};
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case 0x6a: return {Accumulator, Operation::ROR};
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case 0x8a: return {Implied, Operation::TXA};
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case 0xaa: return {Implied, Operation::TAX};
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case 0xca: return {Implied, Operation::DEX};
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case 0xea: return {Implied, Operation::NOP};
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case 0x0b: return {Immediate, Operation::ANC};
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case 0x2b: return {Immediate, Operation::ANC};
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case 0x4b: return {Immediate, Operation::ASR};
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case 0x6b: return {Immediate, Operation::ARR};
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case 0x8b: return {Immediate, Operation::ANE};
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case 0xab: return {Immediate, Operation::LXA};
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case 0xcb: return {Immediate, Operation::SBX};
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case 0xeb: return {Immediate, Operation::SBC};
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case 0x0c: return {Absolute, Operation::NOP};
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case 0x2c: return {Absolute, Operation::BIT};
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case 0x4c: return {JMPAbsolute, Operation::JMP};
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case 0x6c: return {JMPAbsoluteIndirect, Operation::JMP};
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case 0x8c: return {Absolute, Operation::STY};
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case 0xac: return {Absolute, Operation::LDY};
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case 0xcc: return {Absolute, Operation::CPY};
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case 0xec: return {Absolute, Operation::CPX};
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case 0x0d: return {Absolute, Operation::ORA};
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case 0x2d: return {Absolute, Operation::AND};
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case 0x4d: return {Absolute, Operation::EOR};
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case 0x6d: return {Absolute, Operation::ADC};
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case 0x8d: return {Absolute, Operation::STA};
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case 0xad: return {Absolute, Operation::LDA};
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case 0xcd: return {Absolute, Operation::CMP};
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case 0xed: return {Absolute, Operation::SBC};
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case 0x0e: return {Absolute, Operation::ASL};
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case 0x2e: return {Absolute, Operation::ROL};
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case 0x4e: return {Absolute, Operation::LSR};
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case 0x6e: return {Absolute, Operation::ROR};
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case 0x8e: return {Absolute, Operation::STX};
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case 0xae: return {Absolute, Operation::LDX};
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case 0xce: return {Absolute, Operation::DEC};
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case 0xee: return {Absolute, Operation::INC};
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case 0x0f: return {Absolute, Operation::ASO};
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case 0x2f: return {Absolute, Operation::RLA};
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case 0x4f: return {Absolute, Operation::LSE};
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case 0x6f: return {Absolute, Operation::RRA};
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case 0x8f: return {Absolute, Operation::SAX};
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case 0xaf: return {Absolute, Operation::LAX};
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case 0xcf: return {Absolute, Operation::DCP};
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case 0xef: return {Absolute, Operation::INS};
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case 0x10: return {Relative, Operation::BPL};
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case 0x30: return {Relative, Operation::BMI};
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case 0x50: return {Relative, Operation::BVC};
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case 0x70: return {Relative, Operation::BVS};
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case 0x90: return {Relative, Operation::BCC};
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case 0xb0: return {Relative, Operation::BCS};
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case 0xd0: return {Relative, Operation::BNE};
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case 0xf0: return {Relative, Operation::BEQ};
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case 0x11: return {IndirectIndexed, Operation::ORA};
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case 0x31: return {IndirectIndexed, Operation::AND};
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case 0x51: return {IndirectIndexed, Operation::EOR};
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case 0x71: return {IndirectIndexed, Operation::ADC};
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case 0x91: return {IndirectIndexed, Operation::STA};
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case 0xb1: return {IndirectIndexed, Operation::LDA};
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case 0xd1: return {IndirectIndexed, Operation::CMP};
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case 0xf1: return {IndirectIndexed, Operation::SBC};
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case 0x12: return {JAM, Operation::JAM};
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case 0x32: return {JAM, Operation::JAM};
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case 0x52: return {JAM, Operation::JAM};
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case 0x72: return {JAM, Operation::JAM};
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case 0x92: return {JAM, Operation::JAM};
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case 0xb2: return {JAM, Operation::JAM};
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case 0xd2: return {JAM, Operation::JAM};
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case 0xf2: return {JAM, Operation::JAM};
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case 0x13: return {IndirectIndexed, Operation::ASO};
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case 0x33: return {IndirectIndexed, Operation::RLA};
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case 0x53: return {IndirectIndexed, Operation::LSE};
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case 0x73: return {IndirectIndexed, Operation::RRA};
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case 0x93: return {SHxIndirectIndexed, Operation::SHA};
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case 0xb3: return {IndirectIndexed, Operation::LAX};
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case 0xd3: return {IndirectIndexed, Operation::DCP};
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case 0xf3: return {IndirectIndexed, Operation::INS};
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case 0x14: return {ZeroIndexed, Operation::NOP};
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case 0x34: return {ZeroIndexed, Operation::NOP};
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case 0x54: return {ZeroIndexed, Operation::NOP};
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case 0x74: return {ZeroIndexed, Operation::NOP};
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case 0x94: return {ZeroIndexed, Operation::STY};
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case 0xb4: return {ZeroIndexed, Operation::LDY};
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case 0xd4: return {ZeroIndexed, Operation::NOP};
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case 0xf4: return {ZeroIndexed, Operation::NOP};
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case 0x15: return {ZeroIndexed, Operation::ORA};
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case 0x35: return {ZeroIndexed, Operation::AND};
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case 0x55: return {ZeroIndexed, Operation::EOR};
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case 0x75: return {ZeroIndexed, Operation::ADC};
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case 0x95: return {ZeroIndexed, Operation::STA};
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case 0xb5: return {ZeroIndexed, Operation::LDA};
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case 0xd5: return {ZeroIndexed, Operation::CMP};
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case 0xf5: return {ZeroIndexed, Operation::SBC};
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case 0x16: return {ZeroIndexed, Operation::ASL};
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case 0x36: return {ZeroIndexed, Operation::ROL};
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case 0x56: return {ZeroIndexed, Operation::LSR};
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case 0x76: return {ZeroIndexed, Operation::ROR};
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case 0x96: return {ZeroIndexed, Operation::STX};
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case 0xb6: return {ZeroIndexed, Operation::LDX};
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case 0xd6: return {ZeroIndexed, Operation::DEC};
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case 0xf6: return {ZeroIndexed, Operation::INC};
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case 0x17: return {ZeroIndexed, Operation::ASO};
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case 0x37: return {ZeroIndexed, Operation::RLA};
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case 0x57: return {ZeroIndexed, Operation::LSE};
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case 0x77: return {ZeroIndexed, Operation::RRA};
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case 0x97: return {ZeroIndexed, Operation::SAX};
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case 0xb7: return {ZeroIndexed, Operation::LAX};
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case 0xd7: return {ZeroIndexed, Operation::DCP};
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case 0xf7: return {ZeroIndexed, Operation::INS};
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case 0x18: return {Implied, Operation::CLC};
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case 0x38: return {Implied, Operation::SEC};
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case 0x58: return {Implied, Operation::CLI};
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case 0x78: return {Implied, Operation::SEI};
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case 0x98: return {Implied, Operation::TYA};
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case 0xb8: return {Implied, Operation::CLV};
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case 0xd8: return {Implied, Operation::CLD};
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case 0xf8: return {Implied, Operation::SED};
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case 0x19: return {AbsoluteIndexed, Index::Y, Operation::ORA};
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case 0x39: return {AbsoluteIndexed, Index::Y, Operation::AND};
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case 0x59: return {AbsoluteIndexed, Index::Y, Operation::EOR};
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case 0x79: return {AbsoluteIndexed, Index::Y, Operation::ADC};
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case 0x99: return {AbsoluteIndexed, Index::Y, Operation::STA};
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case 0xb9: return {AbsoluteIndexed, Index::Y, Operation::LDA};
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case 0xd9: return {AbsoluteIndexed, Index::Y, Operation::CMP};
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case 0xf9: return {AbsoluteIndexed, Index::Y, Operation::SBC};
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case 0x1a: return {Implied, Operation::NOP};
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case 0x3a: return {Implied, Operation::NOP};
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case 0x5a: return {Implied, Operation::NOP};
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case 0x7a: return {Implied, Operation::NOP};
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case 0x9a: return {Implied, Operation::TXS};
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case 0xba: return {Implied, Operation::TSX};
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case 0xda: return {Implied, Operation::NOP};
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case 0xfa: return {Implied, Operation::NOP};
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case 0x1b: return {AbsoluteIndexed, Index::Y, Operation::ASO};
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case 0x3b: return {AbsoluteIndexed, Index::Y, Operation::RLA};
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case 0x5b: return {AbsoluteIndexed, Index::Y, Operation::LSE};
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case 0x7b: return {AbsoluteIndexed, Index::Y, Operation::RRA};
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case 0x9b: return {SHxAbsoluteXY, Operation::SHS};
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case 0xbb: return {AbsoluteIndexed, Index::Y, Operation::LAS};
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case 0xdb: return {AbsoluteIndexed, Index::Y, Operation::DCP};
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case 0xfb: return {AbsoluteIndexed, Index::Y, Operation::INS};
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case 0x1c: return {AbsoluteIndexed, Index::X, Operation::NOP};
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case 0x3c: return {AbsoluteIndexed, Index::X, Operation::NOP};
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case 0x5c: return {AbsoluteIndexed, Index::X, Operation::NOP};
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case 0x7c: return {AbsoluteIndexed, Index::X, Operation::NOP};
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case 0x9c: return {SHxAbsoluteXY, Operation::SHY};
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case 0xbc: return {AbsoluteIndexed, Index::X, Operation::LDY};
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|
case 0xdc: return {AbsoluteIndexed, Index::X, Operation::NOP};
|
|
case 0xfc: return {AbsoluteIndexed, Index::X, Operation::NOP};
|
|
|
|
case 0x1d: return {AbsoluteIndexed, Index::X, Operation::ORA};
|
|
case 0x3d: return {AbsoluteIndexed, Index::X, Operation::AND};
|
|
case 0x5d: return {AbsoluteIndexed, Index::X, Operation::EOR};
|
|
case 0x7d: return {AbsoluteIndexed, Index::X, Operation::ADC};
|
|
case 0x9d: return {AbsoluteIndexed, Index::X, Operation::STA};
|
|
case 0xbd: return {AbsoluteIndexed, Index::X, Operation::LDA};
|
|
case 0xdd: return {AbsoluteIndexed, Index::X, Operation::CMP};
|
|
case 0xfd: return {AbsoluteIndexed, Index::X, Operation::SBC};
|
|
|
|
case 0x1e: return {AbsoluteIndexed, Operation::ASL};
|
|
case 0x3e: return {AbsoluteIndexed, Operation::ROL};
|
|
case 0x5e: return {AbsoluteIndexed, Operation::LSR};
|
|
case 0x7e: return {AbsoluteIndexed, Operation::ROR};
|
|
case 0x9e: return {SHxAbsoluteXY, Operation::SHX};
|
|
case 0xbe: return {AbsoluteIndexed, Operation::LDX};
|
|
case 0xde: return {AbsoluteIndexed, Operation::DEC};
|
|
case 0xfe: return {AbsoluteIndexed, Operation::INC};
|
|
|
|
case 0x1f: return {AbsoluteIndexed, Operation::ASO};
|
|
case 0x3f: return {AbsoluteIndexed, Operation::RLA};
|
|
case 0x5f: return {AbsoluteIndexed, Operation::LSE};
|
|
case 0x7f: return {AbsoluteIndexed, Operation::RRA};
|
|
case 0x9f: return {SHxAbsoluteXY, Operation::SHA};
|
|
case 0xbf: return {AbsoluteIndexed, Operation::LAX};
|
|
case 0xdf: return {AbsoluteIndexed, Operation::DCP};
|
|
case 0xff: return {AbsoluteIndexed, Operation::INS};
|
|
}
|
|
|
|
__builtin_unreachable();
|
|
}
|
|
};
|
|
|
|
template <Model model>
|
|
struct Decoder<model, std::enable_if_t<model == Model::Synertek65C02>> {
|
|
static constexpr Instruction decode(const uint8_t opcode) {
|
|
using enum AddressingMode;
|
|
switch(opcode) {
|
|
default: return Decoder<Model::M6502>::decode(opcode);
|
|
|
|
case 0x80: return {Relative, Operation::BRA};
|
|
|
|
case 0x02: return {Immediate, Operation::NOP};
|
|
case 0x22: return {Immediate, Operation::NOP};
|
|
case 0x42: return {Immediate, Operation::NOP};
|
|
case 0x62: return {Immediate, Operation::NOP};
|
|
|
|
case 0x03: return {Implied, Operation::FastNOP};
|
|
case 0x23: return {Implied, Operation::FastNOP};
|
|
case 0x43: return {Implied, Operation::FastNOP};
|
|
case 0x63: return {Implied, Operation::FastNOP};
|
|
case 0x83: return {Implied, Operation::FastNOP};
|
|
case 0xa3: return {Implied, Operation::FastNOP};
|
|
case 0xc3: return {Implied, Operation::FastNOP};
|
|
case 0xe3: return {Implied, Operation::FastNOP};
|
|
|
|
case 0x04: return {Zero, Operation::TSB};
|
|
case 0x64: return {Zero, Operation::STZ};
|
|
case 0x9e: return {AbsoluteIndexed, Operation::STZ};
|
|
|
|
case 0x07: return {Zero, Operation::NOP};
|
|
case 0x27: return {Zero, Operation::NOP};
|
|
case 0x47: return {Zero, Operation::NOP};
|
|
case 0x67: return {Zero, Operation::NOP};
|
|
case 0x87: return {Zero, Operation::NOP};
|
|
case 0xa7: return {Zero, Operation::NOP};
|
|
case 0xc7: return {Zero, Operation::NOP};
|
|
case 0xe7: return {Zero, Operation::NOP};
|
|
|
|
case 0x89: return {Immediate, Operation::BITNoNV};
|
|
|
|
case 0x0b: return {Implied, Operation::FastNOP};
|
|
case 0x2b: return {Implied, Operation::FastNOP};
|
|
case 0x4b: return {Implied, Operation::FastNOP};
|
|
case 0x6b: return {Implied, Operation::FastNOP};
|
|
case 0x8b: return {Implied, Operation::FastNOP};
|
|
case 0xab: return {Implied, Operation::FastNOP};
|
|
case 0xcb: return {Implied, Operation::FastNOP};
|
|
case 0xeb: return {Implied, Operation::FastNOP};
|
|
|
|
case 0x0c: return {Absolute, Operation::TSB};
|
|
|
|
case 0x0f: return {Absolute, Operation::FastNOP};
|
|
case 0x2f: return {Absolute, Operation::FastNOP};
|
|
case 0x4f: return {Absolute, Operation::FastNOP};
|
|
case 0x6f: return {Absolute, Operation::FastNOP};
|
|
case 0x8f: return {Absolute, Operation::FastNOP};
|
|
case 0xaf: return {Absolute, Operation::FastNOP};
|
|
case 0xcf: return {Absolute, Operation::FastNOP};
|
|
case 0xef: return {Absolute, Operation::FastNOP};
|
|
|
|
case 0x12: return {ZeroIndirect, Operation::ORA};
|
|
case 0x32: return {ZeroIndirect, Operation::AND};
|
|
case 0x52: return {ZeroIndirect, Operation::EOR};
|
|
case 0x72: return {ZeroIndirect, Operation::ADC};
|
|
case 0x92: return {ZeroIndirect, Operation::STA};
|
|
case 0xb2: return {ZeroIndirect, Operation::LDA};
|
|
case 0xd2: return {ZeroIndirect, Operation::CMP};
|
|
case 0xf2: return {ZeroIndirect, Operation::SBC};
|
|
|
|
case 0x13: return {Implied, Operation::FastNOP};
|
|
case 0x33: return {Implied, Operation::FastNOP};
|
|
case 0x53: return {Implied, Operation::FastNOP};
|
|
case 0x73: return {Implied, Operation::FastNOP};
|
|
case 0x93: return {Implied, Operation::FastNOP};
|
|
case 0xb3: return {Implied, Operation::FastNOP};
|
|
case 0xd3: return {Implied, Operation::FastNOP};
|
|
case 0xf3: return {Implied, Operation::FastNOP};
|
|
|
|
case 0x14: return {Zero, Operation::TRB};
|
|
case 0x34: return {ZeroIndexed, Operation::BIT};
|
|
case 0x74: return {ZeroIndexed, Operation::STZ};
|
|
|
|
case 0x17: return {ZeroIndexed, Operation::NOP};
|
|
case 0x37: return {ZeroIndexed, Operation::NOP};
|
|
case 0x57: return {ZeroIndexed, Operation::NOP};
|
|
case 0x77: return {ZeroIndexed, Operation::NOP};
|
|
case 0x97: return {ZeroIndexed, Operation::NOP};
|
|
case 0xb7: return {ZeroIndexed, Operation::NOP};
|
|
case 0xd7: return {ZeroIndexed, Operation::NOP};
|
|
case 0xf7: return {ZeroIndexed, Operation::NOP};
|
|
|
|
case 0x1a: return {Implied, Operation::INA};
|
|
case 0x3a: return {Implied, Operation::DEA};
|
|
case 0x5a: return {Push, Operation::STY};
|
|
case 0x7a: return {Pull, Operation::LDY};
|
|
case 0xda: return {Push, Operation::STX};
|
|
case 0xfa: return {Pull, Operation::LDX};
|
|
|
|
case 0x1b: return {Implied, Operation::FastNOP};
|
|
case 0x3b: return {Implied, Operation::FastNOP};
|
|
case 0x5b: return {Implied, Operation::FastNOP};
|
|
case 0x7b: return {Implied, Operation::FastNOP};
|
|
case 0x9b: return {Implied, Operation::FastNOP};
|
|
case 0xbb: return {Implied, Operation::FastNOP};
|
|
case 0xdb: return {ZeroIndexed, Operation::NOP};
|
|
case 0xfb: return {Implied, Operation::FastNOP};
|
|
|
|
case 0x1c: return {Absolute, Operation::TRB};
|
|
case 0x3c: return {AbsoluteIndexed, Operation::BIT};
|
|
case 0x5c: return {AbsoluteIndexed, Operation::FastNOP};
|
|
case 0x7c: return {JMPAbsoluteIndexedIndirect, Operation::JMP};
|
|
case 0x9c: return {Absolute, Operation::STZ};
|
|
|
|
case 0x1e: return {FastAbsoluteIndexedModify, Operation::ASL};
|
|
case 0x3e: return {FastAbsoluteIndexedModify, Operation::ROL};
|
|
case 0x5e: return {FastAbsoluteIndexedModify, Operation::LSR};
|
|
case 0x7e: return {FastAbsoluteIndexedModify, Operation::ROR};
|
|
|
|
case 0x1f: return {AbsoluteIndexed, Operation::FastNOP};
|
|
case 0x3f: return {AbsoluteIndexed, Operation::FastNOP};
|
|
case 0x5f: return {AbsoluteIndexed, Operation::FastNOP};
|
|
case 0x7f: return {AbsoluteIndexed, Operation::FastNOP};
|
|
case 0x9f: return {AbsoluteIndexed, Operation::FastNOP};
|
|
case 0xbf: return {AbsoluteIndexed, Operation::FastNOP};
|
|
case 0xdf: return {AbsoluteIndexed, Operation::FastNOP};
|
|
case 0xff: return {AbsoluteIndexed, Operation::FastNOP};
|
|
}
|
|
}
|
|
};
|
|
|
|
template <Model model>
|
|
struct Decoder<model, std::enable_if_t<model == Model::Rockwell65C02>> {
|
|
static constexpr Instruction decode(const uint8_t opcode) {
|
|
using enum AddressingMode;
|
|
switch(opcode) {
|
|
default: return Decoder<Model::Synertek65C02>::decode(opcode);
|
|
|
|
case 0x0f: return {BBRBBS, Operation::BBRBBS};
|
|
case 0x2f: return {BBRBBS, Operation::BBRBBS};
|
|
case 0x4f: return {BBRBBS, Operation::BBRBBS};
|
|
case 0x6f: return {BBRBBS, Operation::BBRBBS};
|
|
case 0x8f: return {BBRBBS, Operation::BBRBBS};
|
|
case 0xaf: return {BBRBBS, Operation::BBRBBS};
|
|
case 0xcf: return {BBRBBS, Operation::BBRBBS};
|
|
case 0xef: return {BBRBBS, Operation::BBRBBS};
|
|
|
|
case 0x1f: return {BBRBBS, Operation::BBRBBS};
|
|
case 0x3f: return {BBRBBS, Operation::BBRBBS};
|
|
case 0x5f: return {BBRBBS, Operation::BBRBBS};
|
|
case 0x7f: return {BBRBBS, Operation::BBRBBS};
|
|
case 0x9f: return {BBRBBS, Operation::BBRBBS};
|
|
case 0xbf: return {BBRBBS, Operation::BBRBBS};
|
|
case 0xdf: return {BBRBBS, Operation::BBRBBS};
|
|
case 0xff: return {BBRBBS, Operation::BBRBBS};
|
|
}
|
|
}
|
|
};
|
|
|
|
template <Model model>
|
|
struct Decoder<model, std::enable_if_t<model == Model::WDC65C02>> {
|
|
static constexpr Instruction decode(const uint8_t opcode) {
|
|
using enum AddressingMode;
|
|
switch(opcode) {
|
|
default: return Decoder<Model::Rockwell65C02>::decode(opcode);
|
|
case 0xdb: return {STP, Operation::STP};
|
|
case 0xcb: return {WAI, Operation::WAI};
|
|
}
|
|
}
|
|
};
|
|
|
|
}
|