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491 lines
15 KiB
C++
491 lines
15 KiB
C++
//
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// MemoryController.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 20/03/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "InputOutputController.hpp"
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#include "Video.hpp"
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#include "Sound.hpp"
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#include "../../../InstructionSets/ARM/Registers.hpp"
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#include "../../../Outputs/Log.hpp"
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#include "../../../Activity/Observer.hpp"
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namespace Archimedes {
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/// Provides the mask with all bits set in the range [start, end], where start must be >= end.
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template <int start, int end> struct BitMask {
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static_assert(start >= end);
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static constexpr uint32_t value = ((1 << (start + 1)) - 1) - ((1 << end) - 1);
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};
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static_assert(BitMask<0, 0>::value == 1);
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static_assert(BitMask<1, 1>::value == 2);
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static_assert(BitMask<15, 15>::value == 32768);
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static_assert(BitMask<15, 0>::value == 0xffff);
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static_assert(BitMask<15, 14>::value == 49152);
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/// Models the MEMC, making this the Archimedes bus. Owns various other chips on the bus as a result.
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template <typename InterruptObserverT, typename ClockRateObserverT>
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struct MemoryController {
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MemoryController(InterruptObserverT &observer, ClockRateObserverT &clock_rate_observer) :
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ioc_(observer, clock_rate_observer, ram_.data()) {
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read_zones_[0] = Zone::HighROM; // Temporarily put high ROM at address 0.
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// TODO: could I just copy it in? Or, at least,
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// could I detect at ROM loading time whether I can?
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}
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int interrupt_mask() const {
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return ioc_.interrupt_mask();
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}
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void set_rom(const std::vector<uint8_t> &rom) {
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if(rom_.size() % rom.size() || rom.size() > rom_.size()) {
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// TODO: throw.
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return;
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}
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// Copy in as many times as it'll fit.
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std::size_t base = 0;
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while(base < rom_.size()) {
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std::copy(
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rom.begin(),
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rom.end(),
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rom_.begin() + base);
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base += rom.size();
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}
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}
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template <typename IntT>
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uint32_t aligned(uint32_t address) {
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if constexpr (std::is_same_v<IntT, uint32_t>) {
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return address & static_cast<uint32_t>(~3);
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}
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return address;
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}
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template <typename IntT>
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bool write(uint32_t address, IntT source, InstructionSet::ARM::Mode, bool trans) {
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switch(write_zones_[(address >> 21) & 31]) {
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case Zone::DMAAndMEMC: {
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if(trans) return false;
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const auto buffer_address = [](uint32_t source) -> uint32_t {
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return (source & 0x1'fffc) << 2;
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};
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// The MEMC itself isn't on the data bus; all values below should be taken from `address`.
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switch((address >> 17) & 0b111) {
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case 0b000: ioc_.video().set_frame_start(buffer_address(address)); break;
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case 0b001: ioc_.video().set_buffer_start(buffer_address(address)); break;
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case 0b010: ioc_.video().set_buffer_end(buffer_address(address)); break;
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case 0b011: ioc_.video().set_cursor_start(buffer_address(address)); break;
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case 0b100: ioc_.sound().set_next_start(buffer_address(address)); break;
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case 0b101: ioc_.sound().set_next_end(buffer_address(address)); break;
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case 0b110: ioc_.sound().swap(); break;
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case 0b111:
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os_mode_ = address & (1 << 12);
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sound_dma_enable_ = address & (1 << 11);
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ioc_.sound().set_dma_enabled(sound_dma_enable_);
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video_dma_enable_ = address & (1 << 10);
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switch((address >> 8) & 3) {
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default:
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dynamic_ram_refresh_ = DynamicRAMRefresh::None;
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break;
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case 0b01:
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case 0b11:
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dynamic_ram_refresh_ = DynamicRAMRefresh((address >> 8) & 3);
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break;
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}
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high_rom_access_time_ = ROMAccessTime((address >> 6) & 3);
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low_rom_access_time_ = ROMAccessTime((address >> 4) & 3);
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page_size_ = PageSize((address >> 2) & 3);
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switch(page_size_) {
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default:
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case PageSize::kb4:
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page_address_shift_ = 12;
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page_adddress_mask_ = 0x0fff;
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break;
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case PageSize::kb8:
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page_address_shift_ = 13;
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page_adddress_mask_ = 0x1fff;
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break;
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case PageSize::kb16:
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page_address_shift_ = 14;
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page_adddress_mask_ = 0x3fff;
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break;
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case PageSize::kb32:
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page_address_shift_ = 15;
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page_adddress_mask_ = 0x7fff;
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break;
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}
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logger.info().append("MEMC Control: %08x -> OS:%d sound:%d video:%d refresh:%d high:%d low:%d size:%d", address, os_mode_, sound_dma_enable_, video_dma_enable_, dynamic_ram_refresh_, high_rom_access_time_, low_rom_access_time_, page_size_);
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map_dirty_ = true;
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break;
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}
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} break;
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case Zone::LogicallyMappedRAM: {
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const auto item = logical_ram<IntT, false>(address, trans);
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if(!item) {
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return false;
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}
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*item = source;
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} break;
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case Zone::IOControllers:
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if(trans) return false;
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ioc_.template write<IntT>(address, source);
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break;
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case Zone::VideoController:
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if(trans) return false;
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// TODO: handle byte writes correctly.
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ioc_.video().write(source);
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break;
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case Zone::PhysicallyMappedRAM:
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if(trans) return false;
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physical_ram<IntT>(address) = source;
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break;
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case Zone::AddressTranslator:
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if(trans) return false;
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// printf("Translator write at %08x; replaces %08x\n", address, pages_[address & 0x7f]);
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pages_[address & 0x7f] = address;
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map_dirty_ = true;
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break;
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default:
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printf("TODO: write of %08x to %08x [%lu]\n", source, address, sizeof(IntT));
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break;
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}
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return true;
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}
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template <typename IntT>
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bool read(uint32_t address, IntT &source, InstructionSet::ARM::Mode, bool trans) {
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switch (read_zones_[(address >> 21) & 31]) {
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case Zone::PhysicallyMappedRAM:
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if(trans) return false;
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source = physical_ram<IntT>(address);
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break;
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case Zone::LogicallyMappedRAM: {
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const auto item = logical_ram<IntT, true>(address, trans);
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if(!item) {
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return false;
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}
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source = *item;
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} break;
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case Zone::LowROM:
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// logger.error().append("TODO: Low ROM read from %08x", address);
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source = IntT(~0);
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break;
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case Zone::HighROM:
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// Real test is: require A24=A25=0, then A25=1.
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read_zones_[0] = Zone::LogicallyMappedRAM;
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source = high_rom<IntT>(address);
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break;
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case Zone::IOControllers:
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if(trans) return false;
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ioc_.template read<IntT>(address, source);
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break;
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default:
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logger.error().append("TODO: read from %08x", address);
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break;
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}
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return true;
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}
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//
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// Expose various IOC-owned things.
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//
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void tick_timers() { ioc_.tick_timers(); }
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void tick_floppy() { ioc_.tick_floppy(); }
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void set_disk(std::shared_ptr<Storage::Disk::Disk> disk, size_t drive) {
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ioc_.set_disk(disk, drive);
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}
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Outputs::Speaker::Speaker *speaker() {
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return ioc_.sound().speaker();
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}
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auto &sound() { return ioc_.sound(); }
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const auto &sound() const { return ioc_.sound(); }
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auto &video() { return ioc_.video(); }
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const auto &video() const { return ioc_.video(); }
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auto &keyboard() { return ioc_.keyboard(); }
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const auto &keyboard() const { return ioc_.keyboard(); }
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void set_activity_observer(Activity::Observer *observer) {
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ioc_.set_activity_observer(observer);
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}
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private:
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Log::Logger<Log::Source::ARMIOC> logger;
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enum class Zone {
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LogicallyMappedRAM,
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PhysicallyMappedRAM,
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IOControllers,
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LowROM,
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HighROM,
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VideoController,
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DMAAndMEMC,
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AddressTranslator,
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};
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static std::array<Zone, 0x20> zones(bool is_read) {
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std::array<Zone, 0x20> zones{};
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for(size_t c = 0; c < zones.size(); c++) {
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const auto address = c << 21;
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if(address < 0x200'0000) {
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zones[c] = Zone::LogicallyMappedRAM;
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} else if(address < 0x300'0000) {
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zones[c] = Zone::PhysicallyMappedRAM;
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} else if(address < 0x340'0000) {
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zones[c] = Zone::IOControllers;
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} else if(address < 0x360'0000) {
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zones[c] = is_read ? Zone::LowROM : Zone::VideoController;
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} else if(address < 0x380'0000) {
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zones[c] = is_read ? Zone::LowROM : Zone::DMAAndMEMC;
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} else {
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zones[c] = is_read ? Zone::HighROM : Zone::AddressTranslator;
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}
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}
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return zones;
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}
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bool has_moved_rom_ = false;
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std::array<uint8_t, 4*1024*1024> ram_{};
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std::array<uint8_t, 2*1024*1024> rom_;
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InputOutputController<InterruptObserverT, ClockRateObserverT> ioc_;
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template <typename IntT>
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IntT &physical_ram(uint32_t address) {
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address = aligned<IntT>(address);
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address &= (ram_.size() - 1);
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return *reinterpret_cast<IntT *>(&ram_[address]);
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}
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template <typename IntT>
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IntT &high_rom(uint32_t address) {
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address = aligned<IntT>(address);
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return *reinterpret_cast<IntT *>(&rom_[address & (rom_.size() - 1)]);
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}
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std::array<Zone, 0x20> read_zones_ = zones(true);
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const std::array<Zone, 0x20> write_zones_ = zones(false);
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// Control register values.
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bool os_mode_ = false;
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bool sound_dma_enable_ = false;
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bool video_dma_enable_ = false; // "Unaffected" by reset, so here picked arbitrarily.
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enum class DynamicRAMRefresh {
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None = 0b00,
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DuringFlyback = 0b01,
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Continuous = 0b11,
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} dynamic_ram_refresh_ = DynamicRAMRefresh::None; // State at reset is undefined; constrain to a valid enum value.
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enum class ROMAccessTime {
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ns450 = 0b00,
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ns325 = 0b01,
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ns200 = 0b10,
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ns200with60nsNibble = 0b11,
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} high_rom_access_time_ = ROMAccessTime::ns450, low_rom_access_time_ = ROMAccessTime::ns450;
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enum class PageSize {
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kb4 = 0b00,
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kb8 = 0b01,
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kb16 = 0b10,
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kb32 = 0b11,
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} page_size_ = PageSize::kb4;
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int page_address_shift_ = 12;
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uint32_t page_adddress_mask_ = 0xffff;
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// Address translator.
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//
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// MEMC contains one entry per a physical page number, indicating where it goes logically.
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// Any logical access is tested against all 128 mappings. So that's backwards compared to
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// the ideal for an emulator, which would map from logical to physical, even if a lot more
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// compact — there are always 128 physical pages; there are up to 8192 logical pages.
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//
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// So captured here are both the physical -> logical map as representative of the real
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// hardware, and the reverse logical -> physical map, which is built (and rebuilt, and rebuilt)
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// from the other.
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// Physical to logical mapping.
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std::array<uint32_t, 128> pages_{};
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// Logical to physical mapping; this is divided by 'access mode'
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// (i.e. the combination of read/write, trans and OS mode flags,
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// as multipliexed by the @c mapping() function) because mapping
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// varies by mode — not just in terms of restricting access, but
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// actually presenting different memory.
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using MapTarget = std::array<uint8_t *, 8192>;
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std::array<MapTarget, 6> mapping_;
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template <bool is_read>
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MapTarget &mapping(bool trans, bool os_mode) {
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const size_t index = (is_read ? 1 : 0) | (os_mode ? 2 : 0) | ((trans && !os_mode) ? 4 : 0);
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return mapping_[index];
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}
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bool map_dirty_ = true;
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template <typename IntT, bool is_read>
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IntT *logical_ram(uint32_t address, bool trans) {
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// Possibly TODO: this recompute-if-dirty flag is supposed to ameliorate for an expensive
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// mapping process. It can be eliminated when the process is improved.
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if(map_dirty_) {
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update_mapping();
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map_dirty_ = false;
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}
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address = aligned<IntT>(address);
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address &= 0x1ff'ffff;
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const size_t page = address >> page_address_shift_;
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const auto &map = mapping<is_read>(trans, os_mode_);
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if(!map[page]) {
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return nullptr;
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}
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address &= page_adddress_mask_;
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return reinterpret_cast<IntT *>(&map[page][address]);
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}
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void update_mapping() {
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// For each physical page, project it into logical space.
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switch(page_size_) {
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default:
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case PageSize::kb4: update_mapping<PageSize::kb4>(); break;
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case PageSize::kb8: update_mapping<PageSize::kb8>(); break;
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case PageSize::kb16: update_mapping<PageSize::kb16>(); break;
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case PageSize::kb32: update_mapping<PageSize::kb32>(); break;
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}
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}
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template <PageSize size>
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void update_mapping() {
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// Clear all logical mappings.
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for(auto &map: mapping_) {
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std::fill(map.begin(), map.end(), nullptr);
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}
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// For each physical page, project it into logical space
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// and store it.
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for(const auto page: pages_) {
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uint32_t physical, logical;
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switch(size) {
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case PageSize::kb4:
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// 4kb:
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// A[6:0] -> PPN[6:0]
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// A[11:10] -> LPN[12:11]; A[22:12] -> LPN[10:0] i.e. 8192 logical pages
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physical = page & BitMask<6, 0>::value;
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physical <<= 12;
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logical = (page & BitMask<11, 10>::value) << 1;
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logical |= (page & BitMask<22, 12>::value) >> 12;
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break;
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case PageSize::kb8:
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// 8kb:
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// A[0] -> PPN[6]; A[6:1] -> PPN[5:0]
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// A[11:10] -> LPN[11:10]; A[22:13] -> LPN[9:0] i.e. 4096 logical pages
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physical = (page & BitMask<0, 0>::value) << 6;
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physical |= (page & BitMask<6, 1>::value) >> 1;
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physical <<= 13;
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logical = page & BitMask<11, 10>::value;
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logical |= (page & BitMask<22, 13>::value) >> 13;
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break;
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case PageSize::kb16:
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// 16kb:
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// A[1:0] -> PPN[6:5]; A[6:2] -> PPN[4:0]
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// A[11:10] -> LPN[10:9]; A[22:14] -> LPN[8:0] i.e. 2048 logical pages
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physical = (page & BitMask<1, 0>::value) << 5;
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physical |= (page & BitMask<6, 2>::value) >> 2;
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physical <<= 14;
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logical = (page & BitMask<11, 10>::value) >> 1;
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logical |= (page & BitMask<22, 14>::value) >> 14;
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break;
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case PageSize::kb32:
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// 32kb:
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// A[1] -> PPN[6]; A[2] -> PPN[5]; A[0] -> PPN[4]; A[6:3] -> PPN[3:0]
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// A[11:10] -> LPN[9:8]; A[22:15] -> LPN[7:0] i.e. 1024 logical pages
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physical = (page & BitMask<1, 1>::value) << 5;
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physical |= (page & BitMask<2, 2>::value) << 3;
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physical |= (page & BitMask<0, 0>::value) << 4;
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physical |= (page & BitMask<6, 3>::value) >> 3;
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physical <<= 15;
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logical = (page & BitMask<11, 10>::value) >> 2;
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logical |= (page & BitMask<22, 15>::value) >> 15;
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break;
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}
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// printf("%08x => physical %d -> logical %d\n", page, (physical >> 15), logical);
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// TODO: consider clashes.
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// TODO: what if there's less than 4mb present?
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const auto target = &ram_[physical];
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const auto set_supervisor = [&](bool read, bool write) {
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if(read) mapping<true>(false, false)[logical] = target;
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if(write) mapping<false>(false, false)[logical] = target;
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};
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const auto set_os = [&](bool read, bool write) {
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if(read) mapping<true>(true, true)[logical] = target;
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if(write) mapping<false>(true, true)[logical] = target;
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};
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const auto set_user = [&](bool read, bool write) {
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if(read) mapping<true>(true, false)[logical] = target;
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if(write) mapping<false>(true, false)[logical] = target;
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};
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set_supervisor(true, true);
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switch((page >> 8) & 3) {
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case 0b00:
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set_os(true, true);
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set_user(true, true);
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break;
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case 0b01:
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set_os(true, true);
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set_user(true, false);
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break;
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default:
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set_os(true, false);
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set_user(false, false);
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break;
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}
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}
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}
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};
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}
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