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https://github.com/TomHarte/CLK.git
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694 lines
20 KiB
C++
694 lines
20 KiB
C++
//
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// PCCompatible.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 15/11/2023.
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// Copyright © 2023 Thomas Harte. All rights reserved.
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//
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#include "PCCompatible.hpp"
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#include "../../InstructionSets/x86/Decoder.hpp"
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#include "../../InstructionSets/x86/Flags.hpp"
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#include "../../InstructionSets/x86/Instruction.hpp"
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#include "../../InstructionSets/x86/Perform.hpp"
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#include "../ScanProducer.hpp"
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#include "../TimedMachine.hpp"
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#include <array>
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namespace PCCompatible {
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template <bool is_8254>
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class PIT {
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public:
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template <int channel> uint8_t read() {
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return channels_[channel].read();
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}
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template <int channel> void write(uint8_t value) {
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printf("Write to %d\n", channel);
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channels_[channel].write(value);
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}
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void set_mode(uint8_t value) {
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const int channel_id = (value >> 6) & 3;
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if(channel_id == 3) {
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read_back_ = is_8254;
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// TODO: decode rest of read-back command.
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return;
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}
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Channel &channel = channels_[channel_id];
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channel.is_bcd = value & 1;
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switch((value >> 1) & 3) {
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default: channel.latch_value(); break;
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case 1: channel.latch_mode = LatchMode::LowOnly; break;
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case 2: channel.latch_mode = LatchMode::HighOnly; break;
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case 3: channel.latch_mode = LatchMode::LowHigh; break;
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}
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channel.next_write_high = false;
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const auto operating_mode = (value >> 3) & 7;
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switch(operating_mode) {
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default: channel.mode = OperatingMode(operating_mode); break;
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case 6: channel.mode = OperatingMode::RateGenerator; break;
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case 7: channel.mode = OperatingMode::SquareWaveGenerator; break;
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}
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printf("%d switches to mode %d\n", channel_id, int(channel.mode));
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// Set up operating mode.
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switch(channel.mode) {
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case OperatingMode::InterruptOnTerminalCount:
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channel.output = false;
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channel.awaiting_reload = true;
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break;
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case OperatingMode::RateGenerator:
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channel.output = true;
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channel.awaiting_reload = true;
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break;
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}
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}
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void run_for(Cycles cycles) {
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// TODO: be intelligent enough to take ticks outside the loop when appropriate.
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auto ticks = cycles.as<int>();
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while(ticks--) {
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bool output_changed;
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output_changed = channels_[0].advance(1);
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output_changed |= channels_[1].advance(1);
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output_changed |= channels_[2].advance(1);
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}
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}
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private:
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// Supported only on 8254s.
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bool read_back_ = false;
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enum class LatchMode {
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LowOnly,
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HighOnly,
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LowHigh,
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};
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enum class OperatingMode {
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InterruptOnTerminalCount = 0,
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HardwareRetriggerableOneShot = 1,
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RateGenerator = 2,
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SquareWaveGenerator = 3,
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SoftwareTriggeredStrobe = 4,
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HardwareTriggeredStrobe = 5,
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};
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struct Channel {
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LatchMode latch_mode = LatchMode::LowHigh;
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OperatingMode mode = OperatingMode::InterruptOnTerminalCount;
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bool is_bcd = false;
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bool gated = false;
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bool awaiting_reload = true;
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uint16_t counter = 0;
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uint16_t reload = 0;
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uint16_t latch = 0;
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bool output = false;
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bool next_write_high = false;
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void latch_value() {
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latch = counter;
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}
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bool advance(int ticks) {
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if(gated || awaiting_reload) return false;
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// TODO: BCD mode is completely ignored below. Possibly not too important.
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const bool initial_output = output;
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switch(mode) {
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case OperatingMode::InterruptOnTerminalCount:
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// Output goes permanently high upon a tick from 1 to 0; reload value is not used on wraparound.
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output |= counter <= ticks;
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counter -= ticks;
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break;
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case OperatingMode::RateGenerator:
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// Output goes low upon a tick from 2 to 1. It goes high again on 1 to 0, and the reload value is used.
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if(counter <= ticks) {
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counter = reload - ticks + counter;
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} else {
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counter -= ticks;
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}
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output = counter != 1;
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break;
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default:
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// TODO.
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break;
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}
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return output != initial_output;
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}
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void write(uint8_t value) {
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switch(latch_mode) {
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case LatchMode::LowOnly:
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reload = (reload & 0xff00) | value;
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break;
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case LatchMode::HighOnly:
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reload = (reload & 0x00ff) | (value << 8);
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break;
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case LatchMode::LowHigh:
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if(!next_write_high) {
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reload = (reload & 0xff00) | value;
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next_write_high = true;
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return;
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}
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reload = (reload & 0x00ff) | (value << 8);
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next_write_high = false;
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break;
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}
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awaiting_reload = false;
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switch(mode) {
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case OperatingMode::InterruptOnTerminalCount:
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case OperatingMode::RateGenerator:
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counter = reload;
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break;
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}
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}
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uint8_t read() {
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switch(latch_mode) {
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case LatchMode::LowOnly: return uint8_t(latch);
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case LatchMode::HighOnly: return uint8_t(latch >> 8);
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default:
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case LatchMode::LowHigh:
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next_write_high ^= true;
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return next_write_high ? uint8_t(latch) : uint8_t(latch >> 8);
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break;
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}
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}
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} channels_[3];
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// TODO:
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//
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// channel 0 is connected to IRQ 0;
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// channel 1 is used for DRAM refresh;
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// channel 2 is gated by a PPI output and feeds into the speaker.
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//
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// RateGenerator: output goes high if gated.
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};
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struct Registers {
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public:
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static constexpr bool is_32bit = false;
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uint8_t &al() { return ax_.halves.low; }
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uint8_t &ah() { return ax_.halves.high; }
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uint16_t &ax() { return ax_.full; }
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CPU::RegisterPair16 &axp() { return ax_; }
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uint8_t &cl() { return cx_.halves.low; }
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uint8_t &ch() { return cx_.halves.high; }
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uint16_t &cx() { return cx_.full; }
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uint8_t &dl() { return dx_.halves.low; }
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uint8_t &dh() { return dx_.halves.high; }
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uint16_t &dx() { return dx_.full; }
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uint8_t &bl() { return bx_.halves.low; }
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uint8_t &bh() { return bx_.halves.high; }
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uint16_t &bx() { return bx_.full; }
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uint16_t &sp() { return sp_; }
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uint16_t &bp() { return bp_; }
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uint16_t &si() { return si_; }
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uint16_t &di() { return di_; }
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uint16_t &ip() { return ip_; }
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uint16_t &es() { return es_; }
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uint16_t &cs() { return cs_; }
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uint16_t &ds() { return ds_; }
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uint16_t &ss() { return ss_; }
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uint16_t es() const { return es_; }
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uint16_t cs() const { return cs_; }
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uint16_t ds() const { return ds_; }
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uint16_t ss() const { return ss_; }
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void reset() {
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cs_ = 0xffff;
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ip_ = 0;
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}
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private:
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CPU::RegisterPair16 ax_;
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CPU::RegisterPair16 cx_;
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CPU::RegisterPair16 dx_;
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CPU::RegisterPair16 bx_;
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uint16_t sp_;
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uint16_t bp_;
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uint16_t si_;
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uint16_t di_;
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uint16_t es_, cs_, ds_, ss_;
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uint16_t ip_;
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};
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class Segments {
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public:
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Segments(const Registers ®isters) : registers_(registers) {}
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using Source = InstructionSet::x86::Source;
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/// Posted by @c perform after any operation which *might* have affected a segment register.
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void did_update(Source segment) {
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switch(segment) {
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default: break;
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case Source::ES: es_base_ = uint32_t(registers_.es()) << 4; break;
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case Source::CS: cs_base_ = uint32_t(registers_.cs()) << 4; break;
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case Source::DS: ds_base_ = uint32_t(registers_.ds()) << 4; break;
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case Source::SS: ss_base_ = uint32_t(registers_.ss()) << 4; break;
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}
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}
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void reset() {
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did_update(Source::ES);
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did_update(Source::CS);
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did_update(Source::DS);
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did_update(Source::SS);
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}
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uint32_t es_base_, cs_base_, ds_base_, ss_base_;
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bool operator ==(const Segments &rhs) const {
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return
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es_base_ == rhs.es_base_ &&
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cs_base_ == rhs.cs_base_ &&
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ds_base_ == rhs.ds_base_ &&
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ss_base_ == rhs.ss_base_;
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}
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private:
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const Registers ®isters_;
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};
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// TODO: send writes to the ROM area off to nowhere.
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struct Memory {
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public:
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using AccessType = InstructionSet::x86::AccessType;
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// Constructor.
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Memory(Registers ®isters, const Segments &segments) : registers_(registers), segments_(segments) {}
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//
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// Preauthorisation call-ins. Since only an 8088 is currently modelled, all accesses are implicitly authorised.
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//
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void preauthorise_stack_write([[maybe_unused]] uint32_t length) {}
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void preauthorise_stack_read([[maybe_unused]] uint32_t length) {}
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void preauthorise_read([[maybe_unused]] InstructionSet::x86::Source segment, [[maybe_unused]] uint16_t start, [[maybe_unused]] uint32_t length) {}
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void preauthorise_read([[maybe_unused]] uint32_t start, [[maybe_unused]] uint32_t length) {}
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//
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// Access call-ins.
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//
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// Accesses an address based on segment:offset.
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template <typename IntT, AccessType type>
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typename InstructionSet::x86::Accessor<IntT, type>::type access(InstructionSet::x86::Source segment, uint16_t offset) {
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const uint32_t physical_address = address(segment, offset);
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if constexpr (std::is_same_v<IntT, uint16_t>) {
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// If this is a 16-bit access that runs past the end of the segment, it'll wrap back
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// to the start. So the 16-bit value will need to be a local cache.
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if(offset == 0xffff) {
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return split_word<type>(physical_address, address(segment, 0));
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}
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}
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return access<IntT, type>(physical_address);
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}
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// Accesses an address based on physical location.
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template <typename IntT, AccessType type>
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typename InstructionSet::x86::Accessor<IntT, type>::type access(uint32_t address) {
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// Dispense with the single-byte case trivially.
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if constexpr (std::is_same_v<IntT, uint8_t>) {
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return memory[address];
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} else if(address != 0xf'ffff) {
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return *reinterpret_cast<IntT *>(&memory[address]);
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} else {
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return split_word<type>(address, 0);
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}
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}
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template <typename IntT>
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void write_back() {
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if constexpr (std::is_same_v<IntT, uint16_t>) {
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if(write_back_address_[0] != NoWriteBack) {
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memory[write_back_address_[0]] = write_back_value_ & 0xff;
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memory[write_back_address_[1]] = write_back_value_ >> 8;
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write_back_address_[0] = 0;
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}
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}
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}
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//
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// Direct write.
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//
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template <typename IntT>
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void preauthorised_write(InstructionSet::x86::Source segment, uint16_t offset, IntT value) {
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// Bytes can be written without further ado.
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if constexpr (std::is_same_v<IntT, uint8_t>) {
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memory[address(segment, offset) & 0xf'ffff] = value;
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return;
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}
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// Words that straddle the segment end must be split in two.
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if(offset == 0xffff) {
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memory[address(segment, offset) & 0xf'ffff] = value & 0xff;
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memory[address(segment, 0x0000) & 0xf'ffff] = value >> 8;
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return;
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}
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const uint32_t target = address(segment, offset) & 0xf'ffff;
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// Words that straddle the end of physical RAM must also be split in two.
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if(target == 0xf'ffff) {
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memory[0xf'ffff] = value & 0xff;
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memory[0x0'0000] = value >> 8;
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return;
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}
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// It's safe just to write then.
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*reinterpret_cast<uint16_t *>(&memory[target]) = value;
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}
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//
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// Helper for instruction fetch.
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//
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std::pair<const uint8_t *, size_t> next_code() {
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const uint32_t start = segments_.cs_base_ + registers_.ip();
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return std::make_pair(&memory[start], 0x10'000 - start);
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}
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std::pair<const uint8_t *, size_t> all() {
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return std::make_pair(memory.data(), 0x10'000);
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}
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//
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// Population.
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//
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void install(size_t address, const uint8_t *data, size_t length) {
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std::copy(data, data + length, memory.begin() + std::vector<uint8_t>::difference_type(address));
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}
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private:
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std::array<uint8_t, 1024*1024> memory{0xff};
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Registers ®isters_;
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const Segments &segments_;
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uint32_t segment_base(InstructionSet::x86::Source segment) {
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using Source = InstructionSet::x86::Source;
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switch(segment) {
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default: return segments_.ds_base_;
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case Source::ES: return segments_.es_base_;
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case Source::CS: return segments_.cs_base_;
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case Source::SS: return segments_.ss_base_;
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}
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}
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uint32_t address(InstructionSet::x86::Source segment, uint16_t offset) {
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return (segment_base(segment) + offset) & 0xf'ffff;
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}
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template <AccessType type>
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typename InstructionSet::x86::Accessor<uint16_t, type>::type
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split_word(uint32_t low_address, uint32_t high_address) {
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if constexpr (is_writeable(type)) {
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write_back_address_[0] = low_address;
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write_back_address_[1] = high_address;
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// Prepopulate only if this is a modify.
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if constexpr (type == AccessType::ReadModifyWrite) {
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write_back_value_ = uint16_t(memory[write_back_address_[0]] | (memory[write_back_address_[1]] << 8));
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}
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return write_back_value_;
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} else {
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return uint16_t(memory[low_address] | (memory[high_address] << 8));
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}
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}
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static constexpr uint32_t NoWriteBack = 0; // A low byte address of 0 can't require write-back.
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uint32_t write_back_address_[2] = {NoWriteBack, NoWriteBack};
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uint16_t write_back_value_;
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};
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class IO {
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public:
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IO(PIT<false> &pit) : pit_(pit) {}
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template <typename IntT> void out([[maybe_unused]] uint16_t port, [[maybe_unused]] IntT value) {
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switch(port) {
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default:
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if constexpr (std::is_same_v<IntT, uint8_t>) {
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printf("Unhandled out: %02x to %04x\n", value, port);
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} else {
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printf("Unhandled out: %04x to %04x\n", value, port);
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}
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break;
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// On the XT the NMI can be masked by setting bit 7 on I/O port 0xA0.
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case 0x00a0:
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printf("TODO: NMIs %s\n", (value & 0x80) ? "masked" : "unmasked");
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break;
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case 0x0000: case 0x0001: case 0x0002: case 0x0003:
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case 0x0004: case 0x0005: case 0x0006: case 0x0007:
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case 0x0008: case 0x0009: case 0x000a: case 0x000b:
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case 0x000c: case 0x000d: case 0x000e: case 0x000f:
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printf("TODO: DMA write of %02x at %04x\n", value, port);
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break;
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case 0x0060: case 0x0061: case 0x0062: case 0x0063:
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case 0x0064: case 0x0065: case 0x0066: case 0x0067:
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case 0x0068: case 0x0069: case 0x006a: case 0x006b:
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case 0x006c: case 0x006d: case 0x006e: case 0x006f:
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// Likely to be helpful: https://github.com/tmk/tmk_keyboard/wiki/IBM-PC-XT-Keyboard-Protocol
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printf("TODO: PPI write of %02x at %04x\n", value, port);
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break;
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case 0x0080: case 0x0081: case 0x0082: case 0x0083:
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case 0x0084: case 0x0085: case 0x0086: case 0x0087:
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case 0x0088: case 0x0089: case 0x008a: case 0x008b:
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case 0x008c: case 0x008d: case 0x008e: case 0x008f:
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printf("TODO: DMA page write of %02x at %04x\n", value, port);
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break;
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case 0x03b0: case 0x03b1: case 0x03b2: case 0x03b3:
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case 0x03b4: case 0x03b5: case 0x03b6: case 0x03b7:
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case 0x03b8: case 0x03b9: case 0x03ba: case 0x03bb:
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case 0x03bc: case 0x03bd: case 0x03be: case 0x03bf:
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printf("TODO: MDA write of %02x at %04x\n", value, port);
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break;
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case 0x03d0: case 0x03d1: case 0x03d2: case 0x03d3:
|
|
case 0x03d4: case 0x03d5: case 0x03d6: case 0x03d7:
|
|
case 0x03d8: case 0x03d9: case 0x03da: case 0x03db:
|
|
case 0x03dc: case 0x03dd: case 0x03de: case 0x03df:
|
|
printf("TODO: CGA write of %02x at %04x\n", value, port);
|
|
break;
|
|
|
|
case 0x0040: pit_.write<0>(uint8_t(value)); break;
|
|
case 0x0041: pit_.write<1>(uint8_t(value)); break;
|
|
case 0x0042: pit_.write<2>(uint8_t(value)); break;
|
|
case 0x0043: pit_.set_mode(uint8_t(value)); break;
|
|
}
|
|
}
|
|
template <typename IntT> IntT in([[maybe_unused]] uint16_t port) {
|
|
switch(port) {
|
|
default:
|
|
printf("Unhandled in: %04x\n", port);
|
|
break;
|
|
|
|
case 0x0040: return pit_.read<0>();
|
|
case 0x0041: return pit_.read<1>();
|
|
case 0x0042: return pit_.read<2>();
|
|
|
|
case 0x0060: case 0x0061: case 0x0062: case 0x0063:
|
|
case 0x0064: case 0x0065: case 0x0066: case 0x0067:
|
|
case 0x0068: case 0x0069: case 0x006a: case 0x006b:
|
|
case 0x006c: case 0x006d: case 0x006e: case 0x006f:
|
|
printf("TODO: PPI read from %04x\n", port);
|
|
break;
|
|
}
|
|
return IntT(~0);
|
|
}
|
|
|
|
private:
|
|
PIT<false> &pit_;
|
|
};
|
|
|
|
class FlowController {
|
|
public:
|
|
FlowController(Registers ®isters, Segments &segments) :
|
|
registers_(registers), segments_(segments) {}
|
|
|
|
// Requirements for perform.
|
|
void jump(uint16_t address) {
|
|
registers_.ip() = address;
|
|
}
|
|
|
|
void jump(uint16_t segment, uint16_t address) {
|
|
registers_.cs() = segment;
|
|
segments_.did_update(Segments::Source::CS);
|
|
registers_.ip() = address;
|
|
}
|
|
|
|
void halt() {}
|
|
void wait() {}
|
|
|
|
void repeat_last() {
|
|
should_repeat_ = true;
|
|
}
|
|
|
|
// Other actions.
|
|
void begin_instruction() {
|
|
should_repeat_ = false;
|
|
}
|
|
bool should_repeat() const {
|
|
return should_repeat_;
|
|
}
|
|
|
|
private:
|
|
Registers ®isters_;
|
|
Segments &segments_;
|
|
bool should_repeat_ = false;
|
|
};
|
|
|
|
class ConcreteMachine:
|
|
public Machine,
|
|
public MachineTypes::TimedMachine,
|
|
public MachineTypes::ScanProducer
|
|
{
|
|
public:
|
|
static constexpr int PitMultiplier = 1;
|
|
static constexpr int PitDivisor = 3;
|
|
|
|
ConcreteMachine(
|
|
[[maybe_unused]] const Analyser::Static::Target &target,
|
|
const ROMMachine::ROMFetcher &rom_fetcher
|
|
) : context(pit_) {
|
|
// Use clock rate as a MIPS count; keeping it as a multiple or divisor of the PIT frequency is easy.
|
|
static constexpr int pit_frequency = 1'193'182;
|
|
set_clock_rate(double(pit_frequency) * double(PitMultiplier) / double(PitDivisor)); // i.e. almost 0.4 MIPS for an XT.
|
|
|
|
// Fetch the BIOS. [8088 only, for now]
|
|
const auto bios = ROM::Name::PCCompatibleGLaBIOS;
|
|
|
|
ROM::Request request = ROM::Request(bios);
|
|
auto roms = rom_fetcher(request);
|
|
if(!request.validate(roms)) {
|
|
throw ROMMachine::Error::MissingROMs;
|
|
}
|
|
|
|
const auto &bios_contents = roms.find(bios)->second;
|
|
context.memory.install(0x10'0000 - bios_contents.size(), bios_contents.data(), bios_contents.size());
|
|
}
|
|
|
|
// MARK: - TimedMachine.
|
|
void run_for(const Cycles cycles) override {
|
|
auto instructions = cycles.as_integral();
|
|
while(instructions--) {
|
|
// First draft: all hardware runs in lockstep.
|
|
pit_.run_for(PitDivisor / PitMultiplier);
|
|
|
|
// Get the next thing to execute into decoded.
|
|
if(!context.flow_controller.should_repeat()) {
|
|
// Decode from the current IP.
|
|
const auto remainder = context.memory.next_code();
|
|
decoded = decoder.decode(remainder.first, remainder.second);
|
|
|
|
// If that didn't yield a whole instruction then the end of memory must have been hit;
|
|
// continue from the beginning.
|
|
if(decoded.first <= 0) {
|
|
const auto all = context.memory.all();
|
|
decoded = decoder.decode(all.first, all.second);
|
|
}
|
|
|
|
context.registers.ip() += decoded.first;
|
|
} else {
|
|
context.flow_controller.begin_instruction();
|
|
}
|
|
|
|
// Execute it.
|
|
InstructionSet::x86::perform(
|
|
decoded.second,
|
|
context
|
|
);
|
|
}
|
|
}
|
|
|
|
// MARK: - ScanProducer.
|
|
void set_scan_target([[maybe_unused]] Outputs::Display::ScanTarget *scan_target) override {}
|
|
Outputs::Display::ScanStatus get_scaled_scan_status() const override {
|
|
return Outputs::Display::ScanStatus();
|
|
}
|
|
|
|
private:
|
|
PIT<false> pit_;
|
|
|
|
struct Context {
|
|
Context(PIT<false> &pit) :
|
|
segments(registers),
|
|
memory(registers, segments),
|
|
flow_controller(registers, segments),
|
|
io(pit)
|
|
{
|
|
reset();
|
|
}
|
|
|
|
void reset() {
|
|
registers.reset();
|
|
segments.reset();
|
|
}
|
|
|
|
InstructionSet::x86::Flags flags;
|
|
Registers registers;
|
|
Segments segments;
|
|
Memory memory;
|
|
FlowController flow_controller;
|
|
IO io;
|
|
static constexpr auto model = InstructionSet::x86::Model::i8086;
|
|
} context;
|
|
|
|
// TODO: eliminate use of Decoder8086 and Decoder8086 in gneral in favour of the templated version, as soon
|
|
// as whatever error is preventing GCC from picking up Decoder's explicit instantiations becomes apparent.
|
|
InstructionSet::x86::Decoder8086 decoder;
|
|
// InstructionSet::x86::Decoder<InstructionSet::x86::Model::i8086> decoder;
|
|
|
|
std::pair<int, InstructionSet::x86::Instruction<false>> decoded;
|
|
};
|
|
|
|
|
|
}
|
|
|
|
using namespace PCCompatible;
|
|
|
|
// See header; constructs and returns an instance of the Amstrad CPC.
|
|
Machine *Machine::PCCompatible(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
|
|
return new PCCompatible::ConcreteMachine(*target, rom_fetcher);
|
|
}
|
|
|
|
Machine::~Machine() {}
|