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472 lines
17 KiB
C++
472 lines
17 KiB
C++
//
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// MemoryMap.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 25/10/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#ifndef Machines_Apple_AppleIIgs_MemoryMap_hpp
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#define Machines_Apple_AppleIIgs_MemoryMap_hpp
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#include <array>
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#include <vector>
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#include "../AppleII/LanguageCardSwitches.hpp"
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#include "../AppleII/AuxiliaryMemorySwitches.hpp"
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namespace Apple {
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namespace IIgs {
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class MemoryMap {
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public:
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// MARK: - Initial construction and configuration.
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MemoryMap() : auxiliary_switches_(*this), language_card_(*this) {}
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void set_storage(std::vector<uint8_t> &ram, std::vector<uint8_t> &rom) {
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// Keep a pointer for later; also note the proper RAM offset.
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ram_base = ram.data();
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shadow_base[1] = &ram[ram.size() - 128*1024];
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// Establish bank mapping.
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uint8_t next_region = 0;
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auto region = [&next_region, this]() -> uint8_t {
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assert(next_region != regions.size());
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return next_region++;
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};
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auto set_region = [this](uint8_t bank, uint16_t start, uint16_t end, uint8_t region) {
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assert((end == 0xffff) || !(end&0xff));
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assert(!(start&0xff));
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// Fill in memory map.
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size_t target = size_t((bank << 8) | (start >> 8));
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for(int c = start; c < end; c += 0x100) {
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region_map[target] = region;
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++target;
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}
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};
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auto set_regions = [this, set_region, region](uint8_t bank, std::initializer_list<uint16_t> addresses, std::vector<uint8_t> allocated_regions = {}) {
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uint16_t previous = 0x0000;
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auto next_region = allocated_regions.begin();
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for(uint16_t address: addresses) {
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set_region(bank, previous, address, next_region != allocated_regions.end() ? *next_region : region());
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previous = address;
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assert(next_region != allocated_regions.end() || allocated_regions.empty());
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if(next_region != allocated_regions.end()) ++next_region;
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}
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assert(next_region == allocated_regions.end());
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};
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// Current beliefs about the IIgs memory map:
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//
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// * language card banking applies to banks $00, $01, $e0 and $e1;
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// * auxiliary memory switches apply to banks $00 only;
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// * shadowing may be enabled only on banks $00 and $01, or on all RAM pages.
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//
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// So banks $00 and $01 need their own divided spaces at the shadowing resolution,
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// all the other fast RAM banks can share a set of divided spaces, $e0 and $e1 need
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// to be able to deal with language card-level division but no further, and the pure
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// ROM pages don't need to be subdivided at all.
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// Reserve region 0 as that for unmapped memory.
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region();
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// Bank $00: all locations potentially affected by the auxiliary switches or the
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// language switches. Which will naturally align with shadowable zones.
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set_regions(0x00, {
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0x0200, 0x0400, 0x0800, 0x0c00,
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0x2000, 0x4000, 0x6000,
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0xc000, 0xc100, 0xc300, 0xc400, 0xc800,
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0xd000, 0xe000,
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0xffff
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});
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// Bank $01: all locations potentially affected by the language switches, by shadowing,
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// or marked for IO.
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set_regions(0x01, {
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0x0400, 0x0800, 0x0c00,
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0x2000, 0x4000, 0x6000, 0xa000,
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0xc000, 0xc100, 0xc300, 0xc400, 0xc800,
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0xd000, 0xe000,
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0xffff
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});
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// Banks $02–[end of RAM]: all locations potentially affected by shadowing.
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const uint8_t fast_ram_bank_count = uint8_t((ram.size() - 128*1024) / 65536);
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if(fast_ram_bank_count > 2) {
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const std::vector<uint8_t> evens = {
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region(), // 0x0000 – 0x0400.
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region(), // 0x0400 – 0x0800.
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region(), // 0x0800 – 0x0c00.
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region(), // 0x0c00 – 0x2000.
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region(), // 0x2000 – 0x4000.
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region(), // 0x4000 – 0x6000.
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region(), // 0x6000 – [end].
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};
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const std::vector<uint8_t> odds = {
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region(), // 0x0000 – 0x0400.
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region(), // 0x0400 – 0x0800.
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region(), // 0x0800 – 0x0c00.
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region(), // 0x0c00 – 0x2000.
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region(), // 0x2000 – 0x4000.
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region(), // 0x4000 – 0x6000.
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region(), // 0x6000 – 0xa000.
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region(), // 0xa000 – [end].
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};
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for(uint8_t bank = 0x02; bank < fast_ram_bank_count; bank += 2) {
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set_regions(bank, {0x0400, 0x0800, 0x0c00, 0x2000, 0x4000, 0x6000, 0xffff}, evens);
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set_regions(bank+1, {0x0400, 0x0800, 0x0c00, 0x2000, 0x4000, 0x6000, 0xa000, 0xffff}, odds);
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}
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}
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// [Banks $80–$e0: empty].
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// Banks $e0, $e1: all locations potentially affected by the language switches or marked for IO.
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// Alas, separate regions are needed due to the same ROM appearing on both pages.
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for(uint8_t c = 0; c < 2; c++) {
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set_regions(0xe0 + c, {0xc000, 0xc100, 0xc300, 0xc400, 0xc800, 0xd000, 0xe000, 0xffff});
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}
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// [Banks $e2–[ROM start]: empty].
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// ROM banks: directly mapped to ROM.
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const uint8_t rom_bank_count = uint8_t(rom.size() >> 16);
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const uint8_t first_rom_bank = uint8_t(0x100 - rom_bank_count);
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const uint8_t rom_region = region();
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for(uint8_t c = 0; c < rom_bank_count; ++c) {
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set_region(first_rom_bank + c, 0x0000, 0xffff, rom_region);
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}
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// Apply proper storage to those banks.
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auto set_storage = [this](uint32_t address, const uint8_t *read, uint8_t *write) {
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// Don't allow the reserved null region to be modified.
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assert(region_map[address >> 8]);
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// Either set or apply a quick bit of testing as to the logic at play.
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auto ®ion = regions[region_map[address >> 8]];
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if(read) read -= address;
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if(write) write -= address;
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if(!region.read) {
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region.read = read;
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region.write = write;
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} else {
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assert(region.read == read);
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assert(region.write == write);
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}
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};
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// This is highly redundant, but decouples this step from the above.
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for(size_t c = 0; c < 0x800000; c += 0x100) {
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if(c < ram.size() - 128*1024) {
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set_storage(uint32_t(c), &ram[c], &ram[c]);
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}
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}
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uint8_t *const slow_ram = &ram[ram.size() - 0x20000];
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for(size_t c = 0xe00000; c < 0xe20000; c += 0x100) {
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set_storage(uint32_t(c), &slow_ram[c - 0xe00000], &slow_ram[c - 0xe00000]);
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}
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for(uint32_t c = 0; c < uint32_t(rom_bank_count); c++) {
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set_storage((first_rom_bank + c) << 16, &rom[c << 16], nullptr);
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}
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// TODO: set 1Mhz flags.
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// Apply initial language/auxiliary state.
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set_card_paging();
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set_zero_page_paging();
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set_main_paging();
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set_shadowing();
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}
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// MARK: - Live bus access notifications.
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void set_shadow_register(uint8_t value) {
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const uint8_t diff = value ^ shadow_register_;
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shadow_register_ = value;
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if(diff & 0x40) { // IO/language-card inhibit
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set_language_card_paging();
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set_card_paging();
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}
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if(diff & 0x3f) {
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set_shadowing();
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}
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}
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void set_speed_register(uint8_t value) {
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const uint8_t diff = value ^ speed_register_;
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speed_register_ = value;
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if(diff & 0x10) {
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set_shadowing();
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}
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}
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void access(uint16_t address, bool is_read) {
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auxiliary_switches_.access(address, is_read);
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if(address &0xfff0 == 0xc080) language_card_.access(address, is_read);
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}
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private:
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Apple::II::AuxiliaryMemorySwitches<MemoryMap> auxiliary_switches_;
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Apple::II::LanguageCardSwitches<MemoryMap> language_card_;
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friend Apple::II::AuxiliaryMemorySwitches<MemoryMap>;
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friend Apple::II::LanguageCardSwitches<MemoryMap>;
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uint8_t shadow_register_ = 0x08;
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uint8_t speed_register_ = 0x00;
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// MARK: - Memory banking.
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void set_language_card_paging() {
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const auto language_state = language_card_.state();
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const auto zero_state = auxiliary_switches_.zero_state();
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const bool inhibit_banks0001 = shadow_register_ & 0x40;
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auto apply = [&language_state, &zero_state, this](uint32_t bank_base, uint8_t *ram) {
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// All references below are to 0xc000, 0xd000 and 0xe000 but should
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// work regardless of bank.
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// TODO: verify order of ternary here — on the plain Apple II it was arbitrary.
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uint8_t *const lower_ram_bank = ram - (language_state.bank1 ? 0x0000 : 0x1000);
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// Crib the ROM pointer from a page it's always visible on.
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const uint8_t *const rom = ®ions[region_map[0xffd0]].read[0xffd000] - ((bank_base << 8) + 0xd000);
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auto &d0_region = regions[region_map[bank_base | 0xd0]];
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d0_region.read = language_state.read ? lower_ram_bank : rom;
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d0_region.write = language_state.write ? nullptr : lower_ram_bank;
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auto &e0_region = regions[region_map[bank_base | 0xe0]];
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e0_region.read = language_state.read ? ram : rom;
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e0_region.write = language_state.write ? nullptr : ram;
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// Assert assumptions made above re: memory layout.
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assert(region_map[bank_base | 0xd0] + 1 == region_map[bank_base | 0xe0]);
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assert(region_map[bank_base | 0xe0] == region_map[bank_base | 0xff]);
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};
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auto set_no_card = [this](uint32_t bank_base) {
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auto &d0_region = regions[region_map[bank_base | 0xd0]];
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d0_region.read = ram_base;
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d0_region.write = ram_base;
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auto &e0_region = regions[region_map[bank_base | 0xe0]];
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e0_region.read = ram_base;
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e0_region.write = ram_base;
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};
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if(inhibit_banks0001) {
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set_no_card(0x0000);
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set_no_card(0x0100);
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} else {
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apply(0x0000, zero_state ? &ram_base[0x10000] : ram_base);
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apply(0x0100, ram_base);
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}
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uint8_t *const e0_ram = regions[region_map[0xe000]].write;
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apply(0xe000, e0_ram);
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apply(0xe100, e0_ram);
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}
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void set_card_paging() {
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const bool inhibit_banks0001 = shadow_register_ & 0x40;
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const auto state = auxiliary_switches_.card_state();
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auto apply = [&state, this](uint32_t bank_base) {
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auto &c0_region = regions[region_map[bank_base | 0xc0]];
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auto &c1_region = regions[region_map[bank_base | 0xc1]];
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auto &c3_region = regions[region_map[bank_base | 0xc3]];
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auto &c4_region = regions[region_map[bank_base | 0xc4]];
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auto &c8_region = regions[region_map[bank_base | 0xc8]];
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const uint8_t *const rom = ®ions[region_map[0xffd0]].read[0xffc100] - ((bank_base << 8) + 0xc100);
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// This is applied dynamically as it may be added or lost in banks $00 and $01.
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c0_region.flags |= Region::IsIO;
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#define apply_region(flag, region) \
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if(flag) { \
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region.read = rom; \
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region.flags &= ~Region::IsIO; \
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} else { \
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region.flags |= Region::IsIO; \
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}
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apply_region(state.region_C1_C3, c1_region);
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apply_region(state.region_C3, c3_region);
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apply_region(state.region_C4_C8, c4_region);
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apply_region(state.region_C8_D0, c8_region);
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#undef apply_region
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// Sanity checks.
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assert(region_map[bank_base | 0xc1] == region_map[bank_base | 0xc0]+1);
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assert(region_map[bank_base | 0xc3] == region_map[bank_base | 0xc1]+1);
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assert(region_map[bank_base | 0xc4] == region_map[bank_base | 0xc3]+1);
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assert(region_map[bank_base | 0xc8] == region_map[bank_base | 0xc4]+1);
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};
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if(inhibit_banks0001) {
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// Set no IO in the Cx00 range for banks $00 and $01, just
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// regular RAM (or possibly auxiliary).
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const auto auxiliary_state = auxiliary_switches_.main_state();
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for(uint8_t region = region_map[0x00c0]; region < region_map[0x00d0]; region++) {
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regions[region].read = auxiliary_state.base.read ? &ram_base[0x10000] : ram_base;
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regions[region].write = auxiliary_state.base.write ? &ram_base[0x10000] : ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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for(uint8_t region = region_map[0x01c0]; region < region_map[0x01d0]; region++) {
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regions[region].read = regions[region].write = ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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} else {
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// Obey the card state for banks $00 and $01.
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apply(0x0000);
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apply(0x0100);
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}
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// Obey the card state for banks $e0 and $e1.
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apply(0xe000);
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apply(0xe100);
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}
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void set_zero_page_paging() {
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// Affects bank $00 only, and should be a single region.
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auto ®ion = regions[region_map[0]];
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region.read = region.write = auxiliary_switches_.zero_state() ? &ram_base[0x10000] : ram_base;
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// Switching to or from auxiliary RAM potentially affects the language
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// and regular card areas.
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set_card_paging();
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set_language_card_paging();
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}
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void set_shadowing() {
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const bool inhibit_all_pages = speed_register_ & 0x10;
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#define apply(flag, zone) \
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if(flag) { \
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regions[region_map[zone]].flags &= ~Region::IsShadowed; \
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} else { \
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regions[region_map[zone]].flags |= Region::IsShadowed; \
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}
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// Text Page 1, main and auxiliary.
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apply(shadow_register_ & 0x01, 0x0004);
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apply(shadow_register_ & 0x01, 0x0104);
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apply((shadow_register_ & 0x01) && inhibit_all_pages, 0x0204);
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apply((shadow_register_ & 0x01) && inhibit_all_pages, 0x0304);
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// Text Page 2, main and auxiliary.
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// TODO: on a ROM03 machine only.
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apply(shadow_register_ & 0x20, 0x0008);
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apply(shadow_register_ & 0x20, 0x0108);
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apply((shadow_register_ & 0x20) && inhibit_all_pages, 0x0208);
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apply((shadow_register_ & 0x20) && inhibit_all_pages, 0x0308);
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// Hi-res graphics Page 1, main and auxiliary.
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apply(shadow_register_ & 0x02, 0x0020);
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apply(shadow_register_ & 0x12, 0x0120);
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apply((shadow_register_ & 0x02) && inhibit_all_pages, 0x0220);
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apply((shadow_register_ & 0x12) && inhibit_all_pages, 0x0320);
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// Hi-res graphics Page 2, main and auxiliary.
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apply(shadow_register_ & 0x04, 0x0040);
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apply(shadow_register_ & 0x14, 0x0140);
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apply((shadow_register_ & 0x04) && inhibit_all_pages, 0x0240);
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apply((shadow_register_ & 0x14) && inhibit_all_pages, 0x0340);
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// Residue of Super Hi-Res.
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apply(shadow_register_ & 0x08, 0x0160);
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apply((shadow_register_ & 0x08) && inhibit_all_pages, 0x0360);
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// TODO: does inhibiting Super Hi-Res also affect the regular hi-res pages?
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#undef apply
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}
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void set_main_paging() {
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const auto state = auxiliary_switches_.main_state();
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#define set(page, flags) {\
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auto ®ion = regions[region_map[page]]; \
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region.read = flags.read ? &ram_base[0x10000] : ram_base; \
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region.write = flags.write ? &ram_base[0x10000] : ram_base; \
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}
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set(0x02, state.base);
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set(0x08, state.base);
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set(0x40, state.base);
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set(0x04, state.region_04_08);
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set(0x20, state.region_20_40);
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#undef set
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// This also affects shadowing flags, if shadowing is enabled at all,
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// and might affect RAM in the IO area of bank $00 because the language
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// card can be inhibited on a IIgs.
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set_shadowing();
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set_card_paging();
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}
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uint8_t shadow_throwaway_;
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public:
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// Memory layout here is done via double indirection; the main loop should:
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// (i) use the top two bytes of the address to get an index from memory_map_; and
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// (ii) use that to index the memory_regions table.
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//
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// Pointers are eight bytes at the time of writing, so the extra level of indirection
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// reduces what would otherwise be a 1.25mb table down to not a great deal more than 64kb.
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std::array<uint8_t, 65536> region_map;
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uint8_t *ram_base = nullptr;
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uint8_t *shadow_base[2] = {&shadow_throwaway_, nullptr};
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const int shadow_modulo[2] = {1, 128*1024};
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struct Region {
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uint8_t *write = nullptr;
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const uint8_t *read = nullptr;
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uint8_t flags = 0;
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enum Flag: uint8_t {
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IsShadowed = 1 << 0, // Writes should be shadowed to [end of RAM - 128kb + base offset].
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Is1Mhz = 1 << 1, // Both reads and writes should be synchronised with the 1Mhz clock.
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IsIO = 1 << 2, // Indicates that this region should be checked for soft switches, registers, etc;
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// usurps the shadowed flags.
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};
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};
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std::array<Region, 64> regions; // The assert above ensures that this is large enough; there's no
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// doctrinal reason for it to be whatever size it is now, just
|
||
// adjust as required.
|
||
};
|
||
|
||
// TODO: branching below on region.read/write is predicated on the idea that extra scratch space
|
||
// would be less efficient. Verify that?
|
||
|
||
#define MemoryMapRegion(map, address) map.regions[map.region_map[address >> 8]]
|
||
#define MemoryMapRead(region, address, value) *value = region.read ? region.read[address] : 0xff
|
||
#define MemoryMapWrite(map, region, address, value) \
|
||
if(region.write) { \
|
||
region.write[address] = *value; \
|
||
const auto is_shadowed = region.flags & MemoryMap::Region::IsShadowed; \
|
||
map.shadow_base[is_shadowed][(®ion.write[address] - map.ram_base) % map.shadow_modulo[is_shadowed]] = *value; \
|
||
}
|
||
|
||
// Quick notes on ::IsShadowed contortions:
|
||
//
|
||
// The objective is to support shadowing:
|
||
// 1. without storing a whole extra pointer, and such that the shadowing flags are orthogonal to the current auxiliary memory settings;
|
||
// 2. in such a way as to support shadowing both in banks $00/$01 and elsewhere; and
|
||
// 3. to do so without introducing too much in the way of branching.
|
||
//
|
||
// Hence the implemented solution: if shadowing is enabled then use the distance from the start of physical RAM
|
||
// modulo 128k indexed into the bank $e0/$e1 RAM.
|
||
//
|
||
// With a further twist: the modulo and pointer are indexed on ::IsShadowed to eliminate a branch even on that.
|
||
|
||
}
|
||
}
|
||
|
||
#endif /* MemoryMap_h */
|