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107 lines
3.1 KiB
C++
107 lines
3.1 KiB
C++
//
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// Z80AllRAM.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#include "Z80AllRAM.hpp"
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#include <algorithm>
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using namespace CPU::Z80;
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namespace {
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class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<ConcreteAllRAMProcessor> {
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public:
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ConcreteAllRAMProcessor() : AllRAMProcessor(), completed_cycles(0) {}
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inline int perform_machine_cycle(const MachineCycle &cycle) {
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completed_cycles += cycle.length;
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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case MachineCycle::Operation::ReadOpcode:
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// printf("! ");
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check_address_for_trap(address);
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case MachineCycle::Operation::Read:
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// printf("r %04x [%02x] AF:%04x BC:%04x DE:%04x HL:%04x SP:%04x\n", address, memory_[address], get_value_of_register(CPU::Z80::Register::AF), get_value_of_register(CPU::Z80::Register::BC), get_value_of_register(CPU::Z80::Register::DE), get_value_of_register(CPU::Z80::Register::HL), get_value_of_register(CPU::Z80::Register::StackPointer));
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*cycle.value = memory_[address];
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break;
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case MachineCycle::Operation::Write:
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// printf("w %04x\n", address);
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memory_[address] = *cycle.value;
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break;
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case MachineCycle::Operation::Output:
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break;
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case MachineCycle::Operation::Input:
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// This logic is selected specifically because it seems to match
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// the FUSE unit tests. It might need factoring out.
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*cycle.value = address >> 8;
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break;
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case MachineCycle::Operation::Internal:
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break;
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case MachineCycle::Operation::Interrupt:
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// A pick that means LD HL, (nn) if interpreted as an instruction but is otherwise
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// arbitrary.
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*cycle.value = 0x21;
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break;
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default:
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printf("???\n");
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break;
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}
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timestamp_ += cycle.length;
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if(delegate_ != nullptr) {
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delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle.operation, address, cycle.value ? *cycle.value : 0x00, timestamp_);
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}
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return 0;
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}
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void run_for_cycles(int cycles) {
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CPU::Z80::Processor<ConcreteAllRAMProcessor>::run_for_cycles(cycles);
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}
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uint16_t get_value_of_register(Register r) {
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return CPU::Z80::Processor<ConcreteAllRAMProcessor>::get_value_of_register(r);
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}
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void set_value_of_register(Register r, uint16_t value) {
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CPU::Z80::Processor<ConcreteAllRAMProcessor>::set_value_of_register(r, value);
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}
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bool get_halt_line() {
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return CPU::Z80::Processor<ConcreteAllRAMProcessor>::get_halt_line();
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}
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void reset_power_on() {
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return CPU::Z80::Processor<ConcreteAllRAMProcessor>::reset_power_on();
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}
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void set_interrupt_line(bool value) {
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CPU::Z80::Processor<ConcreteAllRAMProcessor>::set_interrupt_line(value);
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}
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void set_non_maskable_interrupt_line(bool value) {
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CPU::Z80::Processor<ConcreteAllRAMProcessor>::set_non_maskable_interrupt_line(value);
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}
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int get_length_of_completed_machine_cycles() {
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return completed_cycles;
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}
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private:
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int completed_cycles;
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};
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}
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AllRAMProcessor *AllRAMProcessor::Processor() {
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return new ConcreteAllRAMProcessor;
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}
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