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593 lines
21 KiB
C++
593 lines
21 KiB
C++
//
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// Z80.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 14/05/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#ifndef Z80_hpp
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#define Z80_hpp
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#include <cstdint>
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#include <cstdio>
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#include "../MicroOpScheduler.hpp"
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#include "../RegisterSizes.hpp"
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namespace CPU {
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namespace Z80 {
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/*
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The list of registers that can be accessed via @c set_value_of_register and @c set_value_of_register.
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*/
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enum Register {
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ProgramCounter,
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StackPointer,
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A, Flags, AF,
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B, C, BC,
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D, E, DE,
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H, L, HL,
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ADash, FlagsDash, AFDash,
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BDash, CDash, BCDash,
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DDash, EDash, DEDash,
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HDash, LDash, HLDash,
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IXh, IXl, IX,
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IYh, IYl, IY,
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R, I,
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};
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/*
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Flags as defined on the Z80; can be used to decode the result of @c get_flags or to form a value for @c set_flags.
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*/
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enum Flag: uint8_t {
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Sign = 0x80,
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Zero = 0x40,
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Bit5 = 0x20,
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HalfCarry = 0x10,
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Bit3 = 0x08,
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Parity = 0x04,
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Overflow = 0x04,
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Subtract = 0x02,
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Carry = 0x01
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};
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/*!
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Subclasses will be given the task of performing bus operations, allowing them to provide whatever interface they like
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between a Z80 and the rest of the system. @c BusOperation lists the types of bus operation that may be requested.
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@c None is reserved for internal use. It will never be requested from a subclass.
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*/
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enum BusOperation {
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ReadOpcode = 0,
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Read, Write,
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Input, Output,
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Interrupt,
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// BusRequest, BusAcknowledge,
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Internal
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};
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struct MachineCycle {
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const BusOperation operation;
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const int length;
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const uint16_t *address;
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uint8_t *const value;
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};
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struct MicroOp {
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enum {
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BusOperation,
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DecodeOperation,
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MoveToNextProgram,
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Increment16,
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Decrement16,
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Move8,
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Move16,
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AssembleAF,
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DisassembleAF,
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And,
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Or,
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Xor,
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TestNZ,
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TestZ,
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TestNC,
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TestC,
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TestPO,
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TestPE,
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TestP,
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TestM,
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None
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} type;
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void *source;
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void *destination;
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MachineCycle machine_cycle;
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};
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/*!
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@abstact An abstract base class for emulation of a 6502 processor via the curiously recurring template pattern/f-bounded polymorphism.
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@discussion Subclasses should implement @c perform_bus_operation(BusOperation operation, uint16_t address, uint8_t *value) in
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order to provide the bus on which the 6502 operates and @c flush(), which is called upon completion of a continuous run
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of cycles to allow a subclass to bring any on-demand activities up to date.
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Additional functionality can be provided by the host machine by providing a jam handler and inserting jam opcodes where appropriate;
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that will cause call outs when the program counter reaches those addresses. @c return_from_subroutine can be used to exit from a
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jammed state.
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*/
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template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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private:
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uint8_t a_, i_, r_;
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RegisterPair bc_, de_, hl_;
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RegisterPair afDash_, bcDash_, deDash_, hlDash_;
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RegisterPair ix_, iy_, pc_, sp_;
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uint8_t sign_result_, zero_result_, bit5_result_, half_carry_flag_, bit3_result_, parity_overflow_flag_, subtract_flag_, carry_flag_;
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int number_of_cycles_;
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const MicroOp **program_table_;
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uint8_t operation_;
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RegisterPair address_, temporary_;
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void decode_base_operation(uint8_t operation) {
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#define XX {MicroOp::None, 0}
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#define FETCH(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Read, 3, &y.full, &x}}, {MicroOp::Increment16, &y.full}
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#define FETCHL(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Read, 3, &y.full, &x}}
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#define STOREL(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Write, 3, &y.full, &x}}
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#define FETCH16(x, y) FETCH(x.bytes.low, y), FETCH(x.bytes.high, y)
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#define FETCH16L(x, y) FETCH(x.bytes.low, y), FETCHL(x.bytes.high, y)
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#define PUSH(x) {MicroOp::Decrement16, &sp_.full}, STOREL(x.bytes.high, sp_), {MicroOp::Decrement16, &sp_.full}, STOREL(x.bytes.low, sp_)
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#define POP(x) FETCHL(x.bytes.low, sp_), {MicroOp::Increment16, &sp_.full}, FETCHL(x.bytes.high, sp_), {MicroOp::Increment16, &sp_.full}
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#define JP(cc) Program(FETCH16(temporary_, pc_), {MicroOp::cc}, {MicroOp::Move16, &address_.full, &pc_.full})
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#define LD(a, b) Program({MicroOp::Move8, &b, &a})
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#define LD_GROUP(r) \
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LD(r, bc_.bytes.high), LD(r, bc_.bytes.low), LD(r, de_.bytes.high), LD(r, de_.bytes.low), \
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LD(r, hl_.bytes.high), LD(r, hl_.bytes.low), Program(FETCHL(r, hl_)), LD(r, a_)
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#define OP_GROUP(op) \
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Program({MicroOp::op, &bc_.bytes.high}), Program({MicroOp::op, &bc_.bytes.low}), \
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Program({MicroOp::op, &de_.bytes.high}), Program({MicroOp::op, &de_.bytes.low}), \
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Program({MicroOp::op, &hl_.bytes.high}), Program({MicroOp::op, &hl_.bytes.low}), \
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Program(FETCHL(temporary_.bytes.low, hl_), {MicroOp::op, &temporary_.bytes.low}), \
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Program({MicroOp::op, &a_})
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#define WAIT(n) {MicroOp::BusOperation, nullptr, nullptr, {Internal, n} }
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#define Program(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} }
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static const MicroOp base_program_table[256][20] = {
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{ {MicroOp::MoveToNextProgram} }, /* 0x00 NOP */
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Program(FETCH16(bc_, pc_)), /* 0x01 LD BC, nn */
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XX, /* 0x02 LD (BC), A */
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Program(WAIT(2), {MicroOp::Increment16, &bc_.full}), /* 0x03 INC BC */
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XX, /* 0x04 INC B */
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XX, /* 0x05 DEC B */
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Program(FETCH(bc_.bytes.high, pc_)), /* 0x06 LD B, n */
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XX, /* 0x07 RLCA */
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XX, /* 0x08 EX AF, AF' */
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XX, /* 0x09 ADD HL, BC */
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Program(FETCHL(a_, bc_)), /* 0x0a LD A, (BC) */
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Program(WAIT(2), {MicroOp::Decrement16, &bc_.full}), /* 0x0b DEC BC */
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XX, /* 0x0c INC C */
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XX, /* 0x0d DEC C */
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Program(FETCH(bc_.bytes.low, pc_)), /* 0x0e LD C, n */
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XX, /* 0x0f RRCA */
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XX, /* 0x10 DJNZ */
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Program(FETCH16(de_, pc_)), /* 0x11 LD DE, nn */
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XX, /* 0x12 LD (DE), A */
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Program(WAIT(2), {MicroOp::Increment16, &de_.full}), /* 0x13 INC DE */
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XX, /* 0x14 INC D */
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XX, /* 0x15 DEC D */
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Program(FETCH(de_.bytes.high, pc_)), /* 0x16 LD D, n */
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XX, /* 0x17 RLA */
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XX, /* 0x18 JR */
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XX, /* 0x19 ADD HL, DE */
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Program(FETCHL(a_, de_)), /* 0x1a LD A, (DE) */
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Program(WAIT(2), {MicroOp::Decrement16, &de_.full}), /* 0x1b DEC DE */
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XX, /* 0x1c INC E */
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XX, /* 0x1d DEC E */
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Program(FETCH(de_.bytes.low, pc_)), /* 0x1e LD E, n */
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XX, /* 0x1f RRA */
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XX, /* 0x20 JR NZ */
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Program(FETCH16(hl_, pc_)), /* 0x21 LD HL, nn */
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XX, /* 0x22 LD (nn), HL */
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Program(WAIT(2), {MicroOp::Increment16, &hl_.full}), /* 0x23 INC HL */
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XX, /* 0x24 INC H */
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XX, /* 0x25 DEC H */
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Program(FETCH(hl_.bytes.high, pc_)), /* 0x26 LD H, n */
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XX, /* 0x27 DAA */
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XX, /* 0x28 JR Z */
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XX, /* 0x29 ADD HL, HL */
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Program(FETCH16(address_, pc_), FETCH16L(hl_, address_)), /* 0x2a LD HL, (nn) */
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Program(WAIT(2), {MicroOp::Decrement16, &hl_.full}), /* 0x2b DEC HL */
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XX, /* 0x2c INC L */
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XX, /* 0x2d DEC L */
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Program(FETCH(hl_.bytes.low, pc_)), /* 0x2e LD L, n */
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XX, /* 0x2f CPL */
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XX, /* 0x30 JR NC */
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Program(FETCH16(sp_, pc_)), /* 0x31 LD SP, nn */
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XX, /* 0x32 LD (nn), A */
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Program(WAIT(2), {MicroOp::Increment16, &sp_.full}), /* 0x33 INC SP */
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XX, /* 0x34 INC (HL) */
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XX, /* 0x35 DEC (HL) */
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XX, /* 0x36 LD (HL), n */
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XX, /* 0x37 SCF */
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XX, /* 0x38 JR C */
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XX, /* 0x39 ADD HL, SP */
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XX, /* 0x3a LD A, (nn) */
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Program(WAIT(2), {MicroOp::Decrement16, &sp_.full}), /* 0x3b DEC SP */
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XX, /* 0x3c INC A */
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XX, /* 0x3d DEC A */
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XX, /* 0x3e LD A, n */
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XX, /* 0x3f CCF */
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LD_GROUP(bc_.bytes.high), /* 0x40 LD B, B; 0x41 LD B, C; 0x42 LD B, D; 0x43 LD B, E; 0x44 LD B, H; 0x45 LD B, L; 0x46 LD B, (HL); 0x47 LD B, A */
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LD_GROUP(bc_.bytes.low), /* 0x48 LD C, B; 0x49 LD C, C; 0x4a LD C, D; 0x4b LD C, E; 0x4c LD C, H; 0x4d LD C, L; 0x4e LD C, (HL); 0x4f LD C, A */
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LD_GROUP(de_.bytes.high), /* 0x50 LD D, B; 0x51 LD D, C; 0x52 LD D, D; 0x53 LD D, E; 0x54 LD D, H; 0x55 LD D, L; 0x56 LD D, (HL); 0x57 LD D, A */
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LD_GROUP(de_.bytes.low), /* 0x58 LD E, B; 0x59 LD E, C; 0x5a LD E, D; 0x5b LD E, E; 0x5c LD E, H; 0x5d LD E, L; 0x5e LD E, (HL); 0x5f LD E, A */
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LD_GROUP(hl_.bytes.high), /* 0x60 LD H, B; 0x61 LD H, C; 0x62 LD H, D; 0x63 LD H, E; 0x64 LD H, H; 0x65 LD H, L; 0x66 LD H, (HL); 0x67 LD H, A */
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LD_GROUP(hl_.bytes.low), /* 0x68 LD L, B; 0x69 LD L, C; 0x6a LD L, D; 0x6b LD L, E; 0x6c LD L, H; 0x6d LD H, L; 0x6e LD L, (HL); 0x6f LD L, A */
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x70
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LD_GROUP(a_), /* 0x78 LD A, B; 0x79 LD A, C; 0x7a LD A, D; 0x7b LD A, E; 0x7c LD A, H; 0x7d LD A, L; 0x7e LD A, (HL); 0x7f LD A, A */
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x80
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x88
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x90
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x98
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OP_GROUP(And), /* 0xa0 AND B; 0xa1 AND C; 0xa2 AND D; 0xa3 AND E; 0xa4 AND H; 0xa5 AND L; 0xa6 AND (HL); 0xa7 AND A */
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OP_GROUP(Xor), /* 0xa8 XOR B; 0xa9 XOR C; 0xaa XOR D; 0xab XOR E; 0xac XOR H; 0xad XOR L; 0xae XOR (HL); 0xaf XOR A */
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OP_GROUP(Or), /* 0xb0 OR B; 0xb1 OR C; 0xb2 OR D; 0xb3 OR E; 0xb4 OR H; 0xb5 OR L; 0xb6 OR (HL); 0xb7 OR A */
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xb8
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XX, /* 0xc0 RET NZ */
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Program(POP(bc_)), /* 0xc1 POP BC */
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JP(TestNZ), /* 0xc2 JP NZ */
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Program(FETCH16L(address_, pc_), {MicroOp::Move16, &address_.full, &pc_.full}), /* 0xc3 JP nn */
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XX, /* 0xc4 CALL NZ */
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Program(WAIT(1), PUSH(bc_)), /* 0xc5 PUSH BC */
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XX, /* 0xc6 ADD A, n */
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XX, /* 0xc7 RST 00h */
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XX, /* 0xc8 RET Z */
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Program(POP(pc_)), /* 0xc9 RET */
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JP(TestZ), /* 0xca JP Z */
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XX, /* 0xcb [CB page] */
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XX, /* 0xcc CALL Z */
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Program(FETCH16(address_, pc_), WAIT(1), PUSH(pc_), {MicroOp::Move16, &address_.full, &pc_.full}), /* 0xcd CALL */
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XX, /* 0xce ADC A, n */
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XX, /* 0xcf RST 08h */
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XX, /* 0xd0 RET NC */
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Program(POP(de_)), /* 0xd1 POP DE */
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JP(TestNC), /* 0xd2 JP NC */
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XX, /* 0xd3 OUT (n), A */
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XX, /* 0xd4 CALL NC */
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Program(WAIT(1), PUSH(de_)), /* 0xd5 PUSH DE */
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XX, /* 0xd6 SUB n */
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XX, /* 0xd7 RST 10h */
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XX, /* 0xd8 RET C */
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XX, /* 0xd9 EXX */
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JP(TestC), /* 0xda JP C */
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XX, /* 0xdb IN A, (n) */
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XX, /* 0xdc CALL C */
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XX, /* 0xdd [DD page] */
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XX, /* 0xde SBC A, n */
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XX, /* 0xdf RST 18h */
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XX, /* 0xe0 RET PO */
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Program(POP(hl_)), /* 0xe1 POP HL */
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JP(TestPO), /* 0xe2 JP PO */
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XX, /* 0xe3 EX (SP), HL */
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XX, /* 0xe4 CALL PO */
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Program(WAIT(1), PUSH(hl_)), /* 0xe5 PUSH HL */
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XX, /* 0xe6 AND n */
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XX, /* 0xe7 RST 20h */
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XX, /* 0xe8 RET PE */
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XX, /* 0xe9 JP (HL) */
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JP(TestPE), /* 0xea JP PE */
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XX, /* 0xeb EX DE, HL */
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XX, /* 0xec CALL PE */
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XX, /* 0xed [ED page] */
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XX, /* 0xee XOR n */
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XX, /* 0xef RST 28h */
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XX, /* 0xf0 RET p */
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Program(POP(temporary_), {MicroOp::DisassembleAF}), /* 0xf1 POP AF */
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JP(TestP), /* 0xf2 JP P */
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XX, /* 0xf3 DI */
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XX, /* 0xf4 CALL P */
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Program(WAIT(1), {MicroOp::AssembleAF}, PUSH(temporary_)), /* 0xf5 PUSH AF */
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XX, /* 0xf6 OR n */
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XX, /* 0xf7 RST 30h */
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XX, /* 0xf8 RET M */
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Program(WAIT(2), {MicroOp::Move16, &hl_.full, &sp_.full}), /* 0xf9 LD SP, HL */
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JP(TestM), /* 0xfa JP M */
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XX, /* 0xfb EI */
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XX, /* 0xfc CALL M */
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XX, /* 0xfd [FD page] */
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XX, /* 0xfe CP n */
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XX, /* 0xff RST 38h */
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};
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if(base_program_table[operation][0].type == MicroOp::None) {
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printf("Unknown Z80 operation %02x!!!\n", operation);
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}
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schedule_program(base_program_table[operation]);
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// program_table_ = base_program_table;
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}
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public:
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Processor() {
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// set_base_program_table();
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}
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/*!
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Runs the Z80 for a supplied number of cycles.
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@discussion Subclasses must implement @c perform_machine_cycle(MachineCycle *cycle) .
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If it is a read operation then @c value will be seeded with the value 0xff.
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@param number_of_cycles The number of cycles to run the Z80 for.
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*/
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void run_for_cycles(int number_of_cycles) {
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static const MicroOp fetch_decode_execute[] = {
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{ MicroOp::BusOperation, nullptr, nullptr, {ReadOpcode, 4, &pc_.full, &operation_}},
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{ MicroOp::DecodeOperation },
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{ MicroOp::MoveToNextProgram }
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};
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#define checkSchedule() \
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if(!scheduled_programs_[schedule_programs_read_pointer_]) {\
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schedule_program(fetch_decode_execute);\
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}
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number_of_cycles_ += number_of_cycles;
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checkSchedule();
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while(1) {
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const MicroOp *operation = &scheduled_programs_[schedule_programs_read_pointer_][schedule_program_program_counter_];
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schedule_program_program_counter_++;
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switch(operation->type) {
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case MicroOp::BusOperation:
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if(number_of_cycles_ < operation->machine_cycle.length) {
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return;
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}
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static_cast<T *>(this)->perform_machine_cycle(&operation->machine_cycle);
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break;
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case MicroOp::MoveToNextProgram:
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move_to_next_program();
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checkSchedule();
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break;
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case MicroOp::DecodeOperation:
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pc_.full++;
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decode_base_operation(operation_);
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break;
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case MicroOp::Increment16: (*(uint16_t *)operation->source)++; break;
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case MicroOp::Decrement16: (*(uint16_t *)operation->source)--; break;
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case MicroOp::Move8: *(uint8_t *)operation->destination = *(uint8_t *)operation->source; break;
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case MicroOp::Move16: *(uint16_t *)operation->destination = *(uint16_t *)operation->source; break;
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case MicroOp::AssembleAF:
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temporary_.bytes.high = a_;
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temporary_.bytes.low = get_flags();
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break;
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case MicroOp::DisassembleAF:
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a_ = temporary_.bytes.high;
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set_flags(temporary_.bytes.low);
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break;
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#define set_parity(v) \
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parity_overflow_flag_ = v^1;\
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parity_overflow_flag_ ^= parity_overflow_flag_ >> 4;\
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parity_overflow_flag_ ^= parity_overflow_flag_ << 2;\
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parity_overflow_flag_ ^= parity_overflow_flag_ >> 1;\
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parity_overflow_flag_ &= Flag::Parity;
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case MicroOp::And:
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a_ &= *(uint8_t *)operation->source;
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sign_result_ = zero_result_ = bit5_result_ = bit3_result_ = a_;
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parity_overflow_flag_ = 0;
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set_parity(a_);
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break;
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case MicroOp::Or:
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a_ |= *(uint8_t *)operation->source;
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sign_result_ = zero_result_ = bit5_result_ = bit3_result_ = a_;
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parity_overflow_flag_ = 0;
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set_parity(a_);
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break;
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case MicroOp::Xor:
|
|
a_ ^= *(uint8_t *)operation->source;
|
|
sign_result_ = zero_result_ = bit5_result_ = bit3_result_ = a_;
|
|
parity_overflow_flag_ = 0;
|
|
set_parity(a_);
|
|
break;
|
|
|
|
#undef set_parity
|
|
|
|
case MicroOp::TestNZ: if(!zero_result_) { move_to_next_program(); checkSchedule(); } break;
|
|
case MicroOp::TestZ: if(zero_result_) { move_to_next_program(); checkSchedule(); } break;
|
|
case MicroOp::TestNC: if(carry_flag_) { move_to_next_program(); checkSchedule(); } break;
|
|
case MicroOp::TestC: if(!carry_flag_) { move_to_next_program(); checkSchedule(); } break;
|
|
case MicroOp::TestPO: if(parity_overflow_flag_) { move_to_next_program(); checkSchedule(); } break;
|
|
case MicroOp::TestPE: if(!parity_overflow_flag_) { move_to_next_program(); checkSchedule(); } break;
|
|
case MicroOp::TestP: if(sign_result_ & 0x80) { move_to_next_program(); checkSchedule(); } break;
|
|
case MicroOp::TestM: if(!(sign_result_ & 0x80)) { move_to_next_program(); checkSchedule(); } break;
|
|
|
|
default:
|
|
printf("Unhandled Z80 operation %d\n", operation->type);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*!
|
|
Called to announce the end of a run_for_cycles period, allowing deferred work to take place.
|
|
|
|
Users of the Z80 template may override this.
|
|
*/
|
|
void flush() {}
|
|
|
|
int perform_machine_cycle(const MachineCycle *cycle) {
|
|
return 0;
|
|
}
|
|
|
|
/*!
|
|
Gets the flags register.
|
|
|
|
@see set_flags
|
|
|
|
@returns The current value of the flags register.
|
|
*/
|
|
uint8_t get_flags() {
|
|
return
|
|
(sign_result_ & Flag::Sign) |
|
|
(zero_result_ ? 0 : Flag::Zero) |
|
|
(bit5_result_ & Flag::Bit5) |
|
|
half_carry_flag_ |
|
|
(bit3_result_ & Flag::Bit3) |
|
|
parity_overflow_flag_ |
|
|
subtract_flag_ |
|
|
carry_flag_;
|
|
}
|
|
|
|
/*!
|
|
Sets the flags register.
|
|
|
|
@see set_flags
|
|
|
|
@param flags The new value of the flags register.
|
|
*/
|
|
void set_flags(uint8_t flags) {
|
|
sign_result_ = flags;
|
|
zero_result_ = (flags & Flag::Zero) ^ Flag::Zero;
|
|
bit5_result_ = flags;
|
|
half_carry_flag_ = flags & Flag::HalfCarry;
|
|
bit3_result_ = flags;
|
|
parity_overflow_flag_ = flags & Flag::Parity;
|
|
subtract_flag_ = flags & Flag::Subtract;
|
|
carry_flag_ = flags & Flag::Carry;
|
|
}
|
|
|
|
/*!
|
|
Gets the value of a register.
|
|
|
|
@see set_value_of_register
|
|
|
|
@param r The register to set.
|
|
@returns The value of the register. 8-bit registers will be returned as unsigned.
|
|
*/
|
|
uint16_t get_value_of_register(Register r) {
|
|
switch (r) {
|
|
case Register::ProgramCounter: return pc_.full;
|
|
case Register::StackPointer: return sp_.full;
|
|
|
|
case Register::A: return a_;
|
|
case Register::Flags: return get_flags();
|
|
case Register::AF: return (uint16_t)((a_ << 8) | get_flags());
|
|
case Register::B: return bc_.bytes.high;
|
|
case Register::C: return bc_.bytes.low;
|
|
case Register::BC: return bc_.full;
|
|
case Register::D: return de_.bytes.high;
|
|
case Register::E: return de_.bytes.low;
|
|
case Register::DE: return de_.full;
|
|
case Register::H: return hl_.bytes.high;
|
|
case Register::L: return hl_.bytes.low;
|
|
case Register::HL: return hl_.full;
|
|
|
|
case Register::ADash: return afDash_.bytes.high;
|
|
case Register::FlagsDash: return afDash_.bytes.low;
|
|
case Register::AFDash: return afDash_.full;
|
|
case Register::BDash: return bcDash_.bytes.high;
|
|
case Register::CDash: return bcDash_.bytes.low;
|
|
case Register::BCDash: return bcDash_.full;
|
|
case Register::DDash: return deDash_.bytes.high;
|
|
case Register::EDash: return deDash_.bytes.low;
|
|
case Register::DEDash: return deDash_.full;
|
|
case Register::HDash: return hlDash_.bytes.high;
|
|
case Register::LDash: return hlDash_.bytes.low;
|
|
case Register::HLDash: return hlDash_.full;
|
|
|
|
case Register::IXh: return ix_.bytes.high;
|
|
case Register::IXl: return ix_.bytes.low;
|
|
case Register::IX: return ix_.full;
|
|
case Register::IYh: return iy_.bytes.high;
|
|
case Register::IYl: return iy_.bytes.low;
|
|
case Register::IY: return iy_.full;
|
|
|
|
case Register::R: return r_;
|
|
case Register::I: return i_;
|
|
|
|
default: return 0;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
Sets the value of a register.
|
|
|
|
@see get_value_of_register
|
|
|
|
@param r The register to set.
|
|
@param value The value to set. If the register is only 8 bit, the value will be truncated.
|
|
*/
|
|
void set_value_of_register(Register r, uint16_t value) {
|
|
switch (r) {
|
|
case Register::ProgramCounter: pc_.full = value; break;
|
|
case Register::StackPointer: sp_.full = value; break;
|
|
|
|
case Register::A: a_ = (uint8_t)value; break;
|
|
case Register::AF: a_ = (uint8_t)(value >> 8); // deliberate fallthrough...
|
|
case Register::Flags: set_flags((uint8_t)value); break;
|
|
|
|
case Register::B: bc_.bytes.high = (uint8_t)value; break;
|
|
case Register::C: bc_.bytes.low = (uint8_t)value; break;
|
|
case Register::BC: bc_.full = value; break;
|
|
case Register::D: de_.bytes.high = (uint8_t)value; break;
|
|
case Register::E: de_.bytes.low = (uint8_t)value; break;
|
|
case Register::DE: de_.full = value; break;
|
|
case Register::H: hl_.bytes.high = (uint8_t)value; break;
|
|
case Register::L: hl_.bytes.low = (uint8_t)value; break;
|
|
case Register::HL: hl_.full = value; break;
|
|
|
|
case Register::ADash: afDash_.bytes.high = (uint8_t)value; break;
|
|
case Register::FlagsDash: afDash_.bytes.low = (uint8_t)value; break;
|
|
case Register::AFDash: afDash_.full = value; break;
|
|
case Register::BDash: bcDash_.bytes.high = (uint8_t)value; break;
|
|
case Register::CDash: bcDash_.bytes.low = (uint8_t)value; break;
|
|
case Register::BCDash: bcDash_.full = value; break;
|
|
case Register::DDash: deDash_.bytes.high = (uint8_t)value; break;
|
|
case Register::EDash: deDash_.bytes.low = (uint8_t)value; break;
|
|
case Register::DEDash: deDash_.full = value; break;
|
|
case Register::HDash: hlDash_.bytes.high = (uint8_t)value; break;
|
|
case Register::LDash: hlDash_.bytes.low = (uint8_t)value; break;
|
|
case Register::HLDash: hlDash_.full = value; break;
|
|
|
|
case Register::IXh: ix_.bytes.high = (uint8_t)value; break;
|
|
case Register::IXl: ix_.bytes.low = (uint8_t)value; break;
|
|
case Register::IX: ix_.full = value; break;
|
|
case Register::IYh: iy_.bytes.high = (uint8_t)value; break;
|
|
case Register::IYl: iy_.bytes.low = (uint8_t)value; break;
|
|
case Register::IY: iy_.full = value; break;
|
|
|
|
case Register::R: r_ = (uint8_t)value; break;
|
|
case Register::I: i_ = (uint8_t)value; break;
|
|
|
|
default: break;
|
|
}
|
|
}
|
|
};
|
|
|
|
}
|
|
}
|
|
|
|
#endif /* Z80_hpp */
|