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https://github.com/TomHarte/CLK.git
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684 lines
21 KiB
C++
684 lines
21 KiB
C++
//
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// Chipset.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 22/07/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "Chipset.hpp"
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//#define NDEBUG
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#define LOG_PREFIX "[Amiga chipset] "
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#include "../../Outputs/Log.hpp"
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#include <cassert>
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using namespace Amiga;
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namespace {
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enum InterruptFlag: uint16_t {
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SerialPortTransmit = 1 << 0,
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DiskBlock = 1 << 1,
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Software = 1 << 2,
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IOPortsAndTimers = 1 << 3, // i.e. CIA A.
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Copper = 1 << 4,
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VerticalBlank = 1 << 5,
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Blitter = 1 << 6,
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AudioChannel0 = 1 << 7,
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AudioChannel1 = 1 << 8,
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AudioChannel2 = 1 << 9,
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AudioChannel3 = 1 << 10,
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SerialPortReceive = 1 << 11,
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DiskSyncMatch = 1 << 12,
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External = 1 << 13, // i.e. CIA B.
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};
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}
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Chipset::Chipset(uint16_t *ram, size_t size) :
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blitter_(ram, size),
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copper_(*this, ram, size),
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crt_(908, 4, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red4Green4Blue4) {
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}
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Chipset::Changes Chipset::run_for(HalfCycles length) {
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return run<false>(length);
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}
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Chipset::Changes Chipset::run_until_cpu_slot() {
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return run<true>();
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}
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void Chipset::set_cia_interrupts(bool cia_a, bool cia_b) {
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// TODO: are these really latched, or are they active live?
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if(cia_a || cia_b) {
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interrupt_requests_ |=
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(cia_a ? InterruptFlag::IOPortsAndTimers : 0) |
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(cia_b ? InterruptFlag::External : 0);
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update_interrupts();
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}
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}
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bool Chipset::Copper::advance(uint16_t position) {
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switch(state_) {
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default: return false;
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case State::Waiting:
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// TODO: blitter-finished bit.
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if((position & position_mask_) >= instruction_[0]) {
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state_ = State::FetchFirstWord;
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}
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return false;
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case State::FetchFirstWord:
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instruction_[0] = ram_[address_ & ram_mask_];
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++address_;
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state_ = State::FetchSecondWord;
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break;
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case State::FetchSecondWord: {
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const bool should_skip_move = skip_next_;
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skip_next_ = false;
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instruction_[1] = ram_[address_ & ram_mask_];
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++address_;
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if(!(instruction_[0] & 1)) {
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// A MOVE.
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if(!should_skip_move) {
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// Stop if this move would be a privilege violation.
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instruction_[0] &= 0x1fe;
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if((instruction_[0] < 0x10) || (instruction_[0] < 0x20 && !(control_&1))) {
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LOG("Invalid Copper MOVE to " << PADHEX(4) << instruction_[0] << "; stopping");
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state_ = State::Stopped;
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break;
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}
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// Construct a 68000-esque Microcycle in order to be able to perform the access.
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CPU::MC68000::Microcycle cycle;
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cycle.operation = CPU::MC68000::Microcycle::SelectWord;
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uint32_t full_address = instruction_[0];
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CPU::RegisterPair16 data = instruction_[1];
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cycle.address = &full_address;
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cycle.value = &data;
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chipset_.perform(cycle);
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}
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// Roll onto the next command.
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state_ = State::FetchFirstWord;
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break;
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}
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// Prepare for a position comparison.
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position_mask_ = 0x8001 | (instruction_[1] & 0x7ffe);
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instruction_[0] &= position_mask_;
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if(!(instruction_[1] & 1)) {
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// A WAIT. Just note that this is now waiting; the proper test
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// will be applied from the next potential `advance` onwards.
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state_ = State::Waiting;
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break;
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}
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// Neither a WAIT nor a MOVE => a SKIP.
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// TODO: blitter-finished bit.
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skip_next_ = (position & position_mask_) >= instruction_[0];
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state_ = State::FetchFirstWord;
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} break;
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}
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return true;
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}
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template <int cycle> void Chipset::output() {
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// Notes to self on guesses below:
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//
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// Hardware stop is at 0x18;
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// 12/64 * 227 = 42.5625
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//
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// "However, horizontal blanking actually limits the displayable
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// video to 368 low resolution pixel"
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//
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// => 184 windows out of 227 are visible, which concurs.
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//
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// A complete from-thin-air guess:
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//
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// 7 cycles blank;
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// 17 cycles sync;
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// 3 cycles blank;
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// 9 cycles colour burst;
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// 7 cycles blank.
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constexpr int blank1 = 7;
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constexpr int sync = 17 + blank1;
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constexpr int blank2 = 3 + sync;
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constexpr int burst = 9 + blank2;
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constexpr int blank3 = 7 + burst;
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static_assert(blank3 == 43);
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#define LINK(location, action, length) \
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if(cycle == (location)) { \
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crt_.action((length) * 4); \
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}
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if(y_ < vertical_blank_height_) {
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// Put three lines of sync at the centre of the vertical blank period.
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// Offset by half a line if interlaced and on an odd frame.
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const int midline = vertical_blank_height_ >> 1;
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if(frame_height_ & 1) {
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if(y_ < midline - 1 || y_ > midline + 2) {
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(line_length_ - 1, output_blank, line_length_ - 1 - sync);
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} else if(y_ == midline - 1) {
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LINK(113, output_blank, 113);
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LINK(line_length_ - 1, output_sync, line_length_ - 1 - 113);
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} else if(y_ == midline + 2) {
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LINK(113, output_sync, 113);
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LINK(line_length_ - 1, output_blank, line_length_ - 1 - 113);
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} else {
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LINK(blank1, output_sync, blank1);
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LINK(sync, output_blank, sync - blank1);
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LINK(line_length_ - 1, output_sync, line_length_ - 1 - sync);
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}
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} else {
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if(y_ < midline - 1 || y_ > midline + 1) {
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(line_length_ - 1, output_blank, line_length_ - 1 - sync);
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} else {
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LINK(blank1, output_sync, blank1);
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LINK(sync, output_blank, sync - blank1);
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LINK(line_length_ - 1, output_sync, line_length_ - 1 - sync);
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}
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}
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} else {
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// Output the correct sequence of blanks, syncs and burst atomically.
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(blank2, output_blank, blank2 - sync);
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LINK(burst, output_default_colour_burst, burst - blank2); // TODO: only if colour enabled.
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LINK(blank3, output_blank, blank3 - burst);
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// Output colour 0 to fill the rest of the line; Kickstart uses this
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// colour to post the error code. TODO: actual pixels, etc.
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if(cycle == line_length_ - 1) {
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uint16_t *const pixels = reinterpret_cast<uint16_t *>(crt_.begin_data(1));
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if(pixels) {
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*pixels = palette_[0];
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}
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crt_.output_data((cycle - blank3) * 4, 1);
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}
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}
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#undef LINK
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}
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template <int cycle, bool stop_if_cpu> bool Chipset::perform_cycle() {
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// TODO: actual CPU scheduling.
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if constexpr (stop_if_cpu) {
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return true;
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}
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if constexpr (cycle & 1) {
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// Odd slot priority is:
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//
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// 1. Copper, if interested.
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// 2. Bitplane.
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// 3. Blitter.
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// 4. CPU.
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if((dma_control_ & 0x280) == 0x280) {
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if(copper_.advance(uint16_t(((y_ & 0xff) << 8) | (cycle & 0xfe)))) {
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return false;
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}
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} else {
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copper_.stop();
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}
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} else {
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// Even slot use/priority:
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//
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// 1. Bitplane fetches.
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// 2. Disk, then audio, then sprites depending on region.
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// 3. Blitter.
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// 4. CPU.
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}
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return false;
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}
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template <bool stop_on_cpu> int Chipset::advance_slots(int first_slot, int last_slot) {
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if(first_slot == last_slot) {
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return -1;
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}
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#define C(x) \
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case x: \
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if constexpr(stop_on_cpu) {\
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if(perform_cycle<x, stop_on_cpu>()) {\
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return x - first_slot;\
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}\
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} else {\
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perform_cycle<x, stop_on_cpu>(); \
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} \
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output<x>(); \
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if((x + 1) == last_slot) break; \
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[[fallthrough]]
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#define C10(x) C(x); C(x+1); C(x+2); C(x+3); C(x+4); C(x+5); C(x+6); C(x+7); C(x+8); C(x+9);
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switch(first_slot) {
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C10(0); C10(10); C10(20); C10(30); C10(40);
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C10(50); C10(60); C10(70); C10(80); C10(90);
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C10(100); C10(110); C10(120); C10(130); C10(140);
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C10(150); C10(160); C10(170); C10(180); C10(190);
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C10(200); C10(210);
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C(220); C(221); C(222); C(223); C(224);
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C(225); C(226); C(227); C(228);
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default: assert(false);
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}
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#undef C
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return -1;
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}
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template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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Changes changes;
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// This code uses 'pixels' as a measure, which is equivalent to one pixel clock time,
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// or half a cycle.
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auto pixels_remaining = length.as<int>();
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// Update raster position, spooling out graphics.
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while(pixels_remaining) {
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// Determine number of pixels left on this line.
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const int line_pixels = std::min(pixels_remaining, (line_length_ * 4) - line_cycle_);
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const int start_slot = line_cycle_ >> 2;
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const int end_slot = (line_cycle_ + line_pixels) >> 2;
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const int actual_slots = advance_slots<stop_on_cpu>(start_slot, end_slot);
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if(actual_slots >= 0) {
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// TODO: abbreviate run, prior to adding to totals below.
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assert(false);
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}
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line_cycle_ += line_pixels;
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pixels_remaining -= line_pixels;
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// Advance intraline counter and possibly ripple upwards into
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// lines and fields.
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if(line_cycle_ == (line_length_ * 4)) {
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++changes.hsyncs;
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line_cycle_ = 0;
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++y_;
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if(y_ == frame_height_) {
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++changes.vsyncs;
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interrupt_requests_ |= InterruptFlag::VerticalBlank;
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update_interrupts();
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y_ = 0;
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// TODO: the manual is vague on when this happens. Try to find out.
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copper_.reload(0);
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}
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}
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assert(line_cycle_ < line_length_ * 4);
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}
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changes.interrupt_level = interrupt_level_;
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changes.duration = length;
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return changes;
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}
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void Chipset::update_interrupts() {
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interrupt_level_ = 0;
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const uint16_t enabled_requests = interrupt_enable_ & interrupt_requests_ & 0x3fff;
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if(enabled_requests && (interrupt_enable_ & 0x4000)) {
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if(enabled_requests & (InterruptFlag::External)) {
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interrupt_level_ = 6;
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} else if(enabled_requests & (InterruptFlag::SerialPortReceive | InterruptFlag::DiskSyncMatch)) {
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interrupt_level_ = 5;
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} else if(enabled_requests & (InterruptFlag::AudioChannel0 | InterruptFlag::AudioChannel1 | InterruptFlag::AudioChannel2 | InterruptFlag::AudioChannel3)) {
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interrupt_level_ = 4;
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} else if(enabled_requests & (InterruptFlag::Copper | InterruptFlag::VerticalBlank | InterruptFlag::Blitter)) {
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interrupt_level_ = 3;
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} else if(enabled_requests & (InterruptFlag::IOPortsAndTimers)) {
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interrupt_level_ = 2;
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} else if(enabled_requests & (InterruptFlag::SerialPortTransmit | InterruptFlag::DiskBlock | InterruptFlag::Software)) {
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interrupt_level_ = 1;
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}
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}
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}
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void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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using Microcycle = CPU::MC68000::Microcycle;
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#define RW(address) address | ((cycle.operation & Microcycle::Read) << 12)
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#define Read(address) address | (Microcycle::Read << 12)
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#define Write(address) address
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#define ApplySetClear(target) { \
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const uint16_t value = cycle.value16(); \
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if(value & 0x8000) { \
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target |= (value & 0x7fff); \
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} else { \
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target &= ~(value & 0x7fff); \
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} \
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}
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const uint32_t register_address = *cycle.address & 0x1fe;
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switch(RW(register_address)) {
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default:
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LOG("Unimplemented chipset " << (cycle.operation & Microcycle::Read ? "read" : "write") << " " << PADHEX(6) << *cycle.address);
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assert(false);
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break;
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// Raster position.
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case Read(0x004): {
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const uint16_t position = uint16_t(y_ >> 8);
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LOG("Read vertical position high " << PADHEX(4) << position);
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cycle.set_value16(position);
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} break;
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case Read(0x006): {
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const uint16_t position = uint16_t(((line_cycle_ << 6) & 0xff00) | (y_ & 0x00ff));
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LOG("Read position low " << PADHEX(4) << position);
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cycle.set_value16(position);
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} break;
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case Write(0x02a):
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LOG("TODO: write vertical position high " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x02c):
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LOG("TODO: write vertical position low " << PADHEX(4) << cycle.value16());
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break;
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// Joystick/mouse input.
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case Read(0x00a):
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case Read(0x00c):
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LOG("TODO: Joystick/mouse position " << PADHEX(4) << *cycle.address);
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cycle.set_value16(0x8080);
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break;
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case Write(0x034):
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LOG("TODO: pot port start");
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break;
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case Read(0x016):
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LOG("TODO: pot port read");
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cycle.set_value16(0xff00);
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break;
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// Disk DMA.
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case Write(0x020): case Write(0x022): case Write(0x024):
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case Write(0x026):
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LOG("TODO: disk DMA; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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// Refresh.
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case Write(0x028):
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LOG("TODO (maybe): refresh; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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// Serial port.
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case Write(0x030):
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LOG("TODO: serial data: " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x032):
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LOG("TODO: serial control: " << PADHEX(4) << cycle.value16());
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serial_.set_control(cycle.value16());
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break;
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// DMA management.
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case Read(0x002):
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LOG("DMA control and status read");
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cycle.set_value16(dma_control_ | blitter_.get_status());
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break;
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case Write(0x096):
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ApplySetClear(dma_control_);
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LOG("DMA control modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{dma_control_});
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break;
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// Interrupts.
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case Write(0x09a):
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ApplySetClear(interrupt_enable_);
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update_interrupts();
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LOG("Interrupt enable mask modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{interrupt_enable_});
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break;
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case Read(0x01c):
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cycle.set_value16(interrupt_enable_);
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LOG("Interrupt enable mask read: " << PADHEX(4) << interrupt_enable_);
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break;
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case Write(0x09c):
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ApplySetClear(interrupt_requests_);
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update_interrupts();
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LOG("Interrupt request modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{interrupt_requests_});
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break;
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case Read(0x01e):
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cycle.set_value16(interrupt_requests_);
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LOG("Interrupt requests read: " << PADHEX(4) << interrupt_requests_);
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break;
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// Display management.
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case Write(0x08e): {
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const uint16_t value = cycle.value16();
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display_window_start_[0] = value & 0xff;
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display_window_start_[1] = value >> 8;
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LOG("Display window start set to " << std::dec << display_window_start_[0] << ", " << display_window_start_[1]);
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} break;
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case Write(0x090): {
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const uint16_t value = cycle.value16();
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display_window_stop_[0] = 0x100 | (value & 0xff);
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display_window_stop_[1] = value >> 8;
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display_window_stop_[1] |= ((value >> 7) & 0x100) ^ 0x100;
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LOG("Display window stop set to " << std::dec << display_window_stop_[0] << ", " << display_window_stop_[1]);
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} break;
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case Write(0x092):
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fetch_window_[0] = uint16_t((cycle.value16() & 0xfc) << 1);
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LOG("Fetch window start set to " << std::dec << fetch_window_[0]);
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break;
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case Write(0x094):
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fetch_window_[1] = uint16_t((cycle.value16() & 0xfc) << 1);
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LOG("Fetch window stop set to " << std::dec << fetch_window_[1]);
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break;
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// Bitplanes.
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case Write(0x0e0): case Write(0x0e2):
|
|
case Write(0x0e4): case Write(0x0e6):
|
|
case Write(0x0e8): case Write(0x0ea):
|
|
case Write(0x0ec): case Write(0x0ee):
|
|
case Write(0x0f0): case Write(0x0f2):
|
|
case Write(0x0f4): case Write(0x0f6):
|
|
LOG("TODO: Bitplane pointer; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
|
|
break;
|
|
|
|
case Write(0x100):
|
|
case Write(0x102):
|
|
case Write(0x104):
|
|
case Write(0x106):
|
|
LOG("TODO: Bitplane control; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
|
|
break;
|
|
|
|
case Write(0x108):
|
|
case Write(0x10a):
|
|
LOG("TODO: Bitplane modulo; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
|
|
break;
|
|
|
|
case Write(0x110):
|
|
case Write(0x112):
|
|
case Write(0x114):
|
|
case Write(0x116):
|
|
case Write(0x118):
|
|
case Write(0x11a):
|
|
LOG("TODO: Bitplane data; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
|
|
break;
|
|
|
|
case Read(0x110): case Read(0x112): case Read(0x114): case Read(0x116):
|
|
case Read(0x118): case Read(0x11a):
|
|
cycle.set_value16(0xffff);
|
|
LOG("Invalid read at " << PADHEX(6) << *cycle.address);
|
|
break;
|
|
|
|
// Blitter.
|
|
case Write(0x040): blitter_.set_control(0, cycle.value16()); break;
|
|
case Write(0x042): blitter_.set_control(1, cycle.value16()); break;
|
|
case Write(0x044): blitter_.set_first_word_mask(cycle.value16()); break;
|
|
case Write(0x046): blitter_.set_last_word_mask(cycle.value16()); break;
|
|
|
|
case Write(0x048): blitter_.set_pointer(2, 16, cycle.value16()); break;
|
|
case Write(0x04a): blitter_.set_pointer(2, 0, cycle.value16()); break;
|
|
case Write(0x04c): blitter_.set_pointer(1, 16, cycle.value16()); break;
|
|
case Write(0x04e): blitter_.set_pointer(1, 0, cycle.value16()); break;
|
|
case Write(0x050): blitter_.set_pointer(0, 16, cycle.value16()); break;
|
|
case Write(0x052): blitter_.set_pointer(0, 0, cycle.value16()); break;
|
|
case Write(0x054): blitter_.set_pointer(3, 16, cycle.value16()); break;
|
|
case Write(0x056): blitter_.set_pointer(3, 0, cycle.value16()); break;
|
|
|
|
case Write(0x058): blitter_.set_size(cycle.value16()); break;
|
|
case Write(0x05a): blitter_.set_minterms(cycle.value16()); break;
|
|
case Write(0x05c): blitter_.set_vertical_size(cycle.value16()); break;
|
|
case Write(0x05e): blitter_.set_horizontal_size(cycle.value16()); break;
|
|
|
|
case Write(0x060): blitter_.set_modulo(2, cycle.value16()); break;
|
|
case Write(0x062): blitter_.set_modulo(1, cycle.value16()); break;
|
|
case Write(0x064): blitter_.set_modulo(0, cycle.value16()); break;
|
|
case Write(0x066): blitter_.set_modulo(3, cycle.value16()); break;
|
|
|
|
case Write(0x070): blitter_.set_data(2, cycle.value16()); break;
|
|
case Write(0x072): blitter_.set_data(1, cycle.value16()); break;
|
|
case Write(0x074): blitter_.set_data(0, cycle.value16()); break;
|
|
|
|
// Paula.
|
|
case Write(0x09e):
|
|
case Write(0x0a0): case Write(0x0a2): case Write(0x0a4): case Write(0x0a6):
|
|
case Write(0x0a8): case Write(0x0aa):
|
|
case Write(0x0b0): case Write(0x0b2): case Write(0x0b4): case Write(0x0b6):
|
|
case Write(0x0b8): case Write(0x0ba):
|
|
case Write(0x0c0): case Write(0x0c2): case Write(0x0c4): case Write(0x0c6):
|
|
case Write(0x0c8): case Write(0x0ca):
|
|
case Write(0x0d0): case Write(0x0d2): case Write(0x0d4): case Write(0x0d6):
|
|
case Write(0x0d8): case Write(0x0da):
|
|
LOG("TODO: Paula write " << PADHEX(2) << (*cycle.address & 0xff) << " " << PADHEX(4) << cycle.value16());
|
|
break;
|
|
|
|
// Copper.
|
|
case Write(0x02e):
|
|
LOG("Coprocessor control " << PADHEX(4) << cycle.value16());
|
|
copper_.set_control(cycle.value16());
|
|
break;
|
|
case Write(0x080):
|
|
LOG("Coprocessor first location register high " << PADHEX(4) << cycle.value16());
|
|
copper_.set_address<0, 16>(cycle.value16());
|
|
break;
|
|
case Write(0x082):
|
|
LOG("Coprocessor first location register low " << PADHEX(4) << cycle.value16());
|
|
copper_.set_address<0, 0>(cycle.value16());
|
|
break;
|
|
case Write(0x084):
|
|
LOG("Coprocessor second location register high " << PADHEX(4) << cycle.value16());
|
|
copper_.set_address<1, 16>(cycle.value16());
|
|
break;
|
|
case Write(0x086):
|
|
LOG("Coprocessor second location register low " << PADHEX(4) << cycle.value16());
|
|
copper_.set_address<1, 0>(cycle.value16());
|
|
break;
|
|
case Write(0x088): case Read(0x088):
|
|
LOG("Coprocessor restart at first location");
|
|
copper_.reload(0);
|
|
break;
|
|
case Write(0x08a): case Read(0x08a):
|
|
LOG("Coprocessor restart at second location");
|
|
copper_.reload(1);
|
|
break;
|
|
case Write(0x08c):
|
|
LOG("TODO: coprocessor instruction fetch identity " << PADHEX(4) << cycle.value16());
|
|
break;
|
|
|
|
// Sprites.
|
|
#define Sprite(index, pointer, position) \
|
|
case Write(pointer + 0): sprites_[index].set_pointer(16, cycle.value16()); break; \
|
|
case Write(pointer + 2): sprites_[index].set_pointer(0, cycle.value16()); break; \
|
|
case Write(position + 0): sprites_[index].set_start_position(cycle.value16()); break; \
|
|
case Write(position + 2): sprites_[index].set_stop_and_control(cycle.value16()); break; \
|
|
case Write(position + 4): sprites_[index].set_image_data(0, cycle.value16()); break; \
|
|
case Write(position + 6): sprites_[index].set_image_data(1, cycle.value16()); break;
|
|
|
|
Sprite(0, 0x120, 0x140);
|
|
Sprite(1, 0x124, 0x148);
|
|
Sprite(2, 0x128, 0x150);
|
|
Sprite(3, 0x12c, 0x158);
|
|
Sprite(4, 0x130, 0x160);
|
|
Sprite(5, 0x134, 0x168);
|
|
Sprite(6, 0x138, 0x170);
|
|
Sprite(7, 0x13c, 0x178);
|
|
|
|
#undef Sprite
|
|
|
|
// Colour palette.
|
|
case Write(0x180): case Write(0x182): case Write(0x184): case Write(0x186):
|
|
case Write(0x188): case Write(0x18a): case Write(0x18c): case Write(0x18e):
|
|
case Write(0x190): case Write(0x192): case Write(0x194): case Write(0x196):
|
|
case Write(0x198): case Write(0x19a): case Write(0x19c): case Write(0x19e):
|
|
case Write(0x1a0): case Write(0x1a2): case Write(0x1a4): case Write(0x1a6):
|
|
case Write(0x1a8): case Write(0x1aa): case Write(0x1ac): case Write(0x1ae):
|
|
case Write(0x1b0): case Write(0x1b2): case Write(0x1b4): case Write(0x1b6):
|
|
case Write(0x1b8): case Write(0x1ba): case Write(0x1bc): case Write(0x1be): {
|
|
LOG("Colour palette; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
|
|
|
|
uint8_t *const entry = reinterpret_cast<uint8_t *>(&palette_[(register_address - 0x180) >> 1]);
|
|
entry[0] = cycle.value8_high();
|
|
entry[1] = cycle.value8_low();
|
|
} break;
|
|
}
|
|
|
|
#undef ApplySetClear
|
|
|
|
#undef Write
|
|
#undef Read
|
|
#undef RW
|
|
}
|
|
|
|
// MARK: - Sprites.
|
|
|
|
void Chipset::Sprite::set_pointer(int shift, uint16_t value) {
|
|
LOG("Sprite pointer with shift " << std::dec << shift << " to " << PADHEX(4) << value);
|
|
}
|
|
|
|
void Chipset::Sprite::set_start_position(uint16_t value) {
|
|
LOG("Sprite start position " << PADHEX(4) << value);
|
|
}
|
|
|
|
void Chipset::Sprite::set_stop_and_control(uint16_t value) {
|
|
LOG("Sprite stop and control " << PADHEX(4) << value);
|
|
}
|
|
|
|
void Chipset::Sprite::set_image_data(int slot, uint16_t value) {
|
|
LOG("Sprite image data " << slot << " to " << PADHEX(4) << value);
|
|
}
|
|
|
|
// MARK: - CRT connection.
|
|
|
|
void Chipset::set_scan_target(Outputs::Display::ScanTarget *scan_target) {
|
|
crt_.set_scan_target(scan_target);
|
|
}
|
|
|
|
Outputs::Display::ScanStatus Chipset::get_scaled_scan_status() const {
|
|
return crt_.get_scaled_scan_status();
|
|
}
|
|
|
|
void Chipset::set_display_type(Outputs::Display::DisplayType type) {
|
|
crt_.set_display_type(type);
|
|
}
|
|
|
|
Outputs::Display::DisplayType Chipset::get_display_type() const {
|
|
return crt_.get_display_type();
|
|
}
|