mirror of
https://github.com/TomHarte/CLK.git
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320 lines
7.9 KiB
C++
320 lines
7.9 KiB
C++
//
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// DMA.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 21/11/2023.
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// Copyright © 2023 Thomas Harte. All rights reserved.
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//
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#ifndef DMA_hpp
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#define DMA_hpp
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#include "../../Numeric/RegisterSizes.hpp"
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#include "Memory.hpp"
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#include <array>
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namespace PCCompatible {
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enum class AccessResult {
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Accepted,
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AcceptedWithEOP,
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NotAccepted,
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};
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class i8237 {
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public:
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//
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// CPU-facing interface.
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//
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template <int address>
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void write(uint8_t value) {
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// printf("DMA: Write %02x to %d\n", value, address);
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switch(address) {
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default: {
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constexpr int channel = (address >> 1) & 3;
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constexpr bool is_count = address & 1;
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next_access_low_ ^= true;
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if(next_access_low_) {
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if constexpr (is_count) {
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channels_[channel].count.halves.high = value;
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} else {
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channels_[channel].address.halves.high = value;
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}
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} else {
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if constexpr (is_count) {
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channels_[channel].count.halves.low = value;
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} else {
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channels_[channel].address.halves.low = value;
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}
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}
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} break;
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case 0x8: set_command(value); break;
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case 0x9: set_reset_request(value); break;
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case 0xa: set_reset_mask(value); break;
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case 0xb: set_mode(value); break;
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case 0xc: flip_flop_reset(); break;
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case 0xd: master_reset(); break;
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case 0xe: mask_reset(); break;
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case 0xf: set_mask(value); break;
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}
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}
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template <int address>
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uint8_t read() {
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// printf("DMA: Read %d\n", address);
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switch(address) {
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default: {
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constexpr int channel = (address >> 1) & 3;
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constexpr bool is_count = address & 1;
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next_access_low_ ^= true;
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if(next_access_low_) {
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if constexpr (is_count) {
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return channels_[channel].count.halves.high;
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} else {
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return channels_[channel].address.halves.high;
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}
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} else {
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if constexpr (is_count) {
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return channels_[channel].count.halves.low;
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} else {
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return channels_[channel].address.halves.low;
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}
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}
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} break;
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case 0x8: return status(); break;
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case 0xd: return temporary_register(); break;
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}
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}
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//
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// Interface for reading/writing via DMA.
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//
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/// Provides the next target address for @c channel if performing either a write (if @c is_write is @c true) or read (otherwise).
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///
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/// @returns A combined address and @c AccessResult.
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std::pair<uint16_t, AccessResult> access(size_t channel, bool is_write) {
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if(is_write && channels_[channel].transfer != Channel::Transfer::Write) {
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return std::make_pair(0, AccessResult::NotAccepted);
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}
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if(!is_write && channels_[channel].transfer != Channel::Transfer::Read) {
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return std::make_pair(0, AccessResult::NotAccepted);
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}
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const auto address = channels_[channel].address.full;
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channels_[channel].address.full += channels_[channel].address_decrement ? -1 : 1;
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--channels_[channel].count.full;
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const bool was_complete = channels_[channel].transfer_complete;
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channels_[channel].transfer_complete = (channels_[channel].count.full == 0xffff);
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if(channels_[channel].transfer_complete) {
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// TODO: _something_ with mode.
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}
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auto result = AccessResult::Accepted;
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if(!was_complete && channels_[channel].transfer_complete) {
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result = AccessResult::AcceptedWithEOP;
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}
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return std::make_pair(address, result);
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}
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void set_complete(size_t channel) {
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channels_[channel].transfer_complete = true;
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}
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private:
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uint8_t status() {
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const uint8_t result =
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(channels_[0].transfer_complete ? 0x01 : 0x00) |
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(channels_[1].transfer_complete ? 0x02 : 0x00) |
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(channels_[2].transfer_complete ? 0x04 : 0x00) |
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(channels_[3].transfer_complete ? 0x08 : 0x00) |
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(channels_[0].request ? 0x10 : 0x00) |
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(channels_[1].request ? 0x20 : 0x00) |
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(channels_[2].request ? 0x40 : 0x00) |
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(channels_[3].request ? 0x80 : 0x00);
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for(auto &channel : channels_) {
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channel.transfer_complete = false;
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}
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// printf("DMA: status is %02x\n", result);
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return result;
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}
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uint8_t temporary_register() const {
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// Not actually implemented, so...
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return 0xff;
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}
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void flip_flop_reset() {
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// printf("DMA: Flip flop reset\n");
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next_access_low_ = true;
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}
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void mask_reset() {
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// printf("DMA: Mask reset\n");
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for(auto &channel : channels_) {
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channel.mask = false;
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}
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}
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void master_reset() {
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// printf("DMA: Master reset\n");
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flip_flop_reset();
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for(auto &channel : channels_) {
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channel.mask = true;
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channel.transfer_complete = false;
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channel.request = false;
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}
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// This is a bit of a hack; DMA channel 0 is supposed to be linked to the PIT,
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// performing DRAM refresh. It isn't yet. So hack this, and hack that.
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channels_[0].transfer_complete = true;
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}
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void set_reset_mask(uint8_t value) {
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// printf("DMA: Set/reset mask %02x\n", value);
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channels_[value & 3].mask = value & 4;
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}
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void set_reset_request(uint8_t value) {
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// printf("DMA: Set/reset request %02x\n", value);
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channels_[value & 3].request = value & 4;
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}
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void set_mask(uint8_t value) {
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// printf("DMA: Set mask %02x\n", value);
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channels_[0].mask = value & 1;
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channels_[1].mask = value & 2;
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channels_[2].mask = value & 4;
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channels_[3].mask = value & 8;
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}
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void set_mode(uint8_t value) {
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// printf("DMA: Set mode %02x\n", value);
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channels_[value & 3].transfer = Channel::Transfer((value >> 2) & 3);
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channels_[value & 3].autoinitialise = value & 0x10;
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channels_[value & 3].address_decrement = value & 0x20;
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channels_[value & 3].mode = Channel::Mode(value >> 6);
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}
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void set_command(uint8_t value) {
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// printf("DMA: Set command %02x\n", value);
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enable_memory_to_memory_ = value & 0x01;
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enable_channel0_address_hold_ = value & 0x02;
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enable_controller_ = value & 0x04;
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compressed_timing_ = value & 0x08;
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rotating_priority_ = value & 0x10;
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extended_write_selection_ = value & 0x20;
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dreq_active_low_ = value & 0x40;
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dack_sense_active_high_ = value & 0x80;
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}
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// Low/high byte latch.
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bool next_access_low_ = true;
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// Various fields set by the command register.
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bool enable_memory_to_memory_ = false;
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bool enable_channel0_address_hold_ = false;
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bool enable_controller_ = false;
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bool compressed_timing_ = false;
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bool rotating_priority_ = false;
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bool extended_write_selection_ = false;
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bool dreq_active_low_ = false;
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bool dack_sense_active_high_ = false;
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// Per-channel state.
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struct Channel {
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bool mask = false;
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enum class Transfer {
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Verify, Write, Read, Invalid
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} transfer = Transfer::Verify;
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bool autoinitialise = false;
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bool address_decrement = false;
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enum class Mode {
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Demand, Single, Block, Cascade
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} mode = Mode::Demand;
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bool request = false;
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bool transfer_complete = false;
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CPU::RegisterPair16 address, count;
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};
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std::array<Channel, 4> channels_;
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};
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class DMAPages {
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public:
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template <int index>
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void set_page(uint8_t value) {
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pages_[page_for_index(index)] = value;
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}
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template <int index>
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uint8_t page() {
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return pages_[page_for_index(index)];
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}
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uint8_t channel_page(size_t channel) {
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return pages_[channel];
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}
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private:
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uint8_t pages_[8];
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constexpr int page_for_index(int index) {
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switch(index) {
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case 7: return 0;
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case 3: return 1;
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case 1: return 2;
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case 2: return 3;
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default:
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case 0: return 4;
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case 4: return 5;
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case 5: return 6;
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case 6: return 7;
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}
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}
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};
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class DMA {
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public:
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i8237 controller;
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DMAPages pages;
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// Memory is set posthoc to resolve a startup time.
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void set_memory(Memory *memory) {
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memory_ = memory;
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}
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// TODO: this permits only 8-bit DMA. Fix that.
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AccessResult write(size_t channel, uint8_t value) {
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auto access = controller.access(channel, true);
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if(access.second == AccessResult::NotAccepted) {
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return access.second;
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}
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const uint32_t address = uint32_t(pages.channel_page(channel) << 16) | access.first;
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*memory_->at(address) = value;
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return access.second;
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}
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private:
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Memory *memory_;
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};
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}
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#endif /* DMA_hpp */
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