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120 lines
3.2 KiB
C++
120 lines
3.2 KiB
C++
//
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// 65816Implementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 23/09/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#ifndef WDC65816Implementation_h
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#define WDC65816Implementation_h
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enum MicroOp: uint8_t {
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/// Fetches a byte from the program counter to the instruction buffer and increments the program counter.
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CycleFetchIncrementPC,
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/// Fetches a byte from the program counter without incrementing it, and throws it away.
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CycleFetchPC,
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/// Fetches a byte from the data address to the data buffer.
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CycleFetchData,
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/// Fetches a byte from the data address to the data buffer and increments the data address.
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CycleFetchIncrementData,
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/// Stores a byte from the data buffer.
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CycleStoreData,
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/// Stores a byte to the data address from the data buffer and increments the data address.
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CycleStoreIncrementData,
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/// Stores a byte to the data address from the data buffer and decrements the data address.
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CycleStoreDecrementData,
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/// Pushes a single byte from the data buffer to the stack.
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CyclePush,
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/// Fetches from the current stack location and throws the result away.
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CycleAccessStack,
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/// Sets the data address by copying the final two bytes of the instruction buffer.
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OperationConstructAbsolute,
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/// Sets the data address to the result of (a, x).
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/// TODO: explain better once implemented.
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OperationConstructAbsoluteIndexedIndirect,
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/// Performs whatever operation goes with this program.
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OperationPerform,
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/// Copies the current program counter to the data buffer.
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OperationCopyPCToData,
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/// Copies the current PBR to the data buffer.
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OperationCopyPBRToData,
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/// Complete this set of micr-ops.
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OperationMoveToNextProgram
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};
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enum Operation: uint8_t {
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// These perform the named operation using the value in the data buffer;
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// they are implicitly AccessType::Read.
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ADC, AND, BIT, CMP, CPX, CPY, EOR, ORA, SBC,
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// These load the respective register from the data buffer;
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// they are implicitly AccessType::Read.
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LDA, LDX, LDY,
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// These move the respective register (or value) to the data buffer;
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// they are implicitly AccessType::Write.
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STA, STX, STY, STZ,
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/// Loads the PC with the operand from the data buffer.
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JMP,
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/// Loads the PC and PBR with the operand from the data buffer.
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JML,
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/// Loads the PC with the operand from the data buffer, replacing
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/// it with the old PC.
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JSR,
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/// Loads the PC and the PBR with the operand from the data buffer,
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/// replacing it with the old PC (and only the PC; PBR not included).
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JSL,
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};
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class ProcessorStorageConstructor;
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class ProcessorStorage {
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public:
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ProcessorStorage();
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struct Instruction {
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size_t program_offset;
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Operation operation;
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};
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Instruction instructions[512 + 3]; // Arranged as:
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// 256 entries: emulation-mode instructions;
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// 256 entries: 16-bit instructions;
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// reset
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// NMI
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// IRQ
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private:
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friend ProcessorStorageConstructor;
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// Registers.
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RegisterPair16 a_;
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RegisterPair16 x_, y_;
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uint16_t pc_, s_;
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// Not
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uint16_t direct_;
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// Banking registers are all stored with the relevant byte
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// shifted up bits 16–23.
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uint32_t data_bank_; // i.e. DBR.
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uint32_t program_bank_; // i.e. PBR.
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std::vector<MicroOp> micro_ops_;
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};
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#endif /* WDC65816Implementation_h */
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