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397 lines
11 KiB
C++
397 lines
11 KiB
C++
//
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// PCCompatible.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 15/11/2023.
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// Copyright © 2023 Thomas Harte. All rights reserved.
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//
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#include "PCCompatible.hpp"
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#include "../../InstructionSets/x86/Decoder.hpp"
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#include "../../InstructionSets/x86/Flags.hpp"
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#include "../../InstructionSets/x86/Instruction.hpp"
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#include "../../InstructionSets/x86/Perform.hpp"
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#include "../ScanProducer.hpp"
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#include "../TimedMachine.hpp"
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namespace PCCompatible {
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struct Registers {
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public:
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static constexpr bool is_32bit = false;
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uint8_t &al() { return ax_.halves.low; }
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uint8_t &ah() { return ax_.halves.high; }
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uint16_t &ax() { return ax_.full; }
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CPU::RegisterPair16 &axp() { return ax_; }
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uint8_t &cl() { return cx_.halves.low; }
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uint8_t &ch() { return cx_.halves.high; }
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uint16_t &cx() { return cx_.full; }
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uint8_t &dl() { return dx_.halves.low; }
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uint8_t &dh() { return dx_.halves.high; }
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uint16_t &dx() { return dx_.full; }
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uint8_t &bl() { return bx_.halves.low; }
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uint8_t &bh() { return bx_.halves.high; }
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uint16_t &bx() { return bx_.full; }
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uint16_t &sp() { return sp_; }
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uint16_t &bp() { return bp_; }
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uint16_t &si() { return si_; }
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uint16_t &di() { return di_; }
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uint16_t &ip() { return ip_; }
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uint16_t &es() { return es_; }
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uint16_t &cs() { return cs_; }
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uint16_t &ds() { return ds_; }
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uint16_t &ss() { return ss_; }
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uint16_t es() const { return es_; }
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uint16_t cs() const { return cs_; }
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uint16_t ds() const { return ds_; }
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uint16_t ss() const { return ss_; }
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void reset() {
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cs_ = 0xffff;
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ip_ = 0;
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}
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private:
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CPU::RegisterPair16 ax_;
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CPU::RegisterPair16 cx_;
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CPU::RegisterPair16 dx_;
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CPU::RegisterPair16 bx_;
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uint16_t sp_;
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uint16_t bp_;
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uint16_t si_;
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uint16_t di_;
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uint16_t es_, cs_, ds_, ss_;
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uint16_t ip_;
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};
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class Segments {
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public:
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Segments(const Registers ®isters) : registers_(registers) {}
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using Source = InstructionSet::x86::Source;
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/// Posted by @c perform after any operation which *might* have affected a segment register.
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void did_update(Source segment) {
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switch(segment) {
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default: break;
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case Source::ES: es_base_ = uint32_t(registers_.es()) << 4; break;
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case Source::CS: cs_base_ = uint32_t(registers_.cs()) << 4; break;
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case Source::DS: ds_base_ = uint32_t(registers_.ds()) << 4; break;
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case Source::SS: ss_base_ = uint32_t(registers_.ss()) << 4; break;
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}
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}
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void reset() {
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did_update(Source::ES);
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did_update(Source::CS);
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did_update(Source::DS);
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did_update(Source::SS);
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}
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uint32_t es_base_, cs_base_, ds_base_, ss_base_;
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bool operator ==(const Segments &rhs) const {
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return
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es_base_ == rhs.es_base_ &&
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cs_base_ == rhs.cs_base_ &&
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ds_base_ == rhs.ds_base_ &&
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ss_base_ == rhs.ss_base_;
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}
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private:
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const Registers ®isters_;
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};
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struct Memory {
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public:
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using AccessType = InstructionSet::x86::AccessType;
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// Constructor.
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Memory(Registers ®isters, const Segments &segments) : registers_(registers), segments_(segments) {
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memory.resize(1024*1024);
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}
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//
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// Preauthorisation call-ins. Since only an 8088 is currently modelled, all accesses are implicitly authorised.
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//
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void preauthorise_stack_write([[maybe_unused]] uint32_t length) {}
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void preauthorise_stack_read([[maybe_unused]] uint32_t length) {}
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void preauthorise_read([[maybe_unused]] InstructionSet::x86::Source segment, [[maybe_unused]] uint16_t start, [[maybe_unused]] uint32_t length) {}
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void preauthorise_read([[maybe_unused]] uint32_t start, [[maybe_unused]] uint32_t length) {}
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//
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// Access call-ins.
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//
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// Accesses an address based on segment:offset.
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template <typename IntT, AccessType type>
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typename InstructionSet::x86::Accessor<IntT, type>::type access(InstructionSet::x86::Source segment, uint16_t offset) {
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const uint32_t physical_address = address(segment, offset);
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if constexpr (std::is_same_v<IntT, uint16_t>) {
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// If this is a 16-bit access that runs past the end of the segment, it'll wrap back
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// to the start. So the 16-bit value will need to be a local cache.
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if(offset == 0xffff) {
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return split_word<type>(physical_address, address(segment, 0));
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}
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}
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return access<IntT, type>(physical_address);
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}
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// Accesses an address based on physical location.
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template <typename IntT, AccessType type>
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typename InstructionSet::x86::Accessor<IntT, type>::type access(uint32_t address) {
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// Dispense with the single-byte case trivially.
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if constexpr (std::is_same_v<IntT, uint8_t>) {
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return memory[address];
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} else if(address != 0xf'ffff) {
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return *reinterpret_cast<IntT *>(&memory[address]);
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} else {
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return split_word<type>(address, 0);
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}
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}
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template <typename IntT>
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void write_back() {
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if constexpr (std::is_same_v<IntT, uint16_t>) {
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if(write_back_address_[0] != NoWriteBack) {
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memory[write_back_address_[0]] = write_back_value_ & 0xff;
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memory[write_back_address_[1]] = write_back_value_ >> 8;
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write_back_address_[0] = 0;
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}
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}
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}
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//
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// Direct write.
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//
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template <typename IntT>
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void preauthorised_write(InstructionSet::x86::Source segment, uint16_t offset, IntT value) {
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// Bytes can be written without further ado.
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if constexpr (std::is_same_v<IntT, uint8_t>) {
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memory[address(segment, offset) & 0xf'ffff] = value;
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return;
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}
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// Words that straddle the segment end must be split in two.
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if(offset == 0xffff) {
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memory[address(segment, offset) & 0xf'ffff] = value & 0xff;
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memory[address(segment, 0x0000) & 0xf'ffff] = value >> 8;
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return;
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}
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const uint32_t target = address(segment, offset) & 0xf'ffff;
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// Words that straddle the end of physical RAM must also be split in two.
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if(target == 0xf'ffff) {
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memory[0xf'ffff] = value & 0xff;
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memory[0x0'0000] = value >> 8;
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return;
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}
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// It's safe just to write then.
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*reinterpret_cast<uint16_t *>(&memory[target]) = value;
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}
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//
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// Helper for instruction fetch.
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//
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std::pair<const uint8_t *, size_t> next_code() {
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const uint32_t start = segments_.cs_base_ + registers_.ip();
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return std::make_pair(&memory[start], 0x10'000 - start);
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}
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std::pair<const uint8_t *, size_t> all() {
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return std::make_pair(memory.data(), 0x10'000);
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}
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private:
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std::vector<uint8_t> memory;
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Registers ®isters_;
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const Segments &segments_;
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uint32_t segment_base(InstructionSet::x86::Source segment) {
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using Source = InstructionSet::x86::Source;
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switch(segment) {
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default: return segments_.ds_base_;
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case Source::ES: return segments_.es_base_;
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case Source::CS: return segments_.cs_base_;
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case Source::SS: return segments_.ss_base_;
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}
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}
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uint32_t address(InstructionSet::x86::Source segment, uint16_t offset) {
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return (segment_base(segment) + offset) & 0xf'ffff;
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}
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template <AccessType type>
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typename InstructionSet::x86::Accessor<uint16_t, type>::type
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split_word(uint32_t low_address, uint32_t high_address) {
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if constexpr (is_writeable(type)) {
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write_back_address_[0] = low_address;
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write_back_address_[1] = high_address;
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// Prepopulate only if this is a modify.
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if constexpr (type == AccessType::ReadModifyWrite) {
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write_back_value_ = uint16_t(memory[write_back_address_[0]] | (memory[write_back_address_[1]] << 8));
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}
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return write_back_value_;
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} else {
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return memory[low_address] | (memory[high_address] << 8);
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}
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}
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static constexpr uint32_t NoWriteBack = 0; // A low byte address of 0 can't require write-back.
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uint32_t write_back_address_[2] = {NoWriteBack, NoWriteBack};
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uint16_t write_back_value_;
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};
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struct IO {
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template <typename IntT> void out([[maybe_unused]] uint16_t port, [[maybe_unused]] IntT value) {}
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template <typename IntT> IntT in([[maybe_unused]] uint16_t port) { return IntT(~0); }
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};
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class FlowController {
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public:
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FlowController(Registers ®isters, Segments &segments) :
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registers_(registers), segments_(segments) {}
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// Requirements for perform.
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void jump(uint16_t address) {
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registers_.ip() = address;
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}
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void jump(uint16_t segment, uint16_t address) {
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registers_.cs() = segment;
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segments_.did_update(Segments::Source::CS);
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registers_.ip() = address;
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}
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void halt() {}
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void wait() {}
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void repeat_last() {
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should_repeat_ = true;
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}
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// Other actions.
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void begin_instruction() {
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should_repeat_ = false;
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}
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bool should_repeat() const {
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return should_repeat_;
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}
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private:
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Registers ®isters_;
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Segments &segments_;
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bool should_repeat_ = false;
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};
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class ConcreteMachine:
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public Machine,
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public MachineTypes::TimedMachine,
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public MachineTypes::ScanProducer
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{
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public:
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ConcreteMachine(
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[[maybe_unused]] const Analyser::Static::Target &target,
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[[maybe_unused]] const ROMMachine::ROMFetcher &rom_fetcher
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) {
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// This is actually a MIPS count; try 3 million.
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set_clock_rate(3'000'000);
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// Fetch the BIOS. [8088 only, for now]
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ROM::Request request = ROM::Request(ROM::Name::PCCompatibleGLaBIOS);
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auto roms = rom_fetcher(request);
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if(!request.validate(roms)) {
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throw ROMMachine::Error::MissingROMs;
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}
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}
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// MARK: - TimedMachine.
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void run_for([[maybe_unused]] const Cycles cycles) override {
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auto instructions = cycles.as_integral();
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while(instructions--) {
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// Get the next thing to execute into decoded.
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if(!context.flow_controller.should_repeat()) {
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// Decode from the current IP.
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const auto remainder = context.memory.next_code();
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decoded = decoder.decode(remainder.first, remainder.second);
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// If that didn't yield a whole instruction then the end of memory must have been hit;
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// continue from the beginning.
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if(decoded.first <= 0) {
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const auto all = context.memory.all();
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decoded = decoder.decode(all.first, all.second);
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}
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} else {
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context.flow_controller.begin_instruction();
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}
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// Execute it.
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InstructionSet::x86::perform(
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decoded.second,
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context
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);
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}
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}
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// MARK: - ScanProducer.
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void set_scan_target([[maybe_unused]] Outputs::Display::ScanTarget *scan_target) override {}
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Outputs::Display::ScanStatus get_scaled_scan_status() const override {
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return Outputs::Display::ScanStatus();
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}
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private:
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struct Context {
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Context() :
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segments(registers),
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memory(registers, segments),
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flow_controller(registers, segments)
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{
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reset();
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}
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void reset() {
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registers.reset();
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segments.reset();
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}
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InstructionSet::x86::Flags flags;
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Registers registers;
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Segments segments;
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Memory memory;
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FlowController flow_controller;
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IO io;
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static constexpr auto model = InstructionSet::x86::Model::i8086;
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} context;
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InstructionSet::x86::Decoder<Context::model> decoder;
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std::pair<int, InstructionSet::x86::Instruction<false>> decoded;
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};
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}
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using namespace PCCompatible;
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// See header; constructs and returns an instance of the Amstrad CPC.
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Machine *Machine::PCCompatible(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
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return new PCCompatible::ConcreteMachine(*target, rom_fetcher);
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}
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Machine::~Machine() {}
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