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92 lines
3.1 KiB
C++
92 lines
3.1 KiB
C++
//
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// 6502Esque.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 28/09/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#ifndef m6502Esque_h
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#define m6502Esque_h
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/*
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This file defines how the CPU-controlled part of a bus looks for the 6502 and
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for other processors with a sufficiently-similar bus.
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I'm not yet a big fan of the name I've used here, and I'm still on the fence
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about what to do when eventually I get around to the 6800 and/or 6809, which have
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very similar bus characteristics.
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So: this is _very_ provisional stuff.
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*/
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namespace CPU {
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namespace MOS6502Esque {
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/*
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The list of registers that can be accessed via @c set_value_of_register and @c set_value_of_register.
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*/
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enum Register {
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LastOperationAddress,
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ProgramCounter,
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StackPointer,
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Flags,
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A,
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X,
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Y
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};
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/*!
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Bus handlers will be given the task of performing bus operations, allowing them to provide whatever interface they like
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between a 6502 and the rest of the system. @c BusOperation lists the types of bus operation that may be requested.
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@c None is reserved for internal use. It will never be requested from a subclass. It is safe always to use the
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isReadOperation macro to make a binary choice between reading and writing.
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*/
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enum BusOperation {
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Read, ReadOpcode, Write, Ready, None
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};
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/*!
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Evaluates to `true` if the operation is a read; `false` if it is a write.
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*/
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#define isReadOperation(v) (v == CPU::MOS6502Esque::BusOperation::Read || v == CPU::MOS6502Esque::BusOperation::ReadOpcode)
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/*!
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A class providing empty implementations of the methods a 6502 uses to access the bus. To wire the 6502 to a bus,
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machines should subclass BusHandler and then declare a realisation of the 6502 template, suplying their bus
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handler.
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*/
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template <typename AddressType> class BusHandler {
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public:
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/*!
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Announces that the 6502 has performed the cycle defined by operation, address and value. On the 6502,
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all bus cycles take one clock cycle so the amoutn of time advanced is implicit.
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@param operation The type of bus cycle: read, read opcode (i.e. read, with sync active),
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write or ready.
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@param address The value of the address bus during this bus cycle.
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@param value If this is a cycle that puts a value onto the data bus, *value is that value. If this is
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a cycle that reads the bus, the bus handler should write a value to *value. Writing to *value during
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a read cycle will produce undefined behaviour.
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@returns The number of cycles that passed in objective time while this 6502 bus cycle was ongoing.
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On an archetypal machine this will be Cycles(1) but some architectures may choose not to clock the 6502
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during some periods; one way to simulate that is to have the bus handler return a number other than
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Cycles(1) to describe lengthened bus cycles.
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*/
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Cycles perform_bus_operation([[maybe_unused]] BusOperation operation, [[maybe_unused]] AddressType address, [[maybe_unused]] uint8_t *value) {
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return Cycles(1);
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}
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/*!
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Announces completion of all the cycles supplied to a .run_for request on the 6502. Intended to allow
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bus handlers to perform any deferred output work.
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*/
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void flush() {}
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};
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}
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}
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#endif /* m6502Esque_h */
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