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390 lines
11 KiB
C++
390 lines
11 KiB
C++
//
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// Amiga.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/07/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "Amiga.hpp"
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#include "../MachineTypes.hpp"
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#include "../../Processors/68000/68000.hpp"
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#include "../../Components/6526/6526.hpp"
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#include "../../Analyser/Static/Amiga/Target.hpp"
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#include "../Utility/MemoryPacker.hpp"
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#include "../Utility/MemoryFuzzer.hpp"
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#define LOG_PREFIX "[Amiga] "
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#include "../../Outputs/Log.hpp"
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namespace Amiga {
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class ConcreteMachine:
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public CPU::MC68000::BusHandler,
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public MachineTypes::ScanProducer,
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public MachineTypes::TimedMachine,
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public Machine {
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public:
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ConcreteMachine(const Analyser::Static::Amiga::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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mc68000_(*this),
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cia_a_handler_(memory_),
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cia_a_(cia_a_handler_),
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cia_b_(cia_b_handler_)
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{
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(void)target;
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// Temporary: use a hard-coded Kickstart selection.
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constexpr ROM::Name rom_name = ROM::Name::AmigaA500Kickstart13;
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ROM::Request request(rom_name);
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auto roms = rom_fetcher(request);
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if(!request.validate(roms)) {
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throw ROMMachine::Error::MissingROMs;
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}
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Memory::PackBigEndian16(roms.find(rom_name)->second, memory_.kickstart_.data());
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// NTSC clock rate: 2*3.579545 = 7.15909Mhz.
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// PAL clock rate: 7.09379Mhz.
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set_clock_rate(7'093'790.0);
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}
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// MARK: - MC68000::BusHandler.
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using Microcycle = CPU::MC68000::Microcycle;
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HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
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// Intended 1-2 step here is:
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//
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// (1) determine when this CPU access will be scheduled;
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// (2) do all the other actions prior to this CPU access being scheduled.
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//
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// (or at least enqueue them, JIT-wise).
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// Advance time.
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// TODO: I think there's a divide-by-ten here. Probably these are driven off the 68000 E clock?
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cia_a_.run_for(cycle.length);
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cia_b_.run_for(cycle.length);
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// Do nothing if no address is exposed.
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
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// TODO: interrupt acknowledgement.
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// Grab the target address to pick a memory source.
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const uint32_t address = cycle.host_endian_byte_address();
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// if(cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord)) {
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// printf("%06x\n", *cycle.address);
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// }
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if(!memory_.regions_[address >> 18].read_write_mask) {
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if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) {
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// Check for various potential chip accesses.
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// Per the manual:
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//
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// CIA A is: 101x xxxx xx01 rrrr xxxx xxx0 (i.e. loaded into high byte)
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// CIA B is: 101x xxxx xx10 rrrr xxxx xxx1 (i.e. loaded into low byte)
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//
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// but in order to map 0xbfexxx to CIA A and 0xbfdxxx to CIA B, I think
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// these might be listed the wrong way around.
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//
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// Additional assumption: the relevant CIA select lines are connected
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// directly to the chip enables.
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if((address & 0xe0'0000) == 0xa0'0000) {
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const int reg = address >> 8;
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if(cycle.operation & Microcycle::Read) {
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uint16_t result = 0xffff;
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if(!(address & 0x1000)) result &= 0x00ff | (cia_a_.read(reg) << 8);
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if(!(address & 0x2000)) result &= 0xff00 | (cia_b_.read(reg) << 0);
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cycle.set_value16(result);
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} else {
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if(!(address & 0x1000)) cia_a_.write(reg, cycle.value8_high());
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if(!(address & 0x2000)) cia_b_.write(reg, cycle.value8_low());
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}
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} else if(address >= 0xdf'f000 && address <= 0xdf'f1be) {
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#define RW(address) (address & 0xffe) | ((cycle.operation & Microcycle::Read) << 7)
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#define Read(address) address | 0x1000
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#define Write(address) address
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#define ApplySetClear(target) { \
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const uint16_t value = cycle.value16(); \
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if(value & 0x8000) { \
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target |= (value & 0x7fff); \
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} else { \
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target &= ~(value & 0x7fff); \
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} \
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}
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switch(RW(address)) {
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default:
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printf("Unimplemented chipset access %06x\n", *cycle.address);
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assert(false);
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break;
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// Disk DMA.
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case Write(0x020): case Write(0x022): case Write(0x024):
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case Write(0x026):
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LOG("TODO: disk DMA; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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// Refresh.
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case Write(0x028):
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LOG("TODO (maybe): refresh; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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// Serial port.
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case Write(0x030):
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case Write(0x032):
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LOG("TODO: serial; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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// DMA management.
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case Write(0x096):
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ApplySetClear(dma_control_);
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LOG("DMA control is now " << std::bitset<16>{interrupt_enable_});
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break;
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// Interrupts.
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case Write(0x09a):
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ApplySetClear(interrupt_enable_);
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update_interrupts();
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LOG("Interrupt enable mask is now " << std::bitset<16>{interrupt_enable_});
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break;
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case Write(0x09c):
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ApplySetClear(interrupt_requests_);
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update_interrupts();
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LOG("Interrupt requests are now " << std::bitset<16>{interrupt_enable_});
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break;
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// Bitplanes.
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case Write(0x100):
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case Write(0x102):
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case Write(0x104):
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case Write(0x106):
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LOG("TODO: Bitplane control; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Write(0x108):
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case Write(0x10a):
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LOG("TODO: Bitplane modulo; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Write(0x110):
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case Write(0x112):
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case Write(0x114):
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case Write(0x116):
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case Write(0x118):
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case Write(0x11a):
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LOG("TODO: Bitplane data; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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// Colour palette.
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case Write(0x180): case Write(0x182): case Write(0x184): case Write(0x186):
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case Write(0x188): case Write(0x18a): case Write(0x18c): case Write(0x18e):
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case Write(0x190): case Write(0x192): case Write(0x194): case Write(0x196):
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case Write(0x198): case Write(0x19a): case Write(0x19c): case Write(0x19e):
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case Write(0x1a0): case Write(0x1a2): case Write(0x1a4): case Write(0x1a6):
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case Write(0x1a8): case Write(0x1aa): case Write(0x1ac): case Write(0x1ae):
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case Write(0x1b0): case Write(0x1b2): case Write(0x1b4): case Write(0x1b6):
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case Write(0x1b8): case Write(0x1ba): case Write(0x1bc): case Write(0x1be):
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LOG("TODO: colour palette; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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}
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#undef ApplySetClear
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#undef Write
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#undef Read
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#undef RW
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} else {
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// This'll do for open bus, for now.
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cycle.set_value16(0xffff);
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}
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}
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} else {
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// A regular memory access.
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cycle.apply(
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&memory_.regions_[address >> 18].contents[address],
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memory_.regions_[address >> 18].read_write_mask
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);
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}
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return HalfCycles(0);
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}
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private:
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CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
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// MARK: - Memory map.
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struct MemoryMap {
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public:
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std::array<uint8_t, 512*1024> ram_;
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std::array<uint8_t, 512*1024> kickstart_;
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struct MemoryRegion {
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uint8_t *contents = nullptr;
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unsigned int read_write_mask = 0;
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} regions_[64]; // i.e. top six bits are used as an index.
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MemoryMap() {
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// Address spaces that matter:
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//
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// 00'0000 – 08'0000: chip RAM. [or overlayed KickStart]
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// – 10'0000: extended chip ram for ECS.
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// – 20'0000: auto-config space (/fast RAM).
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// ...
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// bf'd000 – c0'0000: 8250s.
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// c0'0000 – d8'0000: pseudo-fast RAM.
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// ...
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// dc'0000 – dd'0000: optional real-time clock.
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// df'f000 - e0'0000: custom chip registers.
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// ...
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// f0'0000 — : 512kb Kickstart (or possibly just an extra 512kb reserved for hypothetical 1mb Kickstart?).
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// f8'0000 — : 256kb Kickstart if 2.04 or higher.
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// fc'0000 – : 256kb Kickstart otherwise.
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set_region(0xfc'0000, 0x1'00'0000, kickstart_.data(), CPU::MC68000::Microcycle::PermitRead);
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set_overlay(true);
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}
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void set_overlay(bool enabled) {
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if(overlay_ == enabled) {
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return;
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}
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overlay_ = enabled;
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if(enabled) {
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set_region(0x00'0000, 0x08'00000, kickstart_.data(), CPU::MC68000::Microcycle::PermitRead);
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} else {
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set_region(0x00'0000, 0x08'00000, ram_.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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}
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}
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private:
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bool overlay_ = false;
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void set_region(int start, int end, uint8_t *base, unsigned int read_write_mask) {
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assert(!(start & ~0xfc'0000));
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assert(!((end - (1 << 18)) & ~0xfc'0000));
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for(int c = start >> 18; c < end >> 18; c++) {
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regions_[c].contents = base - (c << 18);
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regions_[c].read_write_mask = read_write_mask;
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}
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}
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} memory_;
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// MARK: - Interrupts.
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uint16_t interrupt_enable_ = 0;
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uint16_t interrupt_requests_ = 0;
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void update_interrupts() {
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// TODO.
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}
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// MARK: - DMA control.
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uint16_t dma_control_ = 0;
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// MARK: - CIAs.
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class CIAAHandler: public MOS::MOS6526::PortHandler {
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public:
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CIAAHandler(MemoryMap &map) : map_(map) {}
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void set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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if(port) {
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// Parallel port output.
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LOG("TODO: parallel output " << PADHEX(2) << value);
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} else {
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// b7: /FIR1
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// b6: /FIR0
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// b5: /RDY
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// b4: /TRK0
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// b3: /WPRO
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// b2: /CHNG
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// b1: /LED [output]
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// b0: OVL [output]
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LOG("TODO: LED -> " << (value & 2));
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map_.set_overlay(value & 1);
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}
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}
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uint8_t get_port_input(MOS::MOS6526::Port port) {
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(void)port;
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return 0xff;
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}
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private:
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MemoryMap &map_;
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} cia_a_handler_;
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struct CIABHandler: public MOS::MOS6526::PortHandler {
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void set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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if(port) {
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// Serial port control.
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//
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// b7: /DTR
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// b6: /RTS
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// b5: /CD
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// b4: /CTS
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// b3: /DSR
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// b2: SEL
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// b1: POUT
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// b0: BUSY
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LOG("TODO: Serial control: " << PADHEX(2) << value);
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} else {
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// Disk motor control, drive and head selection,
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// and stepper control:
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//
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// b7: /MTR
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// b6: /SEL3
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// b5: /SEL2
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// b4: /SEL1
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// b3: /SEL0
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// b2: /SIDE
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// b1: DIR
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// b0: /STEP
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LOG("TODO: Stepping, etc; " << PADHEX(2) << value);
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}
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}
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} cia_b_handler_;
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MOS::MOS6526::MOS6526<CIAAHandler, MOS::MOS6526::Personality::P8250> cia_a_;
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MOS::MOS6526::MOS6526<CIABHandler, MOS::MOS6526::Personality::P8250> cia_b_;
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// MARK: - MachineTypes::ScanProducer.
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void set_scan_target(Outputs::Display::ScanTarget *scan_target) final {
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(void)scan_target;
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}
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Outputs::Display::ScanStatus get_scaled_scan_status() const {
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return Outputs::Display::ScanStatus();
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}
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// MARK: - MachineTypes::TimedMachine.
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void run_for(const Cycles cycles) {
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mc68000_.run_for(cycles);
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}
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};
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}
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using namespace Amiga;
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Machine *Machine::Amiga(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
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using Target = Analyser::Static::Amiga::Target;
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const Target *const amiga_target = dynamic_cast<const Target *>(target);
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return new Amiga::ConcreteMachine(*amiga_target, rom_fetcher);
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}
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Machine::~Machine() {}
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