Thomas Harte ee71be0e7e Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.		2017-08-21 21:56:42 -04:00
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C1540Bridge.h
C1540Bridge.mm	The 1540 is now a ClockReceiver.	2017-07-24 22:32:41 -04:00
Clock SignalTests-Bridging-Header.h
DigitalPhaseLockedLoopBridge.h	Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.	2017-07-16 20:55:57 -04:00
DigitalPhaseLockedLoopBridge.mm	Converted the DPLL and disk controller classes to be ClockReceivers.	2017-07-24 21:04:47 -04:00
MOS6522Bridge.h
MOS6522Bridge.mm	Corrected test.	2017-07-24 22:33:49 -04:00
MOS6532Bridge.h
MOS6532Bridge.mm	The 6532 is now a ClockReceiver.	2017-07-24 21:57:24 -04:00
TestMachine6502.h	Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.	2017-08-21 21:56:42 -04:00
TestMachine6502.mm	Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.	2017-08-21 21:56:42 -04:00
TestMachine.h
TestMachine.mm
TestMachine+ForSubclassEyesOnly.h
TestMachineZ80.h	Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.	2017-07-27 20:17:13 -04:00
TestMachineZ80.mm	Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.	2017-07-27 20:17:13 -04:00