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193 lines
7.7 KiB
C++
193 lines
7.7 KiB
C++
//
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// Instruction.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 1/15/21.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_PowerPC_Instruction_h
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#define InstructionSets_PowerPC_Instruction_h
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#include <cstdint>
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namespace CPU {
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namespace Decoder {
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namespace PowerPC {
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enum class Operation: uint8_t {
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Undefined,
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// These 601-exclusive instructions; a lot of them are carry-overs
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// from POWER.
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absx, clcs, divx, divsx, dozx, dozi, lscbxx, maskgx, maskirx, mulx,
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nabsx, rlmix, rribx, slex, sleqx, sliqx, slliqx, sllqx, slqx,
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sraiqx, sraqx, srex, sreax, sreqx, sriqx, srliqx, srlqx, srqx,
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// 32- and 64-bit PowerPC instructions.
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addx, addcx, addex, addi, addic, addic_, addis, addmex, addzex, andx,
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andcx, andi_, andis_, bx, bcx, bcctrx, bclrx, cmp, cmpi, cmpl, cmpli,
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cntlzwx, crand, crandc, creqv, crnand, crnor, cror, crorc, crxor, dcbf,
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dcbst, dcbt, dcbtst, dcbz, divwx, divwux, eciwx, ecowx, eieio, eqvx,
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extsbx, extshx, fabsx, faddx, faddsx, fcmpo, fcmpu, fctiwx, fctiwzx,
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fdivx, fdivsx, fmaddx, fmaddsx, fmrx, fmsubx, fmsubsx, fmulx, fmulsx,
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fnabsx, fnegx, fnmaddx, fnmaddsx, fnmsubx, fnmsubsx, frspx, fsubx, fsubsx,
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icbi, isync, lbz, lbzu, lbzux, lbzx, lfd, lfdu, lfdux, lfdx, lfs, lfsu,
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lfsux, lfsx, lha, lhau, lhaux, lhax, lhbrx, lhz, lhzu, lhzux, lhzx, lmw,
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lswi, lswx, lwarx, lwbrx, lwz, lwzu, lwzux, lwzx, mcrf, mcrfs, mcrxr,
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mfcr, mffsx, mfmsr, mfspr, mfsr, mfsrin, mtcrf, mtfsb0x, mtfsb1x, mtfsfx,
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mtfsfix, mtmsr, mtspr, mtsr, mtsrin, mulhwx, mulhwux, mulli, mullwx,
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nandx, negx, norx, orx, orcx, ori, oris, rfi, rlwimix, rlwinmx, rlwnmx,
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sc, slwx, srawx, srawix, srwx, stb, stbu, stbux, stbx, stfd, stfdu,
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stfdux, stfdx, stfs, stfsu, stfsux, stfsx, sth, sthbrx, sthu, sthux, sthx,
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stmw, stswi, stswx, stw, stwbrx, stwcx_, stwu, stwux, stwx, subfx, subfcx,
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subfex, subfic, subfmex, subfzex, sync, tw, twi, xorx, xori, xoris, mftb,
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// 32-bit, supervisor level.
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dcbi,
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// Supervisor, optional.
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tlbia, tlbie, tlbsync,
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// Optional.
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fresx, frsqrtex, fselx, fsqrtx, slbia, slbie, stfiwx,
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// 64-bit only PowerPC instructions.
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cntlzdx, divdx, divdux, extswx, fcfidx, fctidx, fctidzx, tdi, mulhdux,
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ldx, sldx, ldux, td, mulhdx, ldarx, stdx, stdux, mulld, lwax, lwaux,
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sradix, srdx, sradx, extsw, fsqrtsx, std, stdu, stdcx_,
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};
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/*!
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Holds a decoded PowerPC instruction.
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Implementation note: because the PowerPC encoding is particularly straightforward,
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only the operation has been decoded ahead of time; all other fields are decoded on-demand.
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It would be possible to partition the ordering of Operations into user followed by supervisor,
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eliminating the storage necessary for a flag, but it wouldn't save anything due to alignment.
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*/
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struct Instruction {
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Operation operation = Operation::Undefined;
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bool is_supervisor = false;
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uint32_t opcode = 0;
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Instruction() noexcept {}
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Instruction(uint32_t opcode) noexcept : opcode(opcode) {}
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Instruction(Operation operation, uint32_t opcode, bool is_supervisor = false) noexcept : operation(operation), is_supervisor(is_supervisor), opcode(opcode) {}
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// Instruction fields are decoded below; naming is a compromise between
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// Motorola's documentation and IBM's.
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//
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// I've dutifully implemented various synonyms with unique entry points,
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// in order to capture that information here rather than thrusting it upon
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// the reader of whatever implementation may follow.
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// Currently omitted: OPCD and XO, which I think are unnecessary given that
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// full decoding has already occurred.
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/// Immediate field used to specify an unsigned 16-bit integer.
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uint16_t uimm() const { return uint16_t(opcode & 0xffff); }
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/// Immediate field used to specify a signed 16-bit integer.
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int16_t simm() const { return int16_t(opcode & 0xffff); }
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/// Immediate field used to specify a signed 16-bit integer.
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int16_t d() const { return int16_t(opcode & 0xffff); }
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/// Immediate field used to specify a signed 14-bit integer [64-bit only].
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int16_t ds() const { return int16_t(opcode & 0xfffc); }
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/// Immediate field used as data to be placed into a field in the floating point status and condition register.
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int32_t imm() const { return (opcode >> 12) & 0xf; }
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/// Specifies the conditions on which to trap.
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int32_t to() const { return (opcode >> 21) & 0x1f; }
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/// Register source A or destination.
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uint32_t rA() const { return (opcode >> 16) & 0x1f; }
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/// Register source B.
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uint32_t rB() const { return (opcode >> 11) & 0x1f; }
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/// Register destination.
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uint32_t rD() const { return (opcode >> 21) & 0x1f; }
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/// Register source.
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uint32_t rS() const { return (opcode >> 21) & 0x1f; }
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/// Floating point register source A.
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uint32_t frA() const { return (opcode >> 16) & 0x1f; }
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/// Floating point register source B.
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uint32_t frB() const { return (opcode >> 11) & 0x1f; }
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/// Floating point register source C.
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uint32_t frC() const { return (opcode >> 6) & 0x1f; }
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/// Floating point register source.
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uint32_t frS() const { return (opcode >> 21) & 0x1f; }
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/// Floating point register destination.
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uint32_t frD() const { return (opcode >> 21) & 0x1f; }
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/// Branch conditional options.
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uint32_t bo() const { return (opcode >> 21) & 0x1f; }
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/// Source condition register bit for branch conditionals.
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uint32_t bi() const { return (opcode >> 16) & 0x1f; }
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/// Branch displacement; provided as already sign extended.
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int16_t bd() const { return int16_t(opcode & 0xfffc); }
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/// Specifies the first 1 bit of a 32/64-bit mask for rotate operations.
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uint32_t mb() const { return (opcode >> 6) & 0x1f; }
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/// Specifies the first 1 bit of a 32/64-bit mask for rotate operations.
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uint32_t me() const { return (opcode >> 1) & 0x1f; }
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/// Condition register source bit A.
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uint32_t crbA() const { return (opcode >> 16) & 0x1f; }
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/// Condition register source bit B.
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uint32_t crbB() const { return (opcode >> 11) & 0x1f; }
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/// Condition register (or floating point status & condition register) destination bit.
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uint32_t crbD() const { return (opcode >> 21) & 0x1f; }
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/// Condition register (or floating point status & condition register) destination field.
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uint32_t crfD() const { return (opcode >> 23) & 0x07; }
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/// Condition register (or floating point status & condition register) source field.
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uint32_t crfS() const { return (opcode >> 18) & 0x07; }
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/// Mask identifying fields to be updated by mtcrf.
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uint32_t crm() const { return (opcode >> 12) & 0xff; }
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/// Mask identifying fields to be updated by mtfsf.
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uint32_t fm() const { return (opcode >> 17) & 0xff; }
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/// Specifies the number of bytes to move in an immediate string load or store.
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uint32_t nb() const { return (opcode >> 11) & 0x1f; }
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/// Specifies a shift amount.
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/// TODO: possibly bit 30 is also used in 64-bit mode, find out.
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uint32_t sh() const { return (opcode >> 11) & 0x1f; }
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/// Specifies one of the 16 segment registers [32-bit only].
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uint32_t sr() const { return (opcode >> 16) & 0xf; }
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/// A 24-bit signed number; provided as already sign extended.
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int32_t li() const {
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constexpr uint32_t extensions[2] = {
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0x0000'0000,
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0xfc00'0000
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};
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const uint32_t value = (opcode & 0x03ff'fffc) | extensions[(opcode >> 25) & 1];
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return int32_t(value);
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}
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/// Absolute address bit; @c 0 or @c non-0.
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uint32_t aa() const { return opcode & 0x02; }
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/// Link bit; @c 0 or @c non-0.
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uint32_t lk() const { return opcode & 0x01; }
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/// Record bit; @c 0 or @c non-0.
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uint32_t rc() const { return opcode & 0x01; }
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/// Whether to compare 32-bit or 64-bit numbers [for 64-bit implementations only]; @c 0 or @c non-0.
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uint32_t l() const { return opcode & 0x200000; }
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/// Enables setting of OV and SO in the XER; @c 0 or @c non-0.
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uint32_t oe() const { return opcode & 0x800; }
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};
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// Sanity check on Instruction size.
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static_assert(sizeof(Instruction) <= 8);
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}
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}
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}
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#endif /* InstructionSets_PowerPC_Instruction_h */
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