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mirror of https://github.com/TomHarte/CLK.git synced 2024-12-23 20:29:42 +00:00
CLK/Components/AY38910
2017-08-07 19:51:36 -04:00
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AY38910.cpp Adjusted: invalid register selection simply deselects all registers. 2017-08-07 19:51:36 -04:00
AY38910.hpp The port input/output flags are now honoured; reading a port that is set as an output returns the current output value. 2017-08-07 19:01:18 -04:00