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347 lines
12 KiB
C++
347 lines
12 KiB
C++
//
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// AppleIIgs.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 20/10/2020.
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// Copyright 2020 Thomas Harte. All rights reserved.
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//
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#include "AppleIIgs.hpp"
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#include "../../MachineTypes.hpp"
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#include "../../../Processors/65816/65816.hpp"
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#include "../../../Analyser/Static/AppleIIgs/Target.hpp"
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#include "../AppleII/LanguageCardSwitches.hpp"
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#include "../AppleII/AuxiliaryMemorySwitches.hpp"
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#include <cassert>
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#include <array>
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namespace Apple {
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namespace IIgs {
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class ConcreteMachine:
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public Apple::IIgs::Machine,
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public MachineTypes::TimedMachine,
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public MachineTypes::ScanProducer,
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public CPU::MOS6502Esque::BusHandler<uint32_t> {
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public:
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ConcreteMachine(const Analyser::Static::AppleIIgs::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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m65816_(*this),
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auxiliary_switches_(*this),
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language_card_(*this) {
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set_clock_rate(14318180.0);
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using Target = Analyser::Static::AppleIIgs::Target;
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std::vector<ROMMachine::ROM> rom_descriptions;
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const std::string machine_name = "AppleIIgs";
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switch(target.model) {
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case Target::Model::ROM00:
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/* TODO */
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case Target::Model::ROM01:
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rom_descriptions.emplace_back(machine_name, "the Apple IIgs ROM01", "apple2gs.rom", 128*1024, 0x42f124b0);
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break;
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case Target::Model::ROM03:
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rom_descriptions.emplace_back(machine_name, "the Apple IIgs ROM03", "apple2gs.rom2", 256*1024, 0xde7ddf29);
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break;
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}
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const auto roms = rom_fetcher(rom_descriptions);
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if(!roms[0]) {
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throw ROMMachine::Error::MissingROMs;
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}
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rom_ = *roms[0];
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size_t ram_size = 0;
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switch(target.memory_model) {
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case Target::MemoryModel::TwoHundredAndFiftySixKB:
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ram_size = 256;
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break;
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case Target::MemoryModel::OneMB:
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ram_size = 128 + 1024;
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break;
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case Target::MemoryModel::EightMB:
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ram_size = 128 + 8 * 1024;
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break;
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}
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ram_.resize(ram_size * 1024);
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// Establish bank mapping.
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uint8_t next_region = 0;
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auto region = [&next_region, this]() -> uint8_t {
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assert(next_region != memory_regions_.size());
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return next_region++;
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};
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auto set_region = [this](uint8_t bank, uint16_t start, uint16_t end, uint8_t region) {
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assert((end == 0xffff) || !(end&0xff));
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assert(!(start&0xff));
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// Fill in memory map.
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size_t target = size_t((bank << 8) | (start >> 8));
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for(int c = start; c < end; c += 0x100) {
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memory_map_[target] = region;
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++target;
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}
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};
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// Current beliefs about the IIgs memory map:
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//
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// * language card banking applies to banks $00, $01, $e0 and $e1;
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// * auxiliary memory switches apply to banks $00 only;
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// * shadowing may be enabled only on banks $00 and $01, or on all RAM pages.
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//
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// So banks $00 and $01 need their own divided spaces at the shadowing resolution,
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// all the other fast RAM banks can share a set of divided spaces, $e0 and $e1 need
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// to be able to deal with language card-level division but no further, and the pure
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// ROM pages don't need to be subdivided at all.
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// Reserve region 0 as that for unmapped memory.
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region();
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// Bank $00: all locations potentially affected by the auxiliary switches or the
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// language switches. Which will naturally align with shadowable zones.
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set_region(0x00, 0x0000, 0x0200, region());
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set_region(0x00, 0x0200, 0x0400, region());
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set_region(0x00, 0x0400, 0x0800, region());
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set_region(0x00, 0x0800, 0x2000, region());
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set_region(0x00, 0x2000, 0x4000, region());
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set_region(0x00, 0x4000, 0xc000, region());
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set_region(0x00, 0xc000, 0xc100, region());
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set_region(0x00, 0xc100, 0xc300, region());
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set_region(0x00, 0xc300, 0xc400, region());
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set_region(0x00, 0xc400, 0xc800, region());
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set_region(0x00, 0xc800, 0xd000, region());
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set_region(0x00, 0xd000, 0xe000, region());
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set_region(0x00, 0xe000, 0xffff, region());
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// Bank $01: all locations potentially affected by the language switches, by shadowing,
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// or marked for IO.
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set_region(0x01, 0x0000, 0x0400, region());
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set_region(0x01, 0x0400, 0x0800, region());
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set_region(0x01, 0x0800, 0x0c00, region());
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set_region(0x01, 0x0c00, 0x2000, region());
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set_region(0x01, 0x2000, 0x4000, region());
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set_region(0x01, 0x4000, 0x6000, region());
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set_region(0x01, 0x6000, 0xa000, region());
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set_region(0x01, 0xa000, 0xc000, region());
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set_region(0x01, 0xc000, 0xd000, region());
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set_region(0x01, 0xd000, 0xe000, region());
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set_region(0x01, 0xe000, 0xffff, region());
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// Banks $02–[end of RAM]: all locations potentially affected by shadowing.
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const uint8_t fast_ram_bank_count = uint8_t((ram_size - 128)/64);
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if(fast_ram_bank_count > 2) {
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const uint8_t evens[] = {
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region(), // 0x0000 – 0x0400.
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region(), // 0x0400 – 0x0800.
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region(), // 0x0800 – 0x0c00.
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region(), // 0x0c00 – 0x2000.
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region(), // 0x2000 – 0x4000.
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region(), // 0x4000 – 0x6000.
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region(), // 0x6000 – [end].
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};
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const uint8_t odds[] = {
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region(), // 0x0000 – 0x0400.
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region(), // 0x0400 – 0x0800.
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region(), // 0x0800 – 0x0c00.
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region(), // 0x0c00 – 0x2000.
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region(), // 0x2000 – 0x4000.
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region(), // 0x4000 – 0x6000.
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region(), // 0x6000 – 0xa000.
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region(), // 0xa000 – [end].
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};
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for(uint8_t bank = 0x02; bank < fast_ram_bank_count; bank += 2) {
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set_region(bank, 0x0000, 0x0400, evens[0]);
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set_region(bank, 0x0400, 0x0800, evens[1]);
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set_region(bank, 0x0800, 0x0c00, evens[2]);
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set_region(bank, 0x0c00, 0x2000, evens[3]);
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set_region(bank, 0x2000, 0x4000, evens[4]);
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set_region(bank, 0x4000, 0x6000, evens[5]);
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set_region(bank, 0x6000, 0xffff, evens[6]);
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set_region(bank+1, 0x0000, 0x0400, odds[0]);
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set_region(bank+1, 0x0400, 0x0800, odds[1]);
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set_region(bank+1, 0x0800, 0x0c00, odds[2]);
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set_region(bank+1, 0x0c00, 0x2000, odds[3]);
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set_region(bank+1, 0x2000, 0x4000, odds[4]);
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set_region(bank+1, 0x4000, 0x6000, odds[5]);
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set_region(bank+1, 0x6000, 0xa000, odds[6]);
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set_region(bank+1, 0xa000, 0xffff, odds[7]);
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}
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}
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// [Banks $80–$e0: empty].
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// Banks $e0, $e1: all locations potentially affected by the language switches or marked for IO.
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for(uint8_t c = 0; c < 2; c++) {
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set_region(0xe0 + c, 0x0000, 0xc000, region());
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set_region(0xe0 + c, 0xc000, 0xd000, region());
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set_region(0xe0 + c, 0xd000, 0xffff, region());
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}
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// [Banks $e2–[ROM start]: empty].
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// ROM banks: directly mapped to ROM.
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const uint8_t rom_bank_count = uint8_t(rom_.size() >> 16);
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const uint8_t first_rom_bank = uint8_t(0x100 - rom_bank_count);
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const uint8_t rom_region = region();
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for(uint8_t c = 0; c < rom_bank_count; ++c) {
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set_region(first_rom_bank + c, 0x0000, 0xff00, rom_region);
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}
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// Apply proper storage to those banks.
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auto set_storage = [this](uint32_t address, const uint8_t *read, uint8_t *write) {
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// Don't allow the reserved null region to be modified.
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assert(memory_map_[address >> 8]);
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// Either set or apply a quick bit of testing as to the logic at play.
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auto ®ion = memory_regions_[memory_map_[address >> 8]];
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if(read) read -= address;
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if(write) write -= address;
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if(!region.read) {
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region.read = read;
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region.write = write;
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} else {
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assert(region.read == read);
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assert(region.write == write);
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}
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};
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// This is highly redundant, but decouples this step from the above.
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for(size_t c = 0; c < 0x800000; c += 0x100) {
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if(c < (ram_size - 128)*1024) {
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set_storage(uint32_t(c), &ram_[c], &ram_[c]);
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}
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}
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uint8_t *const slow_ram = &ram_[ram_.size() - 0x20000];
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for(size_t c = 0xe00000; c < 0xe20000; c += 0x100) {
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set_storage(uint32_t(c), &slow_ram[c - 0xe00000], &slow_ram[c - 0xe00000]);
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}
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for(uint32_t c = 0; c < uint32_t(rom_bank_count); ++c) {
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set_storage((first_rom_bank + c) << 16, &rom_[c << 16], &rom_[c << 16]);
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}
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// Apply initial language/auxiliary state. [TODO: including shadowing register].
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set_card_paging();
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set_zero_page_paging();
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set_main_paging();
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}
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void run_for(const Cycles cycles) override {
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m65816_.run_for(cycles);
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}
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void set_scan_target(Outputs::Display::ScanTarget *) override {
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}
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Outputs::Display::ScanStatus get_scaled_scan_status() const override {
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return Outputs::Display::ScanStatus();
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}
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forceinline Cycles perform_bus_operation(const CPU::WDC65816::BusOperation operation, const uint32_t address, uint8_t *const value) {
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const MemoryRegion ®ion = memory_regions_[memory_map_[address >> 8]];
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if(region.flags & MemoryRegion::IsIO) {
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// TODO: all IO accesses.
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} else {
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// TODO: branching below is predicated on the idea that an extra 64kb of scratch write area
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// and 64kb of 0xffs would be worse than branching due to the data set increase. Verify that?
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if(isReadOperation(operation)) {
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*value = region.read ? region.read[address] : 0xff;
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} else {
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if(region.write) {
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region.write[address] = *value;
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// Apply shadowing.
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if(region.flags & (MemoryRegion::IsShadowedE0|MemoryRegion::IsShadowedE1)) {
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const uint32_t shadowed_address = (address & 0xffff) + (uint32_t(0xe1 - (region.flags&MemoryRegion::IsShadowedE0)) << 16);
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memory_regions_[memory_map_[shadowed_address >> 8]].write[shadowed_address] = *value;
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}
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}
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}
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}
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Cycles duration = Cycles(5);
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// TODO: determine the cost of this access.
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// if((mapping.flags & BankMapping::Is1Mhz) || ((mapping.flags & BankMapping::IsShadowed) && !isReadOperation(operation))) {
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// // TODO: (i) get into phase; (ii) allow for the 1Mhz bus length being sporadically 16 rather than 14.
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// duration = Cycles(14);
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// } else {
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// // TODO: (i) get into phase; (ii) allow for collisions with the refresh cycle.
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// duration = Cycles(5);
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// }
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fast_access_phase_ = (fast_access_phase_ + duration.as<int>()) % 5; // TODO: modulo something else, to allow for refresh.
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slow_access_phase_ = (slow_access_phase_ + duration.as<int>()) % 14; // TODO: modulo something else, to allow for stretched cycles.
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return duration;
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}
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// MARK: - Memory banking.
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void set_language_card_paging() {
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}
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void set_card_paging() {
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}
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void set_zero_page_paging() {
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set_language_card_paging();
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}
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void set_main_paging() {
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}
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private:
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CPU::WDC65816::Processor<ConcreteMachine, false> m65816_;
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Apple::II::AuxiliaryMemorySwitches<ConcreteMachine> auxiliary_switches_;
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Apple::II::LanguageCardSwitches<ConcreteMachine> language_card_;
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int fast_access_phase_ = 0;
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int slow_access_phase_ = 0;
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// MARK: - Memory layout and storage.
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// Memory layout here is done via double indirection; the main loop should:
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// (i) use the top two bytes of the address to get an index from memory_map_; and
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// (ii) use that to index the memory_regions_ table.
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//
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// Pointers are eight bytes at the time of writing, so the extra level of indirection
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// reduces what would otherwise be a 1.25mb table down to not a great deal more than 64kb.
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std::array<uint8_t, 65536> memory_map_;
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struct MemoryRegion {
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uint8_t *write = nullptr;
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const uint8_t *read = nullptr;
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uint8_t flags = 0;
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enum Flag: uint8_t {
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IsShadowedE0 = 1 << 0, // i.e. writes should also be written to bank $e0, and costed appropriately.
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IsShadowedE1 = 1 << 1, // i.e. writes should also be written to bank $e1, and costed appropriately.
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Is1Mhz = 1 << 2, // Both reads and writes should be synchronised with the 1Mhz clock.
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IsIO = 1 << 3, // Indicates that this region should be checked for soft switches, registers, etc.
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};
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};
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std::array<MemoryRegion, 47> memory_regions_; // The assert above ensures that this is large enough; there's no
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// doctrinal reason for it to be whatever size it is now, just
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// adjust as required.
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// MARK: - Memory storage.
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// Actual memory storage.
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std::vector<uint8_t> ram_;
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std::vector<uint8_t> rom_;
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};
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}
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}
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using namespace Apple::IIgs;
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Machine *Machine::AppleIIgs(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
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return new ConcreteMachine(*dynamic_cast<const Analyser::Static::AppleIIgs::Target *>(target), rom_fetcher);
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}
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Machine::~Machine() {}
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