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338 lines
11 KiB
Plaintext
338 lines
11 KiB
Plaintext
//
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// ARMDecoderTests.m
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// Clock Signal
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//
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// Created by Thomas Harte on 16/02/2024.
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// Copyright 2024 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include "../../../InstructionSets/ARM/OperationMapper.hpp"
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#include "../../../InstructionSets/ARM/Registers.hpp"
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#include "../../../Numeric/Carry.hpp"
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using namespace InstructionSet::ARM;
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namespace {
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template <ShiftType type, bool set_carry>
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void shift(uint32_t &source, uint32_t amount, uint32_t *carry = nullptr) {
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switch(type) {
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case ShiftType::LogicalLeft:
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if(amount > 32) {
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if constexpr (set_carry) *carry = 0;
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source = 0;
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} else if(amount == 32) {
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if constexpr (set_carry) *carry = source & 1;
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source = 0;
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} else if(amount > 0) {
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if constexpr (set_carry) *carry = source & (0x8000'0000 >> (amount - 1));
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source <<= amount;
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}
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break;
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case ShiftType::LogicalRight:
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if(amount > 32) {
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if constexpr (set_carry) *carry = 0;
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source = 0;
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} else if(amount == 32) {
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if constexpr (set_carry) *carry = source & 0x8000'0000;
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source = 0;
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} else if(amount > 0) {
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if constexpr (set_carry) *carry = source & (1 << (amount - 1));
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source >>= amount;
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} else {
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// A logical shift right by '0' is treated as a shift by 32;
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// assemblers are supposed to map LSR #0 to LSL #0.
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if constexpr (set_carry) *carry = source & 0x8000'0000;
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source = 0;
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}
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break;
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case ShiftType::ArithmeticRight: {
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const uint32_t sign = (source & 0x8000'0000) ? 0xffff'ffff : 0x0000'0000;
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if(amount >= 32) {
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if constexpr (set_carry) *carry = sign;
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source = sign;
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} else if(amount > 0) {
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if constexpr (set_carry) *carry = source & (1 << (amount - 1));
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source = (source >> amount) | (sign << (32 - amount));
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} else {
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// As per logical right, an arithmetic shift of '0' is
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// treated as a shift by 32.
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if constexpr (set_carry) *carry = source & 0x8000'0000;
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source = sign;
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}
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} break;
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case ShiftType::RotateRight: {
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if(amount == 32) {
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if constexpr (set_carry) *carry = source & 0x8000'0000;
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} else if(amount == 0) {
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// Rotate right by 0 is treated as a rotate right by 1 through carry.
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const uint32_t high = *carry << 31;
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if constexpr (set_carry) *carry = source & 1;
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source = (source >> 1) | high;
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} else {
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amount &= 31;
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if constexpr (set_carry) *carry = source & (1 << (amount - 1));
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source = (source >> amount) | (source << (32 - amount));
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}
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} break;
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default: break;
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}
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}
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template <bool set_carry>
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void shift(ShiftType type, uint32_t &source, uint32_t amount, uint32_t *carry) {
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switch(type) {
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case ShiftType::LogicalLeft:
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shift<ShiftType::LogicalLeft, set_carry>(source, amount, carry);
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break;
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case ShiftType::LogicalRight:
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shift<ShiftType::LogicalRight, set_carry>(source, amount, carry);
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break;
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case ShiftType::ArithmeticRight:
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shift<ShiftType::ArithmeticRight, set_carry>(source, amount, carry);
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break;
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case ShiftType::RotateRight:
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shift<ShiftType::RotateRight, set_carry>(source, amount, carry);
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break;
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}
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}
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struct Scheduler {
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bool should_schedule(Condition condition) {
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return registers_.test(condition);
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}
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template <Flags f> void perform(DataProcessing fields) {
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constexpr DataProcessingFlags flags(f);
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const bool shift_by_register = !flags.operand2_is_immediate() && fields.shift_count_is_register();
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// Write a raw result into the PC proxy if the target is R15; it'll be stored properly later.
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uint32_t pc_proxy;
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auto &destination = fields.destination() == 15 ? pc_proxy : registers_.active[fields.destination()];
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// "When R15 appears in either of the Rn or Rs positions it will give the value
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// of the PC alone, with the PSR bits replaced by zeroes. ...
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//
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// If the shift amount is specified in the instruction, the PC will be 8 bytes ahead.
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// If a register is used to specify the shift amount, the PC will be ... 12 bytes ahead
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// when used as Rn or Rm."
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const uint32_t operand1 =
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(fields.operand1() == 15) ?
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registers_.pc(shift_by_register ? 12 : 8) :
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registers_.active[fields.operand1()];
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uint32_t operand2;
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uint32_t rotate_carry = registers_.c();
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// Populate carry from the shift only if it'll be used.
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constexpr bool shift_sets_carry = is_logical(flags.operation()) && flags.set_condition_codes();
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// Get operand 2.
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if constexpr (flags.operand2_is_immediate()) {
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operand2 = fields.immediate();
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if(fields.rotate()) {
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shift<ShiftType::RotateRight, shift_sets_carry>(operand2, fields.rotate(), &rotate_carry);
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}
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} else {
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uint32_t shift_amount;
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if(fields.shift_count_is_register()) {
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// "When R15 appears in either of the Rn or Rs positions it will give the value
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// of the PC alone, with the PSR bits replaced by zeroes. ...
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//
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// If a register is used to specify the shift amount, the
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// PC will be 8 bytes ahead when used as Rs."
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shift_amount =
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fields.shift_register() == 15 ?
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registers_.pc(8) :
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registers_.active[fields.shift_register()];
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} else {
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shift_amount = fields.shift_amount();
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}
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// "When R15 appears in the Rm position it will give the value of the PC together
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// with the PSR flags to the barrel shifter. ...
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//
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// If the shift amount is specified in the instruction, the PC will be 8 bytes ahead.
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// If a register is used to specify the shift amount, the PC will be ... 12 bytes ahead
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// when used as Rn or Rm."
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if(fields.operand2() == 15) {
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operand2 = registers_.pc_status(shift_by_register ? 12 : 8);
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} else {
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operand2 = registers_.active[fields.operand2()];
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}
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shift<shift_sets_carry>(fields.shift_type(), operand2, shift_amount, &rotate_carry);
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}
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// Perform the data processing operation.
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uint32_t conditions = 0;
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switch(flags.operation()) {
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// Logical operations.
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case DataProcessingOperation::AND: conditions = destination = operand1 & operand2; break;
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case DataProcessingOperation::EOR: conditions = destination = operand1 ^ operand2; break;
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case DataProcessingOperation::ORR: conditions = destination = operand1 | operand2; break;
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case DataProcessingOperation::BIC: conditions = destination = operand1 & ~operand2; break;
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case DataProcessingOperation::MOV: conditions = destination = operand2; break;
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case DataProcessingOperation::MVN: conditions = destination = ~operand2; break;
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case DataProcessingOperation::TST: conditions = operand1 & operand2; break;
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case DataProcessingOperation::TEQ: conditions = operand1 ^ operand2; break;
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case DataProcessingOperation::ADD:
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case DataProcessingOperation::ADC:
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case DataProcessingOperation::CMN:
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conditions = operand1 + operand2;
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if constexpr (flags.operation() == DataProcessingOperation::ADC) {
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conditions += registers_.c();
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}
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if constexpr (flags.set_condition_codes()) {
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registers_.set_c(Numeric::carried_out<true, 31>(operand1, operand2, conditions));
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registers_.set_v(Numeric::overflow<true>(operand1, operand2, conditions));
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}
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if constexpr (!is_comparison(flags.operation())) {
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destination = conditions;
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}
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break;
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case DataProcessingOperation::SUB:
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case DataProcessingOperation::SBC:
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case DataProcessingOperation::CMP:
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conditions = operand1 - operand2;
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if constexpr (flags.operation() == DataProcessingOperation::SBC) {
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conditions -= registers_.c();
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}
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if constexpr (flags.set_condition_codes()) {
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registers_.set_c(Numeric::carried_out<false, 31>(operand1, operand2, conditions));
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registers_.set_v(Numeric::overflow<false>(operand1, operand2, conditions));
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}
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if constexpr (!is_comparison(flags.operation())) {
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destination = conditions;
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}
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break;
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case DataProcessingOperation::RSB:
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case DataProcessingOperation::RSC:
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conditions = operand2 - operand1;
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if constexpr (flags.operation() == DataProcessingOperation::RSC) {
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conditions -= registers_.c();
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}
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if constexpr (flags.set_condition_codes()) {
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registers_.set_c(Numeric::carried_out<false, 31>(operand2, operand1, conditions));
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registers_.set_v(Numeric::overflow<false>(operand2, operand1, conditions));
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}
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destination = conditions;
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break;
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}
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if constexpr (flags.set_condition_codes()) {
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// "When Rd is a register other than R15, the condition code flags in the PSR may be
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// updated from the ALU flags as described above. When Rd is R15 and the S flag in
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// the instruction is set, the PSR is overwritten by the corresponding ALU result.
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//
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// ... if the instruction is of a type which does not normally produce a result
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// (CMP, CMN, TST, TEQ) but Rd is R15 and the S bit is set, the result will be used in
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// this case to update those PSR flags which are not protected by virtue of the
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// processor mode."
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if(fields.destination() == 15) {
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if constexpr (is_comparison(flags.operation())) {
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registers_.set_status(pc_proxy);
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} else {
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registers_.set_status(pc_proxy);
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registers_.set_pc(pc_proxy);
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}
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} else {
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// Set N and Z in a unified way.
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registers_.set_nz(conditions);
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// Set C from the barrel shifter if applicable.
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if constexpr (shift_sets_carry) {
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registers_.set_c(rotate_carry);
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}
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}
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} else {
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// "If the S flag is clear when Rd is R15, only the 24 PC bits of R15 will be written."
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if(fields.destination() == 15) {
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registers_.set_pc(pc_proxy);
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}
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}
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}
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template <Flags f> void perform(Multiply fields) {
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constexpr MultiplyFlags flags(f);
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// R15 rules:
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//
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// * Rs: no PSR, 8 bytes ahead;
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// * Rn: with PSR, 8 bytes ahead;
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// * Rm: with PSR, 12 bytes ahead.
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const uint32_t multiplicand = fields.multiplicand() == 15 ? registers_.pc(8) : registers_.active[fields.multiplicand()];
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const uint32_t multiplier = fields.multiplier() == 15 ? registers_.pc_status(8) : registers_.active[fields.multiplier()];
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const uint32_t accumulator =
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flags.operation() == MultiplyOperation::MUL ? 0 :
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(fields.multiplicand() == 15 ? registers_.pc_status(12) : registers_.active[fields.accumulator()]);
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const uint32_t result = multiplicand * multiplier + accumulator;
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if constexpr (flags.set_condition_codes()) {
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registers_.set_nz(result);
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// V is unaffected; C is undefined.
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}
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if(fields.destination() != 15) {
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registers_.active[fields.destination()] = result;
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}
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}
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template <Operation, Flags> void perform(Condition, SingleDataTransfer) {}
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template <Operation, Flags> void perform(Condition, BlockDataTransfer) {}
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template <Operation op> void perform(Condition condition, Branch branch) {
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printf("Branch %sif %d; add %08x\n", op == Operation::BL ? "with link " : "", int(condition), branch.offset());
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}
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template <Operation, Flags> void perform(Condition, CoprocessorRegisterTransfer) {}
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template <Flags> void perform(Condition, CoprocessorDataOperation) {}
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template<Operation, Flags> void perform(Condition, CoprocessorDataTransfer) {}
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void software_interrupt(Condition) {}
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void unknown(uint32_t) {}
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private:
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Registers registers_;
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};
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}
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@interface ARMDecoderTests : XCTestCase
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@end
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@implementation ARMDecoderTests
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- (void)testXYX {
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Scheduler scheduler;
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for(int c = 0; c < 65536; c++) {
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InstructionSet::ARM::dispatch(c << 16, scheduler);
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}
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InstructionSet::ARM::dispatch(0xEAE06900, scheduler);
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}
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@end
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