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465 lines
14 KiB
C++
465 lines
14 KiB
C++
//
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// OperationMapper.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/02/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "../../Reflection/Dispatcher.hpp"
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namespace InstructionSet::ARM {
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enum class Model {
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ARM2,
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};
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enum class Operation {
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AND, /// Rd = Op1 AND Op2.
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EOR, /// Rd = Op1 EOR Op2.
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SUB, /// Rd = Op1 - Op2.
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RSB, /// Rd = Op2 - Op1.
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ADD, /// Rd = Op1 + Op2.
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ADC, /// Rd = Op1 + Ord2 + C.
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SBC, /// Rd = Op1 - Op2 + C.
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RSC, /// Rd = Op2 - Op1 + C.
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TST, /// Set condition codes on Op1 AND Op2.
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TEQ, /// Set condition codes on Op1 EOR Op2.
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CMP, /// Set condition codes on Op1 - Op2.
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CMN, /// Set condition codes on Op1 + Op2.
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ORR, /// Rd = Op1 OR Op2.
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MOV, /// Rd = Op2
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BIC, /// Rd = Op1 AND NOT Op2.
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MVN, /// Rd = NOT Op2.
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MUL, /// Rd = Rm * Rs
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MLA, /// Rd = Rm * Rs + Rn
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B, /// Add offset to PC; programmer allows for PC being two words ahead.
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BL, /// Copy PC and PSR to R14, then branch. Copied PC points to next instruction.
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LDR, /// Read single byte or word from [base + offset], possibly mutating the base.
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STR, /// Write a single byte or word to [base + offset], possibly mutating the base.
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LDM, /// Read 1–16 words from [base], possibly mutating it.
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STM, /// Write 1-16 words to [base], possibly mutating it.
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SWI, /// Perform a software interrupt.
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CDP, /// Coprocessor data operation.
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MRC, /// Move from coprocessor register to ARM register.
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MCR, /// Move from ARM register to coprocessor register.
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LDC, /// Coprocessor data transfer load.
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STC, /// Coprocessor data transfer store.
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Undefined,
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};
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enum class Condition {
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EQ, NE, CS, CC,
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MI, PL, VS, VC,
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HI, LS, GE, LT,
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GT, LE, AL, NV,
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};
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enum class ShiftType {
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LogicalLeft = 0b00,
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LogicalRight = 0b01,
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ArithmeticRight = 0b10,
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RotateRight = 0b11,
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};
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//
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// Implementation details.
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//
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static constexpr int FlagsStartBit = 20;
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using Flags = uint8_t;
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template <int position>
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constexpr bool flag_bit(uint8_t flags) {
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static_assert(position >= 20 && position < 28);
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return flags & (1 << (position - FlagsStartBit));
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}
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struct WithShiftControlBits {
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constexpr WithShiftControlBits(uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The operand 2 register index if @c operand2_is_immediate() is @c false; meaningless otherwise.
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int operand2() const { return opcode_ & 0xf; }
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/// The type of shift to apply to operand 2 if @c operand2_is_immediate() is @c false; meaningless otherwise.
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ShiftType shift_type() const { return ShiftType((opcode_ >> 5) & 3); }
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/// @returns @c true if the amount to shift by should be taken from a register; @c false if it is an immediate value.
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bool shift_count_is_register() const { return opcode_ & (1 << 4); }
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/// The shift amount register index if @c shift_count_is_register() is @c true; meaningless otherwise.
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int shift_register() const { return (opcode_ >> 8) & 0xf; }
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/// The amount to shift by if @c shift_count_is_register() is @c false; meaningless otherwise.
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int shift_amount() const { return (opcode_ >> 7) & 0x1f; }
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protected:
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uint32_t opcode_;
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};
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//
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// Branch (i.e. B and BL).
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//
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struct Branch {
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constexpr Branch(uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The 26-bit offset to add to the PC.
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int offset() const { return (opcode_ & 0xff'ffff) << 2; }
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private:
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uint32_t opcode_;
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};
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//
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// Data processing (i.e. AND to MVN).
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//
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struct DataProcessingFlags {
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constexpr DataProcessingFlags(uint8_t flags) noexcept : flags_(flags) {}
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/// @returns @c true if operand 2 is defined by the @c rotate() and @c immediate() fields;
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/// @c false if it is defined by the @c shift_*() and @c operand2() fields.
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constexpr bool operand2_is_immediate() { return flag_bit<25>(flags_); }
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constexpr bool set_condition_codes() { return flag_bit<20>(flags_); }
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private:
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uint8_t flags_;
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};
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struct DataProcessing: public WithShiftControlBits {
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using WithShiftControlBits::WithShiftControlBits;
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/// The destination register index. i.e. Rd.
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int destination() const { return (opcode_ >> 12) & 0xf; }
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/// The operand 1 register index. i.e. Rn.
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int operand1() const { return (opcode_ >> 16) & 0xf; }
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//
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// Immediate values for operand 2.
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//
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/// An 8-bit value to rotate right @c rotate() places if @c operand2_is_immediate() is @c true; meaningless otherwise.
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int immediate() const { return opcode_ & 0xff; }
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/// The number of bits to rotate @c immediate() by to the right if @c operand2_is_immediate() is @c true; meaningless otherwise.
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int rotate() const { return (opcode_ >> 7) & 0x1e; }
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};
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//
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// MUL and MLA.
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//
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struct MultiplyFlags {
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constexpr MultiplyFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr bool set_condition_codes() { return flag_bit<20>(flags_); }
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private:
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uint8_t flags_;
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};
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struct Multiply {
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constexpr Multiply(uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The destination register index. i.e. 'Rd'.
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int destination() const { return (opcode_ >> 16) & 0xf; }
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/// The accumulator register index for multiply-add. i.e. 'Rn'.
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int accumulator() const { return (opcode_ >> 12) & 0xf; }
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/// The multiplicand register index. i.e. 'Rs'.
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int multiplicand() const { return (opcode_ >> 8) & 0xf; }
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/// The multiplier register index. i.e. 'Rm'.
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int multiplier() const { return opcode_ & 0xf; }
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private:
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uint32_t opcode_;
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};
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//
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// Single data transfer (LDR, STR).
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//
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struct SingleDataTransferFlags {
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constexpr SingleDataTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr bool offset_is_immediate() { return flag_bit<25>(flags_); }
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constexpr bool pre_index() { return flag_bit<24>(flags_); }
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constexpr bool add_offset() { return flag_bit<23>(flags_); }
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constexpr bool transfer_byte() { return flag_bit<22>(flags_); }
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constexpr bool write_back_address() { return flag_bit<21>(flags_); }
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private:
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uint8_t flags_;
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};
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struct SingleDataTransfer: public WithShiftControlBits {
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using WithShiftControlBits::WithShiftControlBits;
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/// The destination register index. i.e. 'Rd' for LDR.
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int destination() const { return (opcode_ >> 12) & 0xf; }
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/// The destination register index. i.e. 'Rd' for STR.
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int source() const { return (opcode_ >> 12) & 0xf; }
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/// The base register index. i.e. 'Rn'.
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int base() const { return (opcode_ >> 16) & 0xf; }
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/// The immediate offset, if @c offset_is_immediate() was @c true; meaningless otherwise.
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int immediate() const { return opcode_ & 0xfff; }
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};
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//
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// Block data transfer (LDR, STR).
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//
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struct BlockDataTransferFlags {
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constexpr BlockDataTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr bool pre_index() { return flag_bit<24>(flags_); }
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constexpr bool add_offset() { return flag_bit<23>(flags_); }
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constexpr bool load_psr() { return flag_bit<22>(flags_); }
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constexpr bool write_back_address() { return flag_bit<21>(flags_); }
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private:
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uint8_t flags_;
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};
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struct BlockDataTransfer: public WithShiftControlBits {
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using WithShiftControlBits::WithShiftControlBits;
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/// The base register index. i.e. 'Rn'.
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int base() const { return (opcode_ >> 16) & 0xf; }
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/// A bitfield indicating which registers to load or store.
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int register_list() const { return opcode_ & 0xffff; }
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};
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//
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// Coprocessor data operation.
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//
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struct CoprocessorDataOperationFlags {
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constexpr CoprocessorDataOperationFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr int operation() const { return (flags_ >> (FlagsStartBit - 20)) & 0xf; }
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private:
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uint8_t flags_;
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};
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struct CoprocessorDataOperation {
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constexpr CoprocessorDataOperation(uint32_t opcode) noexcept : opcode_(opcode) {}
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int operand1() { return (opcode_ >> 16) & 0xf; }
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int operand2() { return opcode_ & 0xf; }
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int destination() { return (opcode_ >> 12) & 0xf; }
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int coprocessor() { return (opcode_ >> 8) & 0xf; }
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int information() { return (opcode_ >> 5) & 0x7; }
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private:
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uint32_t opcode_;
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};
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//
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// Coprocessor register transfer.
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//
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struct CoprocessorRegisterTransferFlags {
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constexpr CoprocessorRegisterTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr int operation() const { return (flags_ >> (FlagsStartBit - 20)) & 0x7; }
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private:
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uint8_t flags_;
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};
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struct CoprocessorRegisterTransfer {
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constexpr CoprocessorRegisterTransfer(uint32_t opcode) noexcept : opcode_(opcode) {}
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int operand1() { return (opcode_ >> 16) & 0xf; }
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int operand2() { return opcode_ & 0xf; }
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int destination() { return (opcode_ >> 12) & 0xf; }
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int coprocessor() { return (opcode_ >> 8) & 0xf; }
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int information() { return (opcode_ >> 5) & 0x7; }
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private:
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uint32_t opcode_;
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};
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//
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// Coprocessor data transfer.
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//
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struct CoprocessorDataTransferFlags {
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constexpr CoprocessorDataTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr bool pre_index() { return flag_bit<24>(flags_); }
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constexpr bool add_offset() { return flag_bit<23>(flags_); }
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constexpr bool transfer_length() { return flag_bit<22>(flags_); }
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constexpr bool write_back_address() { return flag_bit<21>(flags_); }
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private:
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uint8_t flags_;
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};
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struct CoprocessorDataTransfer {
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constexpr CoprocessorDataTransfer(uint32_t opcode) noexcept : opcode_(opcode) {}
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int base() { return (opcode_ >> 16) & 0xf; }
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int source() { return (opcode_ >> 12) & 0xf; }
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int destination() { return (opcode_ >> 12) & 0xf; }
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int coprocessor() { return (opcode_ >> 8) & 0xf; }
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int offset() { return opcode_ & 0xff; }
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private:
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uint32_t opcode_;
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};
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/// Operation mapper; use the free function @c dispatch as defined below.
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struct OperationMapper {
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template <int i, typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &scheduler) {
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constexpr auto partial = uint32_t(i << 20);
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const auto condition = Condition(instruction >> 28);
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// Cf. the ARM2 datasheet, p.45. Tests below match its ordering
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// other than that 'undefined' is the fallthrough case. More specific
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// page references are provided were more detailed versions of the
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// decoding are depicted.
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// Data processing; cf. p.17.
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if constexpr (((partial >> 26) & 0b11) == 0b00) {
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constexpr auto operation = Operation(int(Operation::AND) + ((partial >> 21) & 0xf));
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scheduler.template perform<operation, i>(
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condition,
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DataProcessing(instruction)
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);
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return;
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}
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// Multiply and multiply-accumulate (MUL, MLA); cf. p.23.
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if constexpr (((partial >> 22) & 0b111'111) == 0b000'000) {
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// This implementation provides only eight bits baked into the template parameters so
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// an additional dynamic test is required to check whether this is really, really MUL or MLA.
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if(((instruction >> 4) & 0b1111) == 0b1001) {
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constexpr bool is_mla = partial & (1 << 21);
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scheduler.template perform<is_mla ? Operation::MLA : Operation::MUL, i>(
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condition,
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Multiply(instruction)
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);
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return;
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}
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}
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// Single data transfer (LDR, STR); cf. p.25.
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if constexpr (((partial >> 26) & 0b11) == 0b01) {
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constexpr bool is_ldr = partial & (1 << 20);
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scheduler.template perform<is_ldr ? Operation::LDR : Operation::STR, i>(
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condition,
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SingleDataTransfer(instruction)
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);
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return;
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}
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// Block data transfer (LDM, STM); cf. p.29.
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if constexpr (((partial >> 25) & 0b111) == 0b100) {
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constexpr bool is_ldm = partial & (1 << 20);
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scheduler.template perform<is_ldm ? Operation::LDM : Operation::STM, i>(
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condition,
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BlockDataTransfer(instruction)
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);
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return;
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}
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// Branch and branch with link (B, BL); cf. p.15.
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if constexpr (((partial >> 25) & 0b111) == 0b101) {
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constexpr bool is_bl = partial & (1 << 24);
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scheduler.template perform<is_bl ? Operation::BL : Operation::B>(
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condition,
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Branch(instruction)
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);
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return;
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}
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// Software interreupt; cf. p.35.
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if constexpr (((partial >> 24) & 0b1111) == 0b1111) {
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scheduler.software_interrupt(condition);
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return;
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}
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// Both:
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// Coprocessor data operation; cf. p. 37; and
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// Coprocessor register transfers; cf. p. 42.
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if constexpr (((partial >> 24) & 0b1111) == 0b1110) {
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if(instruction & (1 << 4)) {
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// Register transfer.
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const auto parameters = CoprocessorRegisterTransfer(instruction);
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constexpr bool is_mrc = partial & (1 << 20);
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scheduler.template perform<is_mrc ? Operation::MRC : Operation::MCR, i>(
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condition,
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parameters
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);
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} else {
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// Data operation.
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const auto parameters = CoprocessorDataOperation(instruction);
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scheduler.template perform<i>(
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condition,
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parameters
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);
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}
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return;
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}
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// Coprocessor data transfers; cf. p.39.
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if constexpr (((partial >> 25) & 0b111) == 0b110) {
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constexpr bool is_ldc = partial & (1 << 20);
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scheduler.template perform<is_ldc ? Operation::LDC : Operation::STC, i>(
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condition,
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CoprocessorDataTransfer(instruction)
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);
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return;
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}
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// Fallback position.
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scheduler.unknown(instruction);
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}
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};
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/// A brief documentation of the interface expected by @c dispatch below; will be a concept if/when this project adopts C++20.
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struct SampleScheduler {
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// General template arguments:
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//
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// (1) Operation, telling the function which operation to perform. Will always be from the subset
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// implied by the operation category; and
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// (2) Flags, an opaque type which can be converted into a DataProcessingFlags, MultiplyFlags, etc,
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// by simply construction, to provide all flags that can be baked into the template parameters.
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//
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// Arguments are ommitted if not relevant.
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//
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// Function arguments:
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//
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// (1) Condition, indicating the condition code associated with this operation; and
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// (2) An operation-specific encapsulation of the operation code for decoding of fields that didn't
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// fit into the template parameters.
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template <Operation, Flags> void perform(Condition, DataProcessing);
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template <Operation, Flags> void perform(Condition, Multiply);
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template <Operation, Flags> void perform(Condition, SingleDataTransfer);
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template <Operation, Flags> void perform(Condition, BlockDataTransfer);
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template <Operation> void perform(Condition, Branch);
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template <Operation, Flags> void perform(Condition, CoprocessorRegisterTransfer);
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template <Flags> void perform(Condition, CoprocessorDataOperation);
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template<Operation, Flags> void perform(Condition, CoprocessorDataTransfer);
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// Irregular operations.
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void software_interrupt(Condition);
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void unknown(uint32_t opcode);
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};
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/// Decodes @c instruction, making an appropriate call into @c scheduler.
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///
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/// In lieue of C++20, see the sample definition of SampleScheduler above for the expected interface.
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template <typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &scheduler) {
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OperationMapper mapper;
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Reflection::dispatch(mapper, (instruction >> FlagsStartBit) & 0xff, instruction, scheduler);
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}
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}
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