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404 lines
13 KiB
C++
404 lines
13 KiB
C++
//
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// Amiga.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/07/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "Amiga.hpp"
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#include "../../Activity/Source.hpp"
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#include "../MachineTypes.hpp"
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#include "../../Processors/68000/68000.hpp"
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#include "../../Components/6526/6526.hpp"
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#include "../../Analyser/Static/Amiga/Target.hpp"
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#include "../Utility/MemoryPacker.hpp"
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#include "../Utility/MemoryFuzzer.hpp"
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//#define NDEBUG
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#define LOG_PREFIX "[Amiga] "
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#include "../../Outputs/Log.hpp"
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#include "Chipset.hpp"
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namespace Amiga {
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class ConcreteMachine:
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public Activity::Source,
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public CPU::MC68000::BusHandler,
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public MachineTypes::ScanProducer,
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public MachineTypes::TimedMachine,
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public Machine {
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public:
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ConcreteMachine(const Analyser::Static::Amiga::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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mc68000_(*this),
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chipset_(reinterpret_cast<uint16_t *>(memory_.chip_ram.data()), memory_.chip_ram.size() >> 1),
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cia_a_handler_(memory_),
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cia_a_(cia_a_handler_),
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cia_b_(cia_b_handler_)
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{
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(void)target;
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// Temporary: use a hard-coded Kickstart selection.
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constexpr ROM::Name rom_name = ROM::Name::AmigaA500Kickstart13;
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ROM::Request request(rom_name);
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auto roms = rom_fetcher(request);
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if(!request.validate(roms)) {
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throw ROMMachine::Error::MissingROMs;
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}
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Memory::PackBigEndian16(roms.find(rom_name)->second, memory_.kickstart.data());
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// NTSC clock rate: 2*3.579545 = 7.15909Mhz.
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// PAL clock rate: 7.09379Mhz; 227 cycles/line.
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set_clock_rate(7'093'790.0);
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}
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// MARK: - MC68000::BusHandler.
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using Microcycle = CPU::MC68000::Microcycle;
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HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
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//
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// TODO: clean up below.
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//
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// Probably: let the Chipset own the CIAs, killing the need to pass hsyncs/vsyncs
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// and CIA interrupt lines back and forth. Then the two run_fors can return, at most,
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// an interrupt level and a duration. Possibly give the chipset a reference to the
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// 68k so it can set IPL directly?
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// Do a quick advance check for Chip RAM access; add a suitable delay if required.
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Chipset::Changes net_changes;
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HalfCycles access_delay;
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if(cycle.operation & Microcycle::NewAddress && *cycle.address < 0x20'0000) {
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// TODO: shouldn't delay if the overlay bit is set?
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net_changes = chipset_.run_until_cpu_slot();
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access_delay = net_changes.duration;
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}
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// Compute total length.
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const HalfCycles total_length = cycle.length + access_delay;
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// The CIAs are on the E clock.
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cia_divider_ += total_length;
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const HalfCycles e_clocks = cia_divider_.divide(HalfCycles(20));
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if(e_clocks > HalfCycles(0)) {
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cia_a_.run_for(e_clocks);
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cia_b_.run_for(e_clocks);
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}
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net_changes += chipset_.run_for(total_length);
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cia_a_.advance_tod(net_changes.vsyncs);
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cia_b_.advance_tod(net_changes.hsyncs);
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chipset_.set_cia_interrupts(cia_a_.get_interrupt_line(), cia_b_.get_interrupt_line());
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mc68000_.set_interrupt_level(chipset_.get_interrupt_level());
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// Check for assertion of reset.
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if(cycle.operation & Microcycle::Reset) {
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memory_.reset();
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LOG("Reset; PC is around " << PADHEX(8) << mc68000_.get_state().program_counter);
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}
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// Autovector interrupts.
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if(cycle.operation & Microcycle::InterruptAcknowledge) {
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mc68000_.set_is_peripheral_address(true);
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return access_delay;
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}
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// Do nothing if no address is exposed.
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return access_delay;
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// TODO: interrupt acknowledgement.
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// Grab the target address to pick a memory source.
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const uint32_t address = cycle.host_endian_byte_address();
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// Set VPA if this is [going to be] a CIA access.
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mc68000_.set_is_peripheral_address((address & 0xe0'0000) == 0xa0'0000);
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if(!memory_.regions[address >> 18].read_write_mask) {
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if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) {
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// Check for various potential chip accesses.
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// Per the manual:
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//
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// CIA A is: 101x xxxx xx01 rrrr xxxx xxx0 (i.e. loaded into high byte)
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// CIA B is: 101x xxxx xx10 rrrr xxxx xxx1 (i.e. loaded into low byte)
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//
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// but in order to map 0xbfexxx to CIA A and 0xbfdxxx to CIA B, I think
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// these might be listed the wrong way around.
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//
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// Additional assumption: the relevant CIA select lines are connected
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// directly to the chip enables.
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if((address & 0xe0'0000) == 0xa0'0000) {
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const int reg = address >> 8;
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if(cycle.operation & Microcycle::Read) {
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uint16_t result = 0xffff;
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if(!(address & 0x1000)) result &= 0xff00 | (cia_a_.read(reg) << 0);
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if(!(address & 0x2000)) result &= 0x00ff | (cia_b_.read(reg) << 8);
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cycle.set_value16(result);
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} else {
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if(!(address & 0x1000)) cia_a_.write(reg, cycle.value8_low());
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if(!(address & 0x2000)) cia_b_.write(reg, cycle.value8_high());
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}
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LOG("CIA " << (((address >> 12) & 3)^3) << " " << (cycle.operation & Microcycle::Read ? "read " : "write ") << std::dec << (reg & 0xf) << " of " << PADHEX(2) << +cycle.value8_low());
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} else if(address >= 0xdf'f000 && address <= 0xdf'f1be) {
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chipset_.perform(cycle);
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} else {
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// This'll do for open bus, for now.
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if(cycle.operation & Microcycle::Read) {
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cycle.set_value16(0xffff);
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}
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// Don't log for the region that is definitely just ROM this machine doesn't have.
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if(address < 0xf0'0000) {
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LOG("Unmapped " << (cycle.operation & Microcycle::Read ? "read from " : "write to ") << PADHEX(6) << ((*cycle.address)&0xffffff) << " of " << cycle.value16());
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}
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}
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}
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} else {
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// A regular memory access.
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cycle.apply(
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&memory_.regions[address >> 18].contents[address],
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memory_.regions[address >> 18].read_write_mask
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);
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// if(address < 0x4'0000) {
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// switch((cycle.operation | memory_.regions[address >> 18].read_write_mask) & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::PermitRead | Microcycle::PermitWrite)) {
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// default:
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// if(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte)) {
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// printf("Ignored!\n");
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// }
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// break;
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//
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// case Microcycle::SelectWord | Microcycle::Read | Microcycle::PermitRead:
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// case Microcycle::SelectWord | Microcycle::Read | Microcycle::PermitRead | Microcycle::PermitWrite:
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// printf("%04x -> %04x\n", *cycle.address, cycle.value->full);
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// break;
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// case Microcycle::SelectByte | Microcycle::Read | Microcycle::PermitRead:
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// case Microcycle::SelectByte | Microcycle::Read | Microcycle::PermitRead | Microcycle::PermitWrite:
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// printf("%04x -> %02x\n", *cycle.address, cycle.value->halves.low);
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// break;
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// case Microcycle::SelectWord | Microcycle::PermitWrite:
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// case Microcycle::SelectWord | Microcycle::PermitWrite | Microcycle::PermitRead:
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// printf("%04x <- %04x\n", *cycle.address, cycle.value->full);
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// break;
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// case Microcycle::SelectByte | Microcycle::PermitWrite:
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// case Microcycle::SelectByte | Microcycle::PermitWrite | Microcycle::PermitRead:
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// printf("%04x <- %02x\n", *cycle.address, cycle.value->halves.low);
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// break;
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// }
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// }
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}
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return access_delay;
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}
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private:
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CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
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// MARK: - Memory map.
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struct MemoryMap {
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public:
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std::array<uint8_t, 512*1024> chip_ram{};
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std::array<uint8_t, 512*1024> kickstart{0xff};
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struct MemoryRegion {
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uint8_t *contents = nullptr;
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unsigned int read_write_mask = 0;
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} regions[64]; // i.e. top six bits are used as an index.
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MemoryMap() {
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// Address spaces that matter:
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//
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// 00'0000 – 08'0000: chip RAM. [or overlayed KickStart]
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// – 10'0000: extended chip ram for ECS.
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// – 20'0000: auto-config space (/fast RAM).
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// ...
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// bf'd000 – c0'0000: 8250s.
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// c0'0000 – d8'0000: pseudo-fast RAM.
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// ...
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// dc'0000 – dd'0000: optional real-time clock.
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// df'f000 - e0'0000: custom chip registers.
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// ...
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// f0'0000 — : 512kb Kickstart (or possibly just an extra 512kb reserved for hypothetical 1mb Kickstart?).
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// f8'0000 — : 256kb Kickstart if 2.04 or higher.
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// fc'0000 – : 256kb Kickstart otherwise.
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set_region(0xfc'0000, 0x1'00'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
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reset();
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}
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void reset() {
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set_overlay(true);
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}
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void set_overlay(bool enabled) {
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if(overlay_ == enabled) {
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return;
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}
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overlay_ = enabled;
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if(enabled) {
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set_region(0x00'0000, 0x08'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
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} else {
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// Mirror RAM to fill out the address range up to $20'0000.
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set_region(0x00'0000, 0x08'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x08'0000, 0x10'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x10'0000, 0x18'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x18'0000, 0x20'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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}
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}
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private:
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bool overlay_ = false;
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void set_region(int start, int end, uint8_t *base, unsigned int read_write_mask) {
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assert(!(start & ~0xfc'0000));
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assert(!((end - (1 << 18)) & ~0xfc'0000));
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base -= start;
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for(int c = start >> 18; c < end >> 18; c++) {
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regions[c].contents = base;
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regions[c].read_write_mask = read_write_mask;
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}
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}
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} memory_;
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// MARK: - Chipset.
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Chipset chipset_;
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// MARK: - CIAs.
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class CIAAHandler: public MOS::MOS6526::PortHandler {
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public:
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CIAAHandler(MemoryMap &map) : map_(map) {}
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void set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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if(port) {
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// Parallel port output.
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LOG("TODO: parallel output " << PADHEX(2) << +value);
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} else {
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// b7: /FIR1
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// b6: /FIR0
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// b5: /RDY
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// b4: /TRK0
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// b3: /WPRO
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// b2: /CHNG
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// b1: /LED [output]
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// b0: OVL [output]
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LOG("LED & memory map: " << PADHEX(2) << +value);
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if(observer_) {
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observer_->set_led_status(led_name, !(value & 2));
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}
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map_.set_overlay(value & 1);
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}
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}
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uint8_t get_port_input(MOS::MOS6526::Port port) {
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if(port) {
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LOG("TODO: parallel input?");
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} else {
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LOG("TODO: CIA A, port A input — FIR, RDY, TRK0, etc");
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// Announce that TRK0 is upon us.
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return 0xef;
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}
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return 0xff;
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}
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void set_activity_observer(Activity::Observer *observer) {
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observer_ = observer;
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if(observer) {
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observer->register_led(led_name, Activity::Observer::LEDPresentation::Persistent);
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}
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}
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private:
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MemoryMap &map_;
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Activity::Observer *observer_ = nullptr;
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inline static const std::string led_name = "Power";
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} cia_a_handler_;
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struct CIABHandler: public MOS::MOS6526::PortHandler {
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void set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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if(port) {
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// Serial port control.
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//
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// b7: /DTR
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// b6: /RTS
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// b5: /CD
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// b4: /CTS
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// b3: /DSR
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// b2: SEL
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// b1: POUT
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// b0: BUSY
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LOG("TODO: DTR/RTS/etc: " << PADHEX(2) << +value);
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} else {
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// Disk motor control, drive and head selection,
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// and stepper control:
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//
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// b7: /MTR
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// b6: /SEL3
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// b5: /SEL2
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// b4: /SEL1
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// b3: /SEL0
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// b2: /SIDE
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// b1: DIR
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// b0: /STEP
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LOG("TODO: Stepping, etc; " << PADHEX(2) << +value);
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}
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}
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uint8_t get_port_input(MOS::MOS6526::Port) {
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LOG("Unexpected input for CIA B ");
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return 0xff;
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}
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} cia_b_handler_;
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HalfCycles cia_divider_;
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MOS::MOS6526::MOS6526<CIAAHandler, MOS::MOS6526::Personality::P8250> cia_a_;
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MOS::MOS6526::MOS6526<CIABHandler, MOS::MOS6526::Personality::P8250> cia_b_;
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// MARK: - Activity Source
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void set_activity_observer(Activity::Observer *observer) final {
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cia_a_handler_.set_activity_observer(observer);
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}
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// MARK: - MachineTypes::ScanProducer.
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void set_scan_target(Outputs::Display::ScanTarget *scan_target) final {
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chipset_.set_scan_target(scan_target);
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}
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Outputs::Display::ScanStatus get_scaled_scan_status() const {
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return chipset_.get_scaled_scan_status();
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}
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// MARK: - MachineTypes::TimedMachine.
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void run_for(const Cycles cycles) {
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mc68000_.run_for(cycles);
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}
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};
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}
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using namespace Amiga;
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Machine *Machine::Amiga(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
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using Target = Analyser::Static::Amiga::Target;
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const Target *const amiga_target = dynamic_cast<const Target *>(target);
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return new Amiga::ConcreteMachine(*amiga_target, rom_fetcher);
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}
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Machine::~Machine() {}
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