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mirror of https://github.com/TomHarte/CLK.git synced 2024-12-26 09:29:45 +00:00
CLK/Components/DiskII
Thomas Harte 908d3b0ee5 Slightly wrong as to the details, but gets the controller trying to output.
At an initial look, I think the shift register should end up on the data bus for all odd accesses. Need to investigate more thoroughly.
2018-05-16 22:37:22 -04:00
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DiskII.cpp Slightly wrong as to the details, but gets the controller trying to output. 2018-05-16 22:37:22 -04:00
DiskII.hpp Eliminates 'data' register as it doesn't exist; rejigs state machine command set. 2018-05-16 22:09:59 -04:00