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698 lines
23 KiB
Plaintext
698 lines
23 KiB
Plaintext
//
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// 68000ArithmeticTests.m
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// Clock SignalTests
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//
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// Created by Thomas Harte on 28/06/2019.
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//
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// Largely ported from the tests of the Portable 68k Emulator.
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//
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#import <XCTest/XCTest.h>
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#include "68000.hpp"
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#include <array>
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#include <unordered_map>
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#include <unordered_set>
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#include <set>
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/*
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namespace {
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struct RandomStore {
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using CollectionT = std::unordered_map<uint32_t, std::pair<uint8_t, uint8_t>>;
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CollectionT values;
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void flag(uint32_t address, uint8_t participant) {
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values[address].first |= participant;
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}
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bool has(uint32_t address, uint8_t participant) {
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auto entry = values.find(address);
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if(entry == values.end()) return false;
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return entry->second.first & participant;
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}
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uint8_t value(uint32_t address, uint8_t participant) {
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auto entry = values.find(address);
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if(entry != values.end()) {
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entry->second.first |= participant;
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return entry->second.second;
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}
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const uint8_t value = uint8_t(rand() >> 8);
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values[address] = std::make_pair(participant, value);
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return value;
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}
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void clear() {
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values.clear();
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}
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};
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struct Transaction {
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HalfCycles timestamp;
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uint8_t function_code = 0;
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uint32_t address = 0;
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uint16_t value = 0;
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bool address_strobe = false;
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bool same_address = false;
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bool read = false;
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int data_strobes = 0;
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bool operator != (const Transaction &rhs) const {
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if(timestamp != rhs.timestamp) return true;
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// if(function_code != rhs.function_code) return true;
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if(address != rhs.address) return true;
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if(value != rhs.value) return true;
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if(address_strobe != rhs.address_strobe) return true;
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if(data_strobes != rhs.data_strobes) return true;
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if(same_address != rhs.same_address) return true;
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return false;
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}
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void print() const {
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printf("%d: %d%d%d %c %c%c @ %06x %s %04x\n",
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timestamp.as<int>(),
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(function_code >> 2) & 1,
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(function_code >> 1) & 1,
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(function_code >> 0) & 1,
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address_strobe ? 'a' : '-',
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(data_strobes & 1) ? 'b' : '-',
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(data_strobes & 2) ? 'w' : '-',
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address,
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read ? "->" : "<-",
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value);
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}
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};
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struct HarmlessStopException {};
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struct BusHandler {
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BusHandler(RandomStore &_store, uint8_t _participant) : store(_store), participant(_participant) {}
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void will_perform(uint32_t, uint16_t) {
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--instructions;
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if(instructions < 0) {
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throw HarmlessStopException{};
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}
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}
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template <typename Microcycle> HalfCycles perform_bus_operation(const Microcycle &cycle, bool is_supervisor) {
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Transaction transaction;
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// Fill all of the transaction record except the data field; will do that after
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// any potential read.
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if(cycle.operation & Microcycle::InterruptAcknowledge) {
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transaction.function_code = 0b111;
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} else {
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transaction.function_code = is_supervisor ? 0x4 : 0x0;
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transaction.function_code |= (cycle.operation & Microcycle::IsData) ? 0x1 : 0x2;
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}
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transaction.address_strobe = cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress);
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transaction.same_address = cycle.operation & Microcycle::SameAddress;
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transaction.data_strobes = cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord);
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if(cycle.address) transaction.address = *cycle.address & 0xffff'ff;
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transaction.timestamp = time;
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transaction.read = cycle.operation & Microcycle::Read;
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time += cycle.length;
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// Do the operation...
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const uint32_t address = cycle.address ? (*cycle.address & 0xff'ffff) : 0;
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
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default: break;
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case Microcycle::SelectWord | Microcycle::Read:
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if(!store.has(address, participant)) {
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ram[address] = store.value(address, participant);
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}
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if(!store.has(address+1, participant)) {
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ram[address+1] = store.value(address+1, participant);
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}
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cycle.set_value16((ram[address] << 8) | ram[address + 1]);
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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if(!store.has(address, participant)) {
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ram[address] = store.value(address, participant);
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}
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if(address & 1) {
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cycle.set_value8_low(ram[address]);
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} else {
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cycle.set_value8_high(ram[address]);
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}
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break;
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case Microcycle::SelectWord:
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ram[address] = cycle.value8_high();
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ram[address+1] = cycle.value8_low();
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store.flag(address, participant);
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store.flag(address+1, participant);
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break;
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case Microcycle::SelectByte:
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ram[address] = (address & 1) ? cycle.value8_low() : cycle.value8_high();
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store.flag(address, participant);
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break;
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}
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// Add the data value if relevant.
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if(transaction.data_strobes) {
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transaction.value = cycle.value16();
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}
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// Push back only if interesting.
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if(capture_all_transactions || transaction.address_strobe || transaction.data_strobes || transaction.function_code == 7) {
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if(transaction_delay) {
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--transaction_delay;
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// Start counting time only from the first recorded transaction.
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if(!transaction_delay) {
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time = HalfCycles(0);
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}
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} else {
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transactions.push_back(transaction);
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}
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}
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return HalfCycles(0);
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}
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int transaction_delay;
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int instructions;
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bool capture_all_transactions = false;
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HalfCycles time;
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std::vector<Transaction> transactions;
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std::array<uint8_t, 16*1024*1024> ram;
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void set_default_vectors() {
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// Establish that all exception vectors point to 1024-byte blocks of memory.
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for(int c = 0; c < 256; c++) {
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const uint32_t target = (c + 2) << 10;
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const uint32_t address = c << 2;
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ram[address + 0] = uint8_t(target >> 24);
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ram[address + 1] = uint8_t(target >> 16);
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ram[address + 2] = uint8_t(target >> 8);
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ram[address + 3] = uint8_t(target >> 0);
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store.flag(address+0, participant);
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store.flag(address+1, participant);
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store.flag(address+2, participant);
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store.flag(address+3, participant);
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}
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}
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RandomStore &store;
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const uint8_t participant;
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};
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using OldProcessor = CPU::MC68000::Processor<BusHandler, true, true>;
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using NewProcessor = CPU::MC68000Mk2::Processor<BusHandler, true, true, true>;
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template <typename M68000> struct Tester {
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Tester(RandomStore &store, uint8_t participant) : bus_handler(store, participant), processor(bus_handler) {}
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void run_instructions(int instructions) {
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bus_handler.instructions = instructions;
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try {
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processor.run_for(HalfCycles(5000)); // Arbitrary, but will definitely exceed any one instruction (by quite a distance).
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} catch (const HarmlessStopException &) {}
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}
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void reset_with_opcode(uint16_t opcode) {
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bus_handler.transactions.clear();
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bus_handler.set_default_vectors();
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const uint32_t address = 3 << 10;
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bus_handler.ram[address + 0] = uint8_t(opcode >> 8);
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bus_handler.ram[address + 1] = uint8_t(opcode >> 0);
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bus_handler.store.flag(address, bus_handler.participant);
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bus_handler.store.flag(address+1, bus_handler.participant);
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bus_handler.transaction_delay = 12; // i.e. ignore everything from the RESET sequence.
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bus_handler.time = HalfCycles(0);
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processor.reset();
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}
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BusHandler bus_handler;
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M68000 processor;
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};
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void print_state(FILE *target, const CPU::MC68000Mk2::State &state, const std::vector<Transaction> &transactions, bool is_initial) {
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for(int c = 0; c < 8; c++) {
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fprintf(target, "\"d%d\": %u, ", c, state.registers.data[c]);
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}
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for(int c = 0; c < 7; c++) {
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fprintf(target, "\"a%d\": %u, ", c, state.registers.address[c]);
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}
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fprintf(target, "\"usp\": %u, ", state.registers.user_stack_pointer);
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fprintf(target, "\"ssp\": %u, ", state.registers.supervisor_stack_pointer);
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fprintf(target, "\"sr\": %u, ", state.registers.status);
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fprintf(target, "\"pc\": %u, ", state.registers.program_counter - 4);
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fprintf(target, "\"prefetch\": [%u, %u], ", state.prefetch[0], state.prefetch[1]);
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fprintf(target, "\"ram\": [");
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// Compute RAM from transactions; if this is the initial state then RAM should
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// be everything that was subject to a read which had not previously been
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// subject to a write. Otherwise it can just be everything.
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std::unordered_map<uint32_t, uint8_t> ram;
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if(is_initial) {
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std::unordered_set<uint32_t> written_addresses;
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for(const auto &transaction: transactions) {
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switch(transaction.data_strobes) {
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default: continue;
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case 1:
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if(transaction.read) {
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if(ram.find(transaction.address) == ram.end()) {
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ram[transaction.address] = transaction.value;
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}
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} else {
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written_addresses.insert(transaction.address);
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}
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break;
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case 2:
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if(transaction.read) {
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if(ram.find(transaction.address) == ram.end()) {
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ram[transaction.address] = uint8_t(transaction.value >> 8);
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}
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if(ram.find(transaction.address+1) == ram.end()) {
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ram[transaction.address+1] = uint8_t(transaction.value);
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}
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} else {
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written_addresses.insert(transaction.address);
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written_addresses.insert(transaction.address + 1);
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}
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break;
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}
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}
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} else {
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for(const auto &transaction: transactions) {
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switch(transaction.data_strobes) {
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default: continue;
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case 1:
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ram[transaction.address] = transaction.value;
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break;
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case 2:
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ram[transaction.address] = uint8_t(transaction.value >> 8);
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ram[transaction.address+1] = uint8_t(transaction.value);
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break;
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}
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}
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}
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bool is_first = true;
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for(const auto &pair: ram) {
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if(!is_first) fprintf(target, ", ");
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is_first = false;
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fprintf(target, "[%d, %d]", pair.first, pair.second);
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}
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fprintf(target, "]");
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}
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void print_transactions(FILE *target, const std::vector<Transaction> &transactions, HalfCycles end) {
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auto iterator = transactions.begin();
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bool is_first = true;
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do {
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if(!is_first) fprintf(target, ", ");
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is_first = false;
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fprintf(target, "[");
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auto next = iterator + 1;
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// Attempt to pair off transactions to reproduct YACHT notation.
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bool is_access = true;
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if(!iterator->address_strobe && !iterator->data_strobes) {
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fprintf(target, "\"n\", ");
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is_access = false;
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} else {
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assert(!iterator->data_strobes);
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// Check how many transactions this address persists for;
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// that'll allow a TAS to be recognised here.
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while(next->same_address && next != transactions.end()) {
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++next;
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}
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--next;
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if(next == iterator + 1) {
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if(next->read) {
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fprintf(target, "\"r\", ");
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} else {
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fprintf(target, "\"w\", ");
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}
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} else {
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fprintf(target, "\"t\", ");
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}
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// Include next in the calculation of time below.
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++next;
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}
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HalfCycles length;
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if(next == transactions.end()) {
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length = end - iterator->timestamp;
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} else {
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length = next->timestamp - iterator->timestamp;
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}
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fprintf(target, "%d", length.as<int>() >> 1);
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if(is_access) {
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// Undo the 'move to one after' step that allowed next to be included
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// in this transaction's cycle count.
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--next;
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fprintf(target, ", %d, ", iterator->function_code);
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fprintf(target, "%d, ", iterator->address & 0xff'ffff);
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switch(next->data_strobes) {
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default: assert(false);
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case 1: fprintf(target, "\".b\", %d", next->value & 0xff); break;
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case 2: fprintf(target, "\".w\", %d", next->value); break;
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}
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++next;
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}
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fprintf(target, "]");
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iterator = next;
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} while(iterator != transactions.end());
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}
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}
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@interface M68000OldVsNewTests : XCTestCase
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@end
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@implementation M68000OldVsNewTests
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//- (void)testGenerate {
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- (void)generate {
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srand(68000);
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InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder;
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RandomStore random_store;
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auto tester = std::make_unique<Tester<NewProcessor>>(random_store, 0x02);
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tester->bus_handler.capture_all_transactions = true;
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// Bucket opcodes by operation.
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std::unordered_map<const char *, std::vector<uint16_t>> opcodesByOperation;
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for(int c = 0; c < 65536; c++) {
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// Test only defined opcodes that aren't STOP (which will never teminate).
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const auto instruction = decoder.decode(uint16_t(c));
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if(
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instruction.operation == InstructionSet::M68k::Operation::Undefined ||
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instruction.operation == InstructionSet::M68k::Operation::STOP
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) {
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continue;
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}
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const auto operation = instruction.operation_string();
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opcodesByOperation[operation].push_back(c);
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}
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// Find somewhere to write to.
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NSString *const tempDir = NSTemporaryDirectory();
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NSLog(@"Outputting to %@", tempDir);
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// Aim to get at least 1,000,000 tests total.
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const auto testsPerOperation = int((1'000'000 + (opcodesByOperation.size() - 1)) / opcodesByOperation.size());
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// Generate by operation.
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NSLog(@"Generating %d tests each for %lu operations", testsPerOperation, opcodesByOperation.size());
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for(const auto &pair: opcodesByOperation) {
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NSLog(@"Generating %s", pair.first);
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NSString *const targetName = [NSString stringWithFormat:@"%@%s.json", tempDir, pair.first];
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FILE *const target = fopen(targetName.UTF8String, "wt");
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const bool force_addresses_even = decoder.decode(pair.second[0]).operation == InstructionSet::M68k::Operation::UNLINK;
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bool is_first_test = true;
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fprintf(target, "[");
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// Test each for the selected number of iterations.
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for(int test = 0; test < testsPerOperation; test++) {
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if(!is_first_test) fprintf(target, ",\n");
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is_first_test = false;
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// Establish with certainty the initial memory state.
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random_store.clear();
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const auto opcodeIndex = int(rand() * pair.second.size() / RAND_MAX);
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const uint16_t opcode = pair.second[opcodeIndex];
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tester->reset_with_opcode(opcode);
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// Generate a random initial register state.
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auto initialState = tester->processor.get_state();
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// Require address pointers to be even 99% of the time, or always for UNLINK.
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const bool addresses_are_even = (rand() >= int(float(RAND_MAX) * 0.99f)) || force_addresses_even;
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for(int c = 0; c < 8; c++) {
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initialState.registers.data[c] = rand() ^ (rand() << 1);
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if(c != 7) {
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initialState.registers.address[c] = rand() ^ (rand() << 1);
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if(addresses_are_even) initialState.registers.address[c] &= ~1;
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}
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}
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// Pick a random status such that:
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//
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// (i) supervisor mode is active 99% of the time;
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// (ii) trace is inactive; and
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// (iii) interrupt level is 7.
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const bool is_supervisor = rand() >= int(float(RAND_MAX) * 0.99f);
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initialState.registers.status = (rand() | (int(is_supervisor) << 13) | (7 << 8)) & ~(1 << 15);
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initialState.registers.user_stack_pointer = rand() << 1;
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initialState.registers.supervisor_stack_pointer = rand() << 1;
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// Set state.
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tester->processor.set_state(initialState);
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// Run for zero instructions to grab the real initial state (i.e. valid prefetch, ssp, etc).
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// Then make sure no transactions or time carry over into the actual instruction.
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tester->run_instructions(0);
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auto populatedInitialState = tester->processor.get_state();
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tester->bus_handler.transactions.clear();
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tester->bus_handler.time = HalfCycles(0);
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// Run for another instruction to do the actual work.
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tester->run_instructions(1);
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const auto finalState = tester->processor.get_state();
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// Output initial state.
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fprintf(target, "{ \"name\": \"%04x [%s] %d\", ", opcode, decoder.decode(opcode).to_string().c_str(), test + 1);
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fprintf(target, "\"initial\": {");
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print_state(target, populatedInitialState, tester->bus_handler.transactions, true);
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// Output final state.
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fprintf(target, "}, \"final\": {");
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print_state(target, finalState, tester->bus_handler.transactions, false);
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// Output total length and bus activity.
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fprintf(target, "}, \"length\": %d, ", tester->bus_handler.time.as<int>() >> 1);
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fprintf(target, "\"transactions\": [");
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print_transactions(target, tester->bus_handler.transactions, tester->bus_handler.time);
|
|
fprintf(target, "]}");
|
|
}
|
|
|
|
fprintf(target, "\n]\n");
|
|
fclose(target);
|
|
}
|
|
}
|
|
|
|
- (void)testOldVsNew {
|
|
RandomStore random_store;
|
|
auto oldTester = std::make_unique<Tester<OldProcessor>>(random_store, 0x01);
|
|
auto newTester = std::make_unique<Tester<NewProcessor>>(random_store, 0x02);
|
|
InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder;
|
|
|
|
// Use a fixed seed to guarantee continuity across repeated runs.
|
|
srand(68000);
|
|
|
|
std::set<InstructionSet::M68k::Operation> ignore_list = {
|
|
//
|
|
// Operations that do the wrong thing on the old 68000:
|
|
//
|
|
InstructionSet::M68k::Operation::ABCD, // Old implementation doesn't match flamewing tests, sometimes produces incorrect results.
|
|
InstructionSet::M68k::Operation::SBCD, // Old implementation doesn't match flamewing tests, sometimes produces incorrect results.
|
|
InstructionSet::M68k::Operation::JSR, // Old implementation ends up skipping stack space if the destination throws an address error.
|
|
InstructionSet::M68k::Operation::MOVEtoSR, // Old implementation doesn't repeat a PC fetch.
|
|
InstructionSet::M68k::Operation::MOVEtoCCR, // Old implementation doesn't repeat a PC fetch.
|
|
|
|
//
|
|
// Operations with definite timing deficiencies versus Yacht.txt on the old 68000:
|
|
//
|
|
InstructionSet::M68k::Operation::CMPAl, // Old implementation omits an idle cycle before -(An)
|
|
InstructionSet::M68k::Operation::CLRb, // Old implementation omits an idle cycle before -(An)
|
|
InstructionSet::M68k::Operation::CLRw, // Old implementation omits an idle cycle before -(An)
|
|
InstructionSet::M68k::Operation::NEGXb, // Old implementation omits an idle cycle before -(An)
|
|
InstructionSet::M68k::Operation::NEGXw, // Old implementation omits an idle cycle before -(An)
|
|
InstructionSet::M68k::Operation::NEGb, // Old implementation omits an idle cycle before -(An)
|
|
InstructionSet::M68k::Operation::NEGw, // Old implementation omits an idle cycle before -(An)
|
|
InstructionSet::M68k::Operation::NOTb, // Old implementation omits an idle cycle before -(An)
|
|
InstructionSet::M68k::Operation::NOTw, // Old implementation omits an idle cycle before -(An)
|
|
InstructionSet::M68k::Operation::TRAP, // Old implementation relocates the idle state near the end to the beginning.
|
|
InstructionSet::M68k::Operation::TRAPV, // Old implementation relocates the idle state near the end to the beginning.
|
|
InstructionSet::M68k::Operation::CHKw, // Old implementation pauses four cycles too long.
|
|
InstructionSet::M68k::Operation::TAS, // Old implementation just doesn't match published cycle counts.
|
|
|
|
//
|
|
// Operations with timing discrepancies between the two 68000 implementations
|
|
// that I think are _more_ accurate now, but possibly still need work:
|
|
//
|
|
InstructionSet::M68k::Operation::MULUw,
|
|
InstructionSet::M68k::Operation::MULSw,
|
|
InstructionSet::M68k::Operation::DIVUw,
|
|
InstructionSet::M68k::Operation::DIVSw,
|
|
};
|
|
|
|
int testsRun = 0;
|
|
std::set<InstructionSet::M68k::Operation> failing_operations;
|
|
for(int c = 0; c < 65536; c++) {
|
|
printf("%04x\n", c);
|
|
|
|
// Test only defined opcodes that aren't STOP (which will never teminate).
|
|
const auto instruction = decoder.decode(uint16_t(c));
|
|
if(
|
|
instruction.operation == InstructionSet::M68k::Operation::Undefined ||
|
|
instruction.operation == InstructionSet::M68k::Operation::STOP
|
|
) {
|
|
continue;
|
|
}
|
|
|
|
// If this operation is known to diverge, ignore it. It's dealt with.
|
|
if(ignore_list.find(instruction.operation) != ignore_list.end()) {
|
|
continue;
|
|
}
|
|
|
|
// Test each 1000 times.
|
|
for(int test = 0; test < 1000; test++) {
|
|
++testsRun;
|
|
|
|
// Establish with certainty the initial memory state.
|
|
random_store.clear();
|
|
newTester->reset_with_opcode(c);
|
|
oldTester->reset_with_opcode(c);
|
|
|
|
// Generate a random initial register state.
|
|
auto oldState = oldTester->processor.get_state();
|
|
auto newState = newTester->processor.get_state();
|
|
|
|
for(int c = 0; c < 8; c++) {
|
|
oldState.data[c] = newState.registers.data[c] = rand() ^ (rand() << 1);
|
|
if(c != 7) oldState.address[c] = newState.registers.address[c] = rand() << 1;
|
|
}
|
|
// Fully to paper over the two 68000s' different ways of doing a faked
|
|
// reset, pick a random status such that:
|
|
//
|
|
// (i) supervisor mode is active;
|
|
// (ii) trace is inactive; and
|
|
// (iii) interrupt level is 7.
|
|
oldState.status = newState.registers.status = (rand() | (1 << 13) | (7 << 8)) & ~(1 << 15);
|
|
oldState.user_stack_pointer = newState.registers.user_stack_pointer = rand() << 1;
|
|
oldState.supervisor_stack_pointer = newState.registers.supervisor_stack_pointer = 0x800;
|
|
|
|
newTester->processor.set_state(newState);
|
|
oldTester->processor.set_state(oldState);
|
|
|
|
// Run a single instruction.
|
|
newTester->run_instructions(1);
|
|
oldTester->run_instructions(1);
|
|
|
|
// Grab final states.
|
|
oldState = oldTester->processor.get_state();
|
|
newState = newTester->processor.get_state();
|
|
|
|
// Compare bus activity only if it doesn't look like an address
|
|
// error occurred. Don't check those as the old 68000 appears to be wrong
|
|
// most of the time about function codes, and that bleeds into the stacked data.
|
|
//
|
|
// Net effect will be 50% fewer transaction comparisons for instructions that
|
|
// can trigger an address error.
|
|
const auto &oldTransactions = oldTester->bus_handler.transactions;
|
|
const auto &newTransactions = newTester->bus_handler.transactions;
|
|
if(oldState.program_counter != 0x1404 || newState.registers.program_counter != 0x1404) {
|
|
auto newIt = newTransactions.begin();
|
|
auto oldIt = oldTransactions.begin();
|
|
while(newIt != newTransactions.end() && oldIt != oldTransactions.end()) {
|
|
if(*newIt != *oldIt) {
|
|
printf("Mismatch in %s, test %d:\n", instruction.to_string().c_str(), test);
|
|
|
|
auto repeatIt = newTransactions.begin();
|
|
while(repeatIt != newIt) {
|
|
repeatIt->print();
|
|
++repeatIt;
|
|
}
|
|
printf("---\n");
|
|
while(newIt != newTransactions.end()) {
|
|
printf("n: "); newIt->print();
|
|
++newIt;
|
|
}
|
|
printf("\n");
|
|
while(oldIt != oldTransactions.end()) {
|
|
printf("o: "); oldIt->print();
|
|
++oldIt;
|
|
}
|
|
printf("\n");
|
|
|
|
failing_operations.insert(instruction.operation);
|
|
break;
|
|
}
|
|
|
|
++newIt;
|
|
++oldIt;
|
|
}
|
|
}
|
|
|
|
// Compare registers.
|
|
bool mismatch = false;
|
|
for(int c = 0; c < 8; c++) {
|
|
mismatch |= oldState.data[c] != newState.registers.data[c];
|
|
if(c != 7) mismatch |= oldState.address[c] != newState.registers.address[c];
|
|
}
|
|
mismatch |= oldState.status != newState.registers.status;
|
|
mismatch |= oldState.program_counter != newState.registers.program_counter;
|
|
mismatch |= oldState.user_stack_pointer != newState.registers.user_stack_pointer;
|
|
mismatch |= oldState.supervisor_stack_pointer != newState.registers.supervisor_stack_pointer;
|
|
|
|
if(mismatch) {
|
|
failing_operations.insert(instruction.operation);
|
|
printf("Registers don't match after %s, test %d\n", instruction.to_string().c_str(), test);
|
|
for(const auto &transaction: newTransactions) {
|
|
printf("n: "); transaction.print();
|
|
}
|
|
printf("\n");
|
|
for(const auto &transaction: oldTransactions) {
|
|
printf("o: "); transaction.print();
|
|
}
|
|
printf("\n");
|
|
|
|
// TODO: more detail here!
|
|
}
|
|
}
|
|
}
|
|
|
|
printf("%d tests run\n", testsRun);
|
|
if(failing_operations.empty()) {
|
|
printf("No failures\n");
|
|
} else {
|
|
printf("\nAll failing operations:\n");
|
|
for(const auto operation: failing_operations) {
|
|
printf("%s,\n", InstructionSet::M68k::to_string(operation));
|
|
}
|
|
}
|
|
|
|
// Mark the test as passed or failed.
|
|
XCTAssert(failing_operations.empty());
|
|
}
|
|
|
|
@end
|
|
*/
|