1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-12-27 01:31:42 +00:00
CLK/Components
2017-01-11 22:03:01 -05:00
..
1770 Added a CRC check for read address, ensured CRC, lost data and record not found are initially reset. 2017-01-01 21:00:25 -05:00
6522
6532
6560
AY38910 It seems likely that an AY divides its clock by 8, not 16. I had conflated wave frequency and counter clock. 2017-01-11 22:03:01 -05:00