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86 lines
2.0 KiB
C++
86 lines
2.0 KiB
C++
//
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// ncr5380.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/08/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#ifndef ncr5380_hpp
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#define ncr5380_hpp
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#include <cstdint>
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#include "SCSI.hpp"
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#include "DirectAccessDevice.hpp"
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#include "../../ClockReceiver/ClockReceiver.hpp"
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#include "../../ClockReceiver/ClockingHintSource.hpp"
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namespace NCR {
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namespace NCR5380 {
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/*!
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Models the NCR 5380, a SCSI interface chip.
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*/
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class NCR5380 final: public ClockingHint::Source {
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public:
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NCR5380(int clock_rate);
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/*! Writes @c value to @c address. */
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void write(int address, uint8_t value);
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/*! Reads from @c address. */
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uint8_t read(int address);
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/*!
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As per its design manual:
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"The NCR 5380 is a clockless device. Delays such as bus
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free delay, bus set delay and bus settle delay are
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implemented using gate delays."
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Therefore this fictitious implementation of an NCR5380 needs
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a way to track time even though the real one doesn't take in
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a clock. This is provided by `run_for`.
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Nevertheless, the clocking doesn't need to be very precise.
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Please provide a clock that is close to 200,000 Hz.
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*/
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void run_for(Cycles);
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/// As per ClockingHint::Source.
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ClockingHint::Preference preferred_clocking() final;
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private:
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// TEMPORARY. For development expediency, the 5380 owns its own
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// SCSI bus and direct access device. These will be moved out.
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SCSI::Bus bus_;
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SCSI::DirectAccessDevice device_;
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const int clock_rate_;
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size_t device_id_;
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SCSI::BusState bus_output_ = SCSI::DefaultBusState;
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uint8_t mode_ = 0xff;
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uint8_t initiator_command_ = 0xff;
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uint8_t data_bus_ = 0xff;
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bool test_mode_ = false;
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bool assert_data_bus_ = false;
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enum class ExecutionState {
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None,
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WatchingBusy,
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} state_ = ExecutionState::None;
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int time_in_state_ = 0;
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bool lost_arbitration_ = false, arbitration_in_progress_ = false;
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void set_execution_state(ExecutionState state);
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};
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}
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}
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#endif /* ncr5380_hpp */
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