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451 lines
13 KiB
C++
451 lines
13 KiB
C++
//
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// x86.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 1/1/21.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "x86.hpp"
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#include <algorithm>
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#include <cassert>
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using namespace CPU::Decoder::x86;
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// Only 8086 is suppoted for now.
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Decoder::Decoder(Model) {}
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Instruction Decoder::decode(const uint8_t *source, size_t length) {
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const uint8_t *const end = source + length;
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// MARK: - Prefixes (if present) and the opcode.
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/// Covers anything which is complete as soon as the opcode is encountered.
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#define MapComplete(value, op, src, dest, size) \
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case value: \
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operation_ = Operation::op; \
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source_ = Source::src; \
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destination_ = Source::dest; \
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phase_ = Phase::ReadyToPost; \
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operation_size_ = size; \
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break
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/// Handles instructions of the form rr, kk and rr, jjkk, i.e. a destination register plus an operand.
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#define MapRegData(value, op, dest, size) \
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case value: \
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operation_ = Operation::op; \
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source_ = Source::Immediate; \
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destination_ = Source::dest; \
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phase_ = Phase::AwaitingDisplacementOrOperand; \
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operand_size_ = size; \
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break
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/// Handles instructions of the form Ax, jjkk where the latter is implicitly an address.
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#define MapRegAddr(value, op, dest, op_size, addr_size) \
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case value: \
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operation_ = Operation::op; \
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destination_ = Source::dest; \
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source_ = Source::DirectAddress; \
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phase_ = Phase::AwaitingDisplacementOrOperand; \
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operand_size_ = addr_size; \
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operation_size_ = op_size; \
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break
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/// Handles instructions of the form jjkk, Ax where the former is implicitly an address.
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#define MapAddrReg(value, op, source, op_size, addr_size) \
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case value: \
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operation_ = Operation::op; \
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source_ = Source::source; \
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destination_ = Source::DirectAddress; \
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phase_ = Phase::AwaitingDisplacementOrOperand; \
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operand_size_ = addr_size; \
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operation_size_ = op_size; \
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break
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/// Covers both `mem/reg, reg` and `reg, mem/reg`.
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#define MapMemRegReg(value, op, format, size) \
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case value: \
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operation_ = Operation::op; \
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phase_ = Phase::ModRegRM; \
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modregrm_format_ = ModRegRMFormat::format; \
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operand_size_ = 0; \
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operation_size_ = size; \
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break
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/// Handles JO, JNO, JB, etc — jumps with a single byte displacement.
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#define MapJump(value, op) \
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case value: \
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operation_ = Operation::op; \
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phase_ = Phase::AwaitingDisplacementOrOperand; \
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operand_size_ = 1; \
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break
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/// Handles far CALL and far JMP — fixed four byte operand operations.
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#define MapFar(value, op) \
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case value: \
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operation_ = Operation::op; \
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phase_ = Phase::AwaitingDisplacementOrOperand; \
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operand_size_ = 4; \
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break
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while(phase_ == Phase::Instruction && source != end) {
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// Retain the instruction byte, in case additional decoding is deferred
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// to the ModRegRM byte.
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instr_ = *source;
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++source;
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++consumed_;
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switch(instr_) {
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default: {
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const Instruction instruction(consumed_);
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reset_parsing();
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return instruction;
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}
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#define PartialBlock(start, operation) \
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MapMemRegReg(start + 0x00, operation, MemReg_Reg, 1); \
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MapMemRegReg(start + 0x01, operation, MemReg_Reg, 2); \
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MapMemRegReg(start + 0x02, operation, Reg_MemReg, 1); \
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MapMemRegReg(start + 0x03, operation, Reg_MemReg, 2); \
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MapRegData(start + 0x04, operation, AL, 1); \
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MapRegData(start + 0x05, operation, AX, 2);
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PartialBlock(0x00, ADD);
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MapComplete(0x06, PUSH, ES, None, 2);
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MapComplete(0x07, POP, ES, None, 2);
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PartialBlock(0x08, OR);
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MapComplete(0x0e, PUSH, CS, None, 2);
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// 0x0f: not used.
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PartialBlock(0x10, ADC);
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MapComplete(0x16, PUSH, SS, None, 2);
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MapComplete(0x17, POP, SS, None, 2);
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PartialBlock(0x18, SBB);
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MapComplete(0x1e, PUSH, DS, None, 2);
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MapComplete(0x1f, POP, DS, None, 2);
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PartialBlock(0x20, AND);
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case 0x26: segment_override_ = Source::ES; break;
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MapComplete(0x27, DAA, None, None, 1);
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PartialBlock(0x28, SUB);
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case 0x2e: segment_override_ = Source::CS; break;
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MapComplete(0x2f, DAS, None, None, 1);
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PartialBlock(0x30, XOR);
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case 0x36: segment_override_ = Source::SS; break;
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MapComplete(0x37, AAA, None, None, 1);
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PartialBlock(0x38, CMP);
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case 0x3e: segment_override_ = Source::DS; break;
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MapComplete(0x3f, AAS, None, None, 1);
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#undef PartialBlock
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#define RegisterBlock(start, operation) \
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MapComplete(start + 0x00, operation, AX, AX, 2); \
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MapComplete(start + 0x01, operation, CX, CX, 2); \
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MapComplete(start + 0x02, operation, DX, DX, 2); \
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MapComplete(start + 0x03, operation, BX, BX, 2); \
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MapComplete(start + 0x04, operation, SP, SP, 2); \
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MapComplete(start + 0x05, operation, BP, BP, 2); \
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MapComplete(start + 0x06, operation, SI, SI, 2); \
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MapComplete(start + 0x07, operation, DI, DI, 2); \
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RegisterBlock(0x40, INC);
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RegisterBlock(0x48, DEC);
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RegisterBlock(0x50, PUSH);
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RegisterBlock(0x58, POP);
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#undef RegisterBlock
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// 0x60–0x6f: not used.
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MapJump(0x70, JO);
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MapJump(0x71, JNO);
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MapJump(0x72, JB);
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MapJump(0x73, JNB);
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MapJump(0x74, JE);
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MapJump(0x75, JNE);
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MapJump(0x76, JBE);
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MapJump(0x77, JNBE);
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MapJump(0x78, JS);
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MapJump(0x79, JNS);
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MapJump(0x7a, JP);
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MapJump(0x7b, JNP);
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MapJump(0x7c, JL);
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MapJump(0x7d, JNL);
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MapJump(0x7e, JLE);
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MapJump(0x7f, JNLE);
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// TODO:
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//
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// 0x80, 0x81, 0x82, 0x83, which all require more
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// input, from the ModRegRM byte.
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MapMemRegReg(0x84, TEST, MemReg_Reg, 1);
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MapMemRegReg(0x85, TEST, MemReg_Reg, 2);
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MapMemRegReg(0x86, XCHG, Reg_MemReg, 1);
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MapMemRegReg(0x87, XCHG, Reg_MemReg, 2);
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MapMemRegReg(0x88, MOV, MemReg_Reg, 1);
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MapMemRegReg(0x89, MOV, MemReg_Reg, 2);
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MapMemRegReg(0x8a, MOV, Reg_MemReg, 1);
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MapMemRegReg(0x8b, MOV, Reg_MemReg, 2);
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// 0x8c: not used.
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MapMemRegReg(0x8d, LEA, Reg_MemReg, 2);
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// MapMemRegReg(0x8e, MOV, SegReg_MemReg, 1); // TODO: SegReg_MemReg
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MapMemRegReg(0x8f, POP, MemRegPOP, 2);
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MapComplete(0x90, NOP, None, None, 0); // Or XCHG AX, AX?
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MapComplete(0x91, XCHG, AX, CX, 2);
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MapComplete(0x92, XCHG, AX, DX, 2);
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MapComplete(0x93, XCHG, AX, BX, 2);
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MapComplete(0x94, XCHG, AX, SP, 2);
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MapComplete(0x95, XCHG, AX, BP, 2);
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MapComplete(0x96, XCHG, AX, SI, 2);
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MapComplete(0x97, XCHG, AX, DI, 2);
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MapComplete(0x98, CBW, None, None, 1);
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MapComplete(0x99, CWD, None, None, 2);
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MapFar(0x9a, CALL);
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MapComplete(0x9b, WAIT, None, None, 0);
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MapComplete(0x9c, PUSHF, None, None, 2);
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MapComplete(0x9d, POPF, None, None, 2);
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MapComplete(0x9e, SAHF, None, None, 1);
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MapComplete(0x9f, LAHF, None, None, 1);
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MapRegAddr(0xa0, MOV, AL, 1, 1); MapRegAddr(0xa1, MOV, AX, 2, 2);
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MapAddrReg(0xa2, MOV, AL, 1, 1); MapAddrReg(0xa3, MOV, AX, 2, 2);
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MapComplete(0xa4, MOVS, None, None, 1);
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MapComplete(0xa5, MOVS, None, None, 2);
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MapComplete(0xa6, CMPS, None, None, 1);
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MapComplete(0xa7, CMPS, None, None, 2);
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MapRegData(0xa8, TEST, AL, 1);
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MapRegData(0xa9, TEST, AX, 2);
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MapComplete(0xaa, STOS, None, None, 1);
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MapComplete(0xab, STOS, None, None, 2);
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MapComplete(0xac, LODS, None, None, 1);
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MapComplete(0xad, LODS, None, None, 2);
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MapComplete(0xae, SCAS, None, None, 1);
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MapComplete(0xaf, SCAS, None, None, 2);
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MapRegData(0xb0, MOV, AL, 1); MapRegData(0xb1, MOV, CL, 1);
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MapRegData(0xb2, MOV, DL, 1); MapRegData(0xb3, MOV, BL, 1);
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MapRegData(0xb4, MOV, AH, 1); MapRegData(0xb5, MOV, CH, 1);
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MapRegData(0xb6, MOV, DH, 1); MapRegData(0xb7, MOV, BH, 1);
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MapRegData(0xb8, MOV, AX, 2); MapRegData(0xb9, MOV, CX, 2);
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MapRegData(0xba, MOV, DX, 2); MapRegData(0xbb, MOV, BX, 2);
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MapRegData(0xbc, MOV, SP, 2); MapRegData(0xbd, MOV, BP, 2);
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MapRegData(0xbe, MOV, SI, 2); MapRegData(0xbf, MOV, DI, 2);
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MapRegData(0xc2, RETN, None, 2);
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MapComplete(0xc3, RETN, None, None, 2);
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MapMemRegReg(0xc4, LES, Reg_MemReg, 4);
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MapMemRegReg(0xc5, LDS, Reg_MemReg, 4);
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MapMemRegReg(0xc6, MOV, MemRegMOV, 1);
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MapMemRegReg(0xc7, MOV, MemRegMOV, 2);
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MapRegData(0xca, RETF, None, 2);
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MapComplete(0xcb, RETF, None, None, 4);
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MapComplete(0xcc, INT3, None, None, 0);
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MapRegData(0xcd, INT, None, 1);
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MapComplete(0xce, INTO, None, None, 0);
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MapComplete(0xcf, IRET, None, None, 0);
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MapRegData(0xd4, AAM, None, 1);
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MapRegData(0xd5, AAD, None, 1);
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MapComplete(0xd7, XLAT, None, None, 1);
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MapMemRegReg(0xd8, ESC, MemReg_Reg, 0);
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MapMemRegReg(0xd9, ESC, MemReg_Reg, 0);
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MapMemRegReg(0xda, ESC, MemReg_Reg, 0);
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MapMemRegReg(0xdb, ESC, MemReg_Reg, 0);
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MapMemRegReg(0xdc, ESC, MemReg_Reg, 0);
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MapMemRegReg(0xdd, ESC, MemReg_Reg, 0);
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MapMemRegReg(0xde, ESC, MemReg_Reg, 0);
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MapMemRegReg(0xdf, ESC, MemReg_Reg, 0);
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MapJump(0xe0, LOOPNE); MapJump(0xe1, LOOPE);
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MapJump(0xe2, LOOP); MapJump(0xe3, JPCX);
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MapRegAddr(0xe4, IN, AL, 1, 1); MapRegAddr(0xe5, IN, AX, 2, 1);
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MapAddrReg(0xe6, OUT, AL, 1, 1); MapAddrReg(0xe7, OUT, AX, 2, 1);
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MapRegData(0xe8, CALL, None, 2);
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MapRegData(0xe9, JMP, None, 2);
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MapFar(0xea, JMP);
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MapJump(0xeb, JMP);
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MapComplete(0xec, IN, DX, AL, 1); MapComplete(0xed, IN, DX, AX, 1);
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MapComplete(0xee, OUT, AL, DX, 1); MapComplete(0xef, OUT, AX, DX, 1);
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MapComplete(0xf4, HLT, None, None, 1);
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MapComplete(0xf5, CMC, None, None, 1);
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MapMemRegReg(0xf6, Invalid, MemRegTEST_to_IDIV, 1);
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MapMemRegReg(0xf7, Invalid, MemRegTEST_to_IDIV, 2);
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MapComplete(0xf8, CLC, None, None, 1);
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MapComplete(0xf9, STC, None, None, 1);
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MapComplete(0xfa, CLI, None, None, 1);
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MapComplete(0xfb, STI, None, None, 1);
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MapComplete(0xfc, CLD, None, None, 1);
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MapComplete(0xfd, STD, None, None, 1);
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/*
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Unimplemented (but should be):
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0x8e,
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0xd0, 0xd1, 0xd2, 0xd3,
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0xfe, 0xff
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[and consider which others are unused but seem to be
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known to consume a second byte?]
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*/
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// Other prefix bytes.
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case 0xf0: lock_ = true; break;
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case 0xf2: repetition_ = Repetition::RepNE; break;
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case 0xf3: repetition_ = Repetition::RepE; break;
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}
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}
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#undef MapInstr
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// MARK: - ModRegRM byte, if any.
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if(phase_ == Phase::ModRegRM && source != end) {
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const uint8_t mod = *source >> 6; // i.e. mode.
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const uint8_t reg = (*source >> 3) & 7; // i.e. register.
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const uint8_t rm = *source & 7; // i.e. register/memory.
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++source;
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++consumed_;
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Source memreg;
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constexpr Source reg_table[3][8] = {
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{},
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{
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Source::AL, Source::CL, Source::DL, Source::BL,
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Source::AH, Source::CH, Source::DH, Source::BH,
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}, {
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Source::AX, Source::CX, Source::DX, Source::BX,
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Source::SP, Source::BP, Source::SI, Source::DI,
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}
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};
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switch(mod) {
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case 0: {
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constexpr Source rm_table[8] = {
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Source::IndBXPlusSI, Source::IndBXPlusDI,
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Source::IndBPPlusSI, Source::IndBPPlusDI,
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Source::IndSI, Source::IndDI,
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Source::DirectAddress, Source::IndBX,
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};
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memreg = rm_table[rm];
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} break;
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default: {
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constexpr Source rm_table[8] = {
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Source::IndBXPlusSI, Source::IndBXPlusDI,
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Source::IndBPPlusSI, Source::IndBPPlusDI,
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Source::IndSI, Source::IndDI,
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Source::IndBP, Source::IndBX,
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};
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memreg = rm_table[rm];
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displacement_size_ = 1 + (mod == 2);
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} break;
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// Other operand is just a register.
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case 3:
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memreg = reg_table[operation_size_][rm];
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break;
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}
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switch(modregrm_format_) {
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case ModRegRMFormat::Reg_MemReg:
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case ModRegRMFormat::MemReg_Reg: {
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if(modregrm_format_ == ModRegRMFormat::Reg_MemReg) {
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source_ = memreg;
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destination_ = reg_table[operation_size_][reg];
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} else {
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source_ = reg_table[operation_size_][reg];
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destination_ = memreg;
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}
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} break;
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case ModRegRMFormat::MemRegTEST_to_IDIV:
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source_ = destination_ = memreg;
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switch(reg) {
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default:
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reset_parsing();
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return Instruction(consumed_);
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case 0: operation_ = Operation::TEST; break;
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case 2: operation_ = Operation::NOT; break;
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case 3: operation_ = Operation::NEG; break;
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case 4: operation_ = Operation::MUL; break;
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case 5: operation_ = Operation::IMUL; break;
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case 6: operation_ = Operation::DIV; break;
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case 7: operation_ = Operation::IDIV; break;
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}
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break;
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case ModRegRMFormat::MemRegPOP:
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source_ = destination_ = memreg;
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if(reg != 0) {
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reset_parsing();
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return Instruction(consumed_);
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}
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break;
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case ModRegRMFormat::MemRegMOV:
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source_ = Source::Immediate;
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destination_ = memreg;
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operand_size_ = operation_size_;
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break;
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default: assert(false);
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}
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phase_ = Phase::AwaitingDisplacementOrOperand;
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}
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// MARK: - Displacement and operand.
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if(phase_ == Phase::AwaitingDisplacementOrOperand && source != end) {
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// TODO: calculate number of expected operands.
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const int required_bytes = displacement_size_ + operand_size_;
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const int outstanding_bytes = required_bytes - operand_bytes_;
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const int bytes_to_consume = std::min(int(end - source), outstanding_bytes);
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source += bytes_to_consume;
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consumed_ += bytes_to_consume;
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operand_bytes_ += bytes_to_consume;
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if(bytes_to_consume == outstanding_bytes) {
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phase_ = Phase::ReadyToPost;
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} else {
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// Provide a genuine measure of further bytes required.
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return Instruction(-(outstanding_bytes - bytes_to_consume));
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}
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}
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// MARK: - Check for completion.
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if(phase_ == Phase::ReadyToPost) {
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Instruction result(operation_, Size(operation_size_), source_, destination_, consumed_);
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reset_parsing();
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phase_ = Phase::Instruction;
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return result;
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}
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// i.e. not done yet.
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return Instruction();
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}
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