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302 lines
9.0 KiB
C++
302 lines
9.0 KiB
C++
//
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// x86.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 1/1/21.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef x86_hpp
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#define x86_hpp
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#include <cstddef>
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#include <cstdint>
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namespace CPU {
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namespace Decoder {
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namespace x86 {
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enum class Model {
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i8086,
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};
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enum class Operation: uint8_t {
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Invalid,
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/// ASCII adjust after addition; source will be AL and destination will be AX.
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AAA,
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/// ASCII adjust before division; destination will be AX and source will be a multiplier.
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AAD,
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/// ASCII adjust after multiplication; destination will be AX and source will be a divider.
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AAM,
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/// ASCII adjust after subtraction; source will be AL and destination will be AX.
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AAS,
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/// Add with carry; source, destination, operand and displacement will be populated appropriately.
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ADC,
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/// Add; source, destination, operand and displacement will be populated appropriately.
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ADD,
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/// And; source, destination, operand and displacement will be populated appropriately.
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AND,
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/// Far call; followed by a 32-bit operand.
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CALLF,
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/// Displacement call; followed by a 16-bit operand providing a call offset.
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CALLD,
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CALLN,
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/// Convert byte into word; source will be AL, destination will be AH.
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CBW,
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/// Clear carry flag; no source or destination provided.
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CLC,
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/// Clear direction flag; no source or destination provided.
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CLD,
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/// Clear interrupt flag; no source or destination provided.
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CLI,
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/// Complement carry flag; no source or destination provided.
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CMC,
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/// Compare; source, destination, operand and displacement will be populated appropriately.
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CMP,
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/// Compare [bytes or words, per operation size]; source and destination implied to be DS:[SI] and ES:[DI].
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CMPS,
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/// Convert word to double word; source will be AX and destination will be DX.
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CWD,
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/// Decimal adjust after addition; source and destination will be AL.
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DAA,
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/// Decimal adjust after subtraction; source and destination will be AL.
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DAS,
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/// Dec; source, destination, operand and displacement will be populated appropriately.
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DEC,
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DIV, ESC, HLT, IDIV, IMUL, IN,
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INC, INT, INT3, INTO, IRET,
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JO, JNO, JB, JNB, JE, JNE, JBE, JNBE,
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JS, JNS, JP, JNP, JL, JNL, JLE, JNLE,
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JMPN,
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JMPF,
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JCXZ,
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LAHF, LDS, LEA,
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LODS, LOOPE, LOOPNE, MOV, MOVS, MUL, NEG, NOP, NOT, OR, OUT,
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POP, POPF, PUSH, PUSHF, RCL, RCR, REP, ROL, ROR, SAHF,
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SAR, SBB, SCAS, SAL, SHR, STC, STD, STI, STOS, SUB, TEST,
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WAIT, XCHG, XLAT, XOR,
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LES, LOOP, JPCX,
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RETF,
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RETN,
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};
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enum class Size: uint8_t {
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Implied = 0,
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Byte = 1,
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Word = 2,
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DWord = 4,
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};
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enum class Source: uint8_t {
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None,
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CS, DS, ES, SS,
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AL, AH, AX,
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BL, BH, BX,
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CL, CH, CX,
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DL, DH, DX,
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SI, DI,
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BP, SP,
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IndBXPlusSI,
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IndBXPlusDI,
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IndBPPlusSI,
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IndBPPlusDI,
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IndSI,
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IndDI,
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DirectAddress,
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IndBP,
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IndBX,
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Immediate
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};
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enum class Repetition: uint8_t {
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None, RepE, RepNE
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};
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class Instruction {
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public:
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Operation operation = Operation::Invalid;
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private:
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// b0, b1: a Repetition;
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// b2+: operation size.
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uint8_t repetition_size_ = 0;
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// b0–b5: source;
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// b6–b11: destination;
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// b12–b14: segment override;
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// b15: lock.
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uint16_t sources_ = 0;
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// Unpackable fields.
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int16_t displacement_ = 0;
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uint16_t operand_ = 0; // ... or used to store a segment for far operations.
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public:
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Source source() const { return Source(sources_ & 0x3f); }
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Source destination() const { return Source((sources_ >> 6) & 0x3f); }
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bool lock() const { return sources_ & 0x8000; }
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Source segment_override() const { return Source((sources_ >> 12) & 7); }
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Repetition repetition() const { return Repetition(repetition_size_ & 3); }
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Size operation_size() const { return Size(repetition_size_ >> 2); }
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uint16_t segment() const { return uint16_t(operand_); }
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int16_t displacement() const { return displacement_; }
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uint16_t operand() const { return operand_; }
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Instruction() noexcept {}
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Instruction(
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Operation operation,
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Source source,
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Source destination,
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bool lock,
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Source segment_override,
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Repetition repetition,
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Size operation_size,
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int16_t displacement,
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uint16_t operand) noexcept :
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operation(operation),
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repetition_size_(uint8_t((int(operation_size) << 2) | int(repetition))),
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sources_(uint16_t(
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int(source) |
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(int(destination) << 6) |
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(int(segment_override) << 12) |
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(int(lock) << 15)
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)),
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displacement_(displacement),
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operand_(operand) {}
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};
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static_assert(sizeof(Instruction) <= 8);
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/*!
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Implements Intel x86 instruction decoding.
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This is an experimental implementation; it has not yet undergone significant testing.
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*/
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struct Decoder {
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public:
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Decoder(Model model);
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/*!
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@returns an @c Instruction plus a size; a positive size to indicate successful decoding; a
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negative size specifies the [negatived] number of further bytes the caller should ideally
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collect before calling again. The caller is free to call with fewer, but may not get a decoded
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instruction in response, and the decoder may still not be able to complete decoding
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even if given that number of bytes.
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*/
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std::pair<int, Instruction> decode(const uint8_t *source, size_t length);
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private:
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enum class Phase {
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/// Captures all prefixes and continues until an instruction byte is encountered.
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Instruction,
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/// Receives a ModRegRM byte and either populates the source_ and dest_ fields appropriately
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/// or completes decoding of the instruction, as per the instruction format.
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ModRegRM,
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/// Waits for sufficiently many bytes to pass for the required displacement and operand to be captured.
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/// Cf. displacement_size_ and operand_size_.
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AwaitingDisplacementOrOperand,
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/// Forms and returns an Instruction, and resets parsing state.
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ReadyToPost
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} phase_ = Phase::Instruction;
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/// During the ModRegRM phase, format dictates interpretation of the ModRegRM byte.
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///
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/// During the ReadyToPost phase, format determines how transiently-recorded fields
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/// are packaged into an Instruction.
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enum class ModRegRMFormat: uint8_t {
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// Parse the ModRegRM for mode, register and register/memory fields
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// and populate the source_ and destination_ fields appropriate.
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MemReg_Reg,
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Reg_MemReg,
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// Parse for mode and register/memory fields, populating both
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// source_ and destination_ fields with the result. Use the 'register'
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// field to pick an operation from the TEST/NOT/NEG/MUL/IMUL/DIV/IDIV group.
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MemRegTEST_to_IDIV,
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// Parse for mode and register/memory fields, populating both
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// source_ and destination_ fields with the result. Use the 'register'
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// field to check for the POP operation.
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MemRegPOP,
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// Parse for mode and register/memory fields, populating both
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// the destination_ field with the result and setting source_ to Immediate.
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// Use the 'register' field to check for the MOV operation.
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MemRegMOV,
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// Parse for mode and register/memory fields, populating the
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// destination_ field with the result. Use the 'register' field
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// to pick an operation from the ROL/ROR/RCL/RCR/SAL/SHR/SAR group.
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MemRegROL_to_SAR,
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// Parse for mode and register/memory fields, populating the
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// destination_ field with the result. Use the 'register' field
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// to pick an operation from the ADD/OR/ADC/SBB/AND/SUB/XOR/CMP group and
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// waits for an operand equal to the operation size.
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MemRegADD_to_CMP,
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// Parse for mode and register/memory fields, populating the
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// source_ field with the result. Fills destination_ with a segment
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// register based on the reg field.
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SegReg,
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// Parse for mode and register/memory fields, populating the
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// source_ and destination_ fields with the result. Uses the
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// 'register' field to pick INC or DEC.
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MemRegINC_DEC,
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// Parse for mode and register/memory fields, populating the
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// source_ and destination_ fields with the result. Uses the
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// 'register' field to pick from INC/DEC/CALL/JMP/PUSH, altering
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// the source to ::Immediate and setting an operand size if necessary.
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MemRegINC_to_PUSH,
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} modregrm_format_ = ModRegRMFormat::MemReg_Reg;
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// Ephemeral decoding state.
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Operation operation_ = Operation::Invalid;
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uint8_t instr_ = 0x00; // TODO: is this desired, versus loading more context into ModRegRMFormat?
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int consumed_ = 0, operand_bytes_ = 0;
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// Source and destination locations.
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Source source_ = Source::None;
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Source destination_ = Source::None;
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// Immediate fields.
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int16_t displacement_ = 0;
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uint16_t operand_ = 0;
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// Facts about the instruction.
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int displacement_size_ = 0; // i.e. size of in-stream displacement, if any.
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int operand_size_ = 0; // i.e. size of in-stream operand, if any.
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int operation_size_ = 0; // i.e. size of data manipulated by the operation.
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// Prefix capture fields.
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Repetition repetition_ = Repetition::None;
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bool lock_ = false;
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Source segment_override_ = Source::None;
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/// Resets size capture and all fields with default values.
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void reset_parsing() {
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consumed_ = operand_bytes_ = 0;
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displacement_size_ = operand_size_ = 0;
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lock_ = false;
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segment_override_ = Source::None;
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repetition_ = Repetition::None;
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}
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};
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}
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}
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}
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#endif /* x86_hpp */
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