mirror of https://github.com/TomHarte/CLK.git
88 lines
2.0 KiB
C++
88 lines
2.0 KiB
C++
//
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// ncr5380.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/08/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include <cstdint>
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#include "../../Storage/MassStorage/SCSI/SCSI.hpp"
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namespace NCR::NCR5380 {
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/*!
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Models the NCR 5380, a SCSI interface chip.
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*/
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class NCR5380 final: public SCSI::Bus::Observer {
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public:
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NCR5380(SCSI::Bus &bus, int clock_rate);
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/*! Writes @c value to @c address. */
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void write(int address, uint8_t value, bool dma_acknowledge = false);
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/*! Reads from @c address. */
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uint8_t read(int address, bool dma_acknowledge = false);
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/*! @returns The SCSI ID assigned to this device. */
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size_t scsi_id();
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/*! @return @c true if DMA request is active; @c false otherwise. */
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bool dma_request();
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/*! Signals DMA acknowledge with a simultaneous read. */
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uint8_t dma_acknowledge();
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/*! Signals DMA acknowledge with a simultaneous write. */
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void dma_acknowledge(uint8_t);
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private:
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SCSI::Bus &bus_;
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const int clock_rate_;
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size_t device_id_;
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SCSI::BusState bus_output_ = SCSI::DefaultBusState;
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SCSI::BusState expected_phase_ = SCSI::DefaultBusState;
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uint8_t mode_ = 0xff;
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uint8_t initiator_command_ = 0xff;
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uint8_t data_bus_ = 0xff;
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uint8_t target_command_ = 0xff;
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bool test_mode_ = false;
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bool assert_data_bus_ = false;
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bool dma_request_ = false;
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bool dma_acknowledge_ = false;
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bool end_of_dma_ = false;
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bool irq_ = false;
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bool phase_mismatch_ = false;
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enum class ExecutionState {
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None,
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WaitingForBusy,
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WatchingBusy,
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PerformingDMA,
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} state_ = ExecutionState::None;
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enum class DMAOperation {
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Ready,
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Send,
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TargetReceive,
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InitiatorReceive
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} dma_operation_ = DMAOperation::Ready;
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bool lost_arbitration_ = false, arbitration_in_progress_ = false;
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void set_execution_state(ExecutionState state);
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SCSI::BusState target_output() const;
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void update_control_output();
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void scsi_bus_did_change(SCSI::Bus *, SCSI::BusState new_state, double time_since_change) final;
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bool phase_matches() const;
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};
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}
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