mirror of
https://github.com/TomHarte/CLK.git
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461 lines
14 KiB
Plaintext
461 lines
14 KiB
Plaintext
//
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// ARMDecoderTests.m
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// Clock Signal
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//
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// Created by Thomas Harte on 16/02/2024.
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// Copyright 2024 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include "../../../InstructionSets/ARM/BarrelShifter.hpp"
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#include "../../../InstructionSets/ARM/OperationMapper.hpp"
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#include "../../../InstructionSets/ARM/Registers.hpp"
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#include "../../../Numeric/Carry.hpp"
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using namespace InstructionSet::ARM;
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namespace {
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struct Memory {
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template <typename IntT>
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bool write(uint32_t address, IntT source, Mode mode, bool trans) {
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(void)address;
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(void)source;
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(void)mode;
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(void)trans;
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return true;
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}
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template <typename IntT>
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bool read(uint32_t address, IntT &source, Mode mode, bool trans) {
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(void)address;
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(void)source;
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(void)mode;
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(void)trans;
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return true;
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}
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};
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template <typename MemoryT>
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struct Scheduler {
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bool should_schedule(Condition condition) {
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return registers_.test(condition);
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}
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template <bool allow_register, bool set_carry, typename FieldsT>
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uint32_t decode_shift(FieldsT fields, uint32_t &rotate_carry, uint32_t pc_offset) {
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uint32_t shift_amount;
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if constexpr (allow_register) {
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if(fields.shift_count_is_register()) {
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// "When R15 appears in either of the Rn or Rs positions it will give the value
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// of the PC alone, with the PSR bits replaced by zeroes. ...
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//
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// If a register is used to specify the shift amount, the
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// PC will be 8 bytes ahead when used as Rs."
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shift_amount =
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fields.shift_register() == 15 ?
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registers_.pc(8) :
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registers_.active[fields.shift_register()];
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} else {
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shift_amount = fields.shift_amount();
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}
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} else {
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shift_amount = fields.shift_amount();
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}
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// "When R15 appears in the Rm position it will give the value of the PC together
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// with the PSR flags to the barrel shifter. ...
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//
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// If the shift amount is specified in the instruction, the PC will be 8 bytes ahead.
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// If a register is used to specify the shift amount, the PC will be ... 12 bytes ahead
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// when used as Rn or Rm."
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uint32_t operand2;
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if(fields.operand2() == 15) {
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operand2 = registers_.pc_status(pc_offset);
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} else {
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operand2 = registers_.active[fields.operand2()];
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}
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shift<set_carry>(fields.shift_type(), operand2, shift_amount, rotate_carry);
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return operand2;
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}
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template <Flags f> void perform(DataProcessing fields) {
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constexpr DataProcessingFlags flags(f);
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const bool shift_by_register = !flags.operand2_is_immediate() && fields.shift_count_is_register();
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// Write a raw result into the PC proxy if the target is R15; it'll be stored properly later.
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uint32_t pc_proxy = 0;
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auto &destination = fields.destination() == 15 ? pc_proxy : registers_.active[fields.destination()];
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// "When R15 appears in either of the Rn or Rs positions it will give the value
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// of the PC alone, with the PSR bits replaced by zeroes. ...
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//
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// If the shift amount is specified in the instruction, the PC will be 8 bytes ahead.
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// If a register is used to specify the shift amount, the PC will be ... 12 bytes ahead
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// when used as Rn or Rm."
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const uint32_t operand1 =
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(fields.operand1() == 15) ?
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registers_.pc(shift_by_register ? 12 : 8) :
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registers_.active[fields.operand1()];
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uint32_t operand2;
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uint32_t rotate_carry = registers_.c();
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// Populate carry from the shift only if it'll be used.
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constexpr bool shift_sets_carry = is_logical(flags.operation()) && flags.set_condition_codes();
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// Get operand 2.
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if constexpr (flags.operand2_is_immediate()) {
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operand2 = fields.immediate();
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if(fields.rotate()) {
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shift<ShiftType::RotateRight, shift_sets_carry>(operand2, fields.rotate(), rotate_carry);
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}
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} else {
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operand2 = decode_shift<true, shift_sets_carry>(fields, rotate_carry, shift_by_register ? 12 : 8);
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}
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// Perform the data processing operation.
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uint32_t conditions = 0;
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switch(flags.operation()) {
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// Logical operations.
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case DataProcessingOperation::AND: conditions = destination = operand1 & operand2; break;
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case DataProcessingOperation::EOR: conditions = destination = operand1 ^ operand2; break;
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case DataProcessingOperation::ORR: conditions = destination = operand1 | operand2; break;
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case DataProcessingOperation::BIC: conditions = destination = operand1 & ~operand2; break;
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case DataProcessingOperation::MOV: conditions = destination = operand2; break;
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case DataProcessingOperation::MVN: conditions = destination = ~operand2; break;
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case DataProcessingOperation::TST: conditions = operand1 & operand2; break;
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case DataProcessingOperation::TEQ: conditions = operand1 ^ operand2; break;
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case DataProcessingOperation::ADD:
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case DataProcessingOperation::ADC:
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case DataProcessingOperation::CMN:
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conditions = operand1 + operand2;
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if constexpr (flags.operation() == DataProcessingOperation::ADC) {
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conditions += registers_.c();
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}
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if constexpr (flags.set_condition_codes()) {
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registers_.set_c(Numeric::carried_out<true, 31>(operand1, operand2, conditions));
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registers_.set_v(Numeric::overflow<true>(operand1, operand2, conditions));
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}
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if constexpr (!is_comparison(flags.operation())) {
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destination = conditions;
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}
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break;
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case DataProcessingOperation::SUB:
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case DataProcessingOperation::SBC:
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case DataProcessingOperation::CMP:
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conditions = operand1 - operand2;
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if constexpr (flags.operation() == DataProcessingOperation::SBC) {
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conditions -= registers_.c();
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}
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if constexpr (flags.set_condition_codes()) {
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registers_.set_c(Numeric::carried_out<false, 31>(operand1, operand2, conditions));
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registers_.set_v(Numeric::overflow<false>(operand1, operand2, conditions));
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}
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if constexpr (!is_comparison(flags.operation())) {
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destination = conditions;
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}
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break;
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case DataProcessingOperation::RSB:
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case DataProcessingOperation::RSC:
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conditions = operand2 - operand1;
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if constexpr (flags.operation() == DataProcessingOperation::RSC) {
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conditions -= registers_.c();
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}
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if constexpr (flags.set_condition_codes()) {
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registers_.set_c(Numeric::carried_out<false, 31>(operand2, operand1, conditions));
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registers_.set_v(Numeric::overflow<false>(operand2, operand1, conditions));
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}
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destination = conditions;
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break;
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}
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if constexpr (flags.set_condition_codes()) {
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// "When Rd is a register other than R15, the condition code flags in the PSR may be
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// updated from the ALU flags as described above. When Rd is R15 and the S flag in
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// the instruction is set, the PSR is overwritten by the corresponding ALU result.
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//
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// ... if the instruction is of a type which does not normally produce a result
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// (CMP, CMN, TST, TEQ) but Rd is R15 and the S bit is set, the result will be used in
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// this case to update those PSR flags which are not protected by virtue of the
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// processor mode."
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if(fields.destination() == 15) {
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if constexpr (is_comparison(flags.operation())) {
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registers_.set_status(pc_proxy);
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} else {
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registers_.set_status(pc_proxy);
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registers_.set_pc(pc_proxy);
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}
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} else {
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// Set N and Z in a unified way.
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registers_.set_nz(conditions);
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// Set C from the barrel shifter if applicable.
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if constexpr (shift_sets_carry) {
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registers_.set_c(rotate_carry);
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}
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}
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} else {
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// "If the S flag is clear when Rd is R15, only the 24 PC bits of R15 will be written."
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if(fields.destination() == 15) {
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registers_.set_pc(pc_proxy);
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}
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}
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}
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template <Flags f> void perform(Multiply fields) {
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constexpr MultiplyFlags flags(f);
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// R15 rules:
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//
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// * Rs: no PSR, 8 bytes ahead;
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// * Rn: with PSR, 8 bytes ahead;
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// * Rm: with PSR, 12 bytes ahead.
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const uint32_t multiplicand = fields.multiplicand() == 15 ? registers_.pc(8) : registers_.active[fields.multiplicand()];
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const uint32_t multiplier = fields.multiplier() == 15 ? registers_.pc_status(8) : registers_.active[fields.multiplier()];
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const uint32_t accumulator =
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flags.operation() == MultiplyFlags::Operation::MUL ? 0 :
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(fields.multiplicand() == 15 ? registers_.pc_status(12) : registers_.active[fields.accumulator()]);
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const uint32_t result = multiplicand * multiplier + accumulator;
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if constexpr (flags.set_condition_codes()) {
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registers_.set_nz(result);
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// V is unaffected; C is undefined.
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}
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if(fields.destination() != 15) {
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registers_.active[fields.destination()] = result;
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}
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}
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template <Flags f> void perform(Branch branch) {
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constexpr BranchFlags flags(f);
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if constexpr (flags.operation() == BranchFlags::Operation::BL) {
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registers_.active[14] = registers_.pc(4);
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}
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registers_.set_pc(registers_.pc(8) + branch.offset());
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}
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template <Flags f> void perform(SingleDataTransfer transfer) {
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constexpr SingleDataTransferFlags flags(f);
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// Calculate offset.
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uint32_t offset;
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if constexpr (flags.offset_is_immediate()) {
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offset = transfer.immediate();
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} else {
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// The 8 shift control bits are described in 6.2.3, but
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// the register specified shift amounts are not available
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// in this instruction class.
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uint32_t carry = registers_.c();
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offset = decode_shift<false, false>(transfer, carry, 8);
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}
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// Obtain base address.
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uint32_t address =
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transfer.base() == 15 ?
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registers_.pc(8) :
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registers_.active[transfer.base()];
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// Determine what the address will be after offsetting.
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uint32_t offsetted_address = address;
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if constexpr (flags.add_offset()) {
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offsetted_address += offset;
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} else {
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offsetted_address -= offset;
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}
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// If preindexing, apply now.
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if constexpr (flags.pre_index()) {
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address = offsetted_address;
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}
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// Check for an address exception.
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if(address >= (1 << 26)) {
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registers_.exception<Registers::Exception::Address>();
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return;
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}
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constexpr bool trans = !flags.pre_index() && flags.write_back_address();
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if constexpr (flags.operation() == SingleDataTransferFlags::Operation::STR) {
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const uint32_t source =
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transfer.source() == 15 ?
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registers_.pc_status(12) :
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registers_.active[transfer.source()];
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bool did_write;
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if constexpr (flags.transfer_byte()) {
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did_write = bus_.template write<uint8_t>(address, uint8_t(source), registers_.mode(), trans);
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} else {
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// "The data presented to the data bus are not affected if the address is not word aligned".
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did_write = bus_.template write<uint32_t>(address, source, registers_.mode(), trans);
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}
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if(!did_write) {
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registers_.exception<Registers::Exception::DataAbort>();
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return;
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}
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} else {
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bool did_read;
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uint32_t value;
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if constexpr (flags.transfer_byte()) {
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uint8_t target;
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did_read = bus_.template read<uint8_t>(address, target, registers_.mode(), trans);
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value = target;
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} else {
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did_read = bus_.template read<uint32_t>(address, value, registers_.mode(), trans);
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// "An address offset from a word boundary will cause the data to be rotated into the
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// register so that the addressed byte occuplies bits 0 to 7."
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switch(address & 3) {
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case 0: break;
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case 1: value = (value >> 8) | (value << 24); break;
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case 2: value = (value >> 16) | (value << 16); break;
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case 3: value = (value >> 24) | (value << 8); break;
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}
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}
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if(!did_read) {
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registers_.exception<Registers::Exception::DataAbort>();
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return;
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}
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if(transfer.destination() == 15) {
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registers_.set_pc(value);
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} else {
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registers_.active[transfer.destination()] = value;
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}
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}
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// If either postindexing or else with writeback, update base.
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if constexpr (!flags.pre_index() || flags.write_back_address()) {
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if(transfer.base() == 15) {
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registers_.set_pc(offsetted_address);
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} else {
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registers_.active[transfer.base()] = offsetted_address;
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}
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}
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}
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template <Flags f> void perform(BlockDataTransfer transfer) {
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constexpr BlockDataTransferFlags flags(f);
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uint32_t address = transfer.base() == 15 ?
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registers_.pc_status(8) :
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registers_.active[transfer.base()];
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constexpr uint32_t step = flags.add_offset() ? 4 : -4;
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// TODO: forcing transfer of the user bank.
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// TODO: inclusion of the base in the register list.
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// TODO: data aborts.
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const auto visit = [&](uint32_t &value) {
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if constexpr (flags.pre_index()) {
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address += step;
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}
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if constexpr (flags.operation() == BlockDataTransferFlags::Operation::STM) {
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bus_.template read<uint32_t>(address, value, registers_.mode(), false);
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} else {
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bus_.template write<uint32_t>(address, value, registers_.mode(), false);
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}
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if constexpr (!flags.pre_index()) {
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address += step;
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}
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};
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const uint16_t list = transfer.register_list();
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for(int c = 0; c < 15; c++) {
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if(list & (1 << c)) {
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visit(registers_.active[c]);
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}
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}
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if(list & (1 << 15)) {
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uint32_t value;
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if constexpr (flags.operation() == BlockDataTransferFlags::Operation::STM) {
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value = registers_.pc_status(12);
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visit(value);
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} else {
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visit(value);
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registers_.set_pc(value);
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if constexpr (flags.load_psr()) {
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// TODO: [T]he PSR will be overwritten by the corresponding bits of the loaded value.
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// In user mode, however, the I, F, M0 and M1 bits are protected from change
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// ... The mode at the start of the instruction determines whether these bits
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// are protected.
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}
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}
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}
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if constexpr (flags.write_back_address()) {
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if(transfer.base() != 15) {
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registers_.active[transfer.base()] = address;
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}
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}
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}
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void software_interrupt() {
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registers_.exception<Registers::Exception::SoftwareInterrupt>();
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}
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void unknown() {
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registers_.exception<Registers::Exception::UndefinedInstruction>();
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}
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// Act as if no coprocessors present.
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template <Flags> void perform(CoprocessorRegisterTransfer) {
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registers_.exception<Registers::Exception::UndefinedInstruction>();
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}
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template <Flags> void perform(CoprocessorDataOperation) {
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registers_.exception<Registers::Exception::UndefinedInstruction>();
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}
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template <Flags> void perform(CoprocessorDataTransfer) {
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registers_.exception<Registers::Exception::UndefinedInstruction>();
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}
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MemoryT bus_;
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private:
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Registers registers_;
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};
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}
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@interface ARMDecoderTests : XCTestCase
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@end
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@implementation ARMDecoderTests
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- (void)testXYX {
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Scheduler<Memory> scheduler;
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for(int c = 0; c < 65536; c++) {
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InstructionSet::ARM::dispatch(c << 16, scheduler);
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}
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InstructionSet::ARM::dispatch(0xEAE06900, scheduler);
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}
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@end
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