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377 lines
11 KiB
C++
377 lines
11 KiB
C++
//
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// ncr5380.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/08/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#include "ncr5380.hpp"
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#ifndef NDEBUG
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#define NDEBUG
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#endif
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#define LOG_PREFIX "[5380] "
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#include "../../Outputs/Log.hpp"
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// TODO:
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//
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// end_of_dma_ should be set if: /EOP && /DACK && (/RD || /WR); for at least 100ns.
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using namespace NCR::NCR5380;
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using SCSI::Line;
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NCR5380::NCR5380(SCSI::Bus &bus, int clock_rate) :
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bus_(bus),
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clock_rate_(clock_rate) {
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device_id_ = bus_.add_device();
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bus_.add_observer(this);
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// TODO: use clock rate and expected phase. This implementation currently
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// provides only CPU-driven polling behaviour.
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(void)clock_rate_;
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(void)expected_phase_;
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}
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void NCR5380::write(int address, uint8_t value, bool) {
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switch(address & 7) {
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case 0:
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LOG("[0] Set current SCSI bus state to " << PADHEX(2) << int(value));
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data_bus_ = value;
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if(dma_request_ && dma_operation_ == DMAOperation::Send) {
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dma_acknowledge(value);
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}
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break;
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case 1: {
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LOG("[1] Initiator command register set: " << PADHEX(2) << int(value));
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initiator_command_ = value;
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bus_output_ &= ~(Line::Reset | Line::Acknowledge | Line::Busy | Line::SelectTarget | Line::Attention);
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if(value & 0x80) bus_output_ |= Line::Reset;
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if(value & 0x08) bus_output_ |= Line::Busy;
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if(value & 0x04) bus_output_ |= Line::SelectTarget;
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/* bit 5 = differential enable if this were a 5381 */
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test_mode_ = value & 0x40;
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assert_data_bus_ = value & 0x01;
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update_control_output();
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} break;
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case 2:
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LOG("[2] Set mode: " << PADHEX(2) << int(value));
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mode_ = value;
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// bit 7: 1 = use block mode DMA mode (if DMA mode is also enabled)
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// bit 6: 1 = be a SCSI target; 0 = be an initiator
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// bit 5: 1 = check parity
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// bit 4: 1 = generate an interrupt if parity checking is enabled and an error is found
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// bit 3: 1 = generate an interrupt when an EOP is received from the DMA controller
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// bit 2: 1 = generate an interrupt and reset low 6 bits of register 1 if an unexpected loss of Line::Busy occurs
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// bit 1: 1 = use DMA mode
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// bit 0: 1 = begin arbitration mode (device ID should be in register 0)
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arbitration_in_progress_ = false;
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phase_mismatch_ = false;
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switch(mode_ & 0x3) {
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case 0x0:
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bus_output_ &= ~SCSI::Line::Busy;
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dma_request_ = false;
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set_execution_state(ExecutionState::None);
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break;
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case 0x1:
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arbitration_in_progress_ = true;
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set_execution_state(ExecutionState::WaitingForBusy);
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lost_arbitration_ = false;
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break;
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default:
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assert_data_bus_ = false;
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set_execution_state(ExecutionState::PerformingDMA);
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bus_.update_observers();
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break;
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}
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// "[The End of DMA Transfer] bit is reset when the DMA MODE bit
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// is reset (0) in the Mode Register".
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end_of_dma_ &= bool(value & 0x2);
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update_control_output();
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break;
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case 3: {
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LOG("[3] Set target command: " << PADHEX(2) << int(value));
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target_command_ = value;
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update_control_output();
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} break;
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case 4:
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LOG("[4] Set select enabled: " << PADHEX(2) << int(value));
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break;
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case 5:
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LOG("[5] Start DMA send: " << PADHEX(2) << int(value));
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dma_operation_ = DMAOperation::Send;
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break;
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case 6:
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LOG("[6] Start DMA target receive: " << PADHEX(2) << int(value));
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dma_operation_ = DMAOperation::TargetReceive;
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break;
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case 7:
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LOG("[7] Start DMA initiator receive: " << PADHEX(2) << int(value));
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dma_operation_ = DMAOperation::InitiatorReceive;
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break;
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}
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// Data is output only if the data bus is asserted.
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if(assert_data_bus_) {
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bus_output_ = (bus_output_ & ~SCSI::Line::Data) | data_bus_;
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} else {
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bus_output_ &= ~SCSI::Line::Data;
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}
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// In test mode, still nothing is output. Otherwise throw out
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// the current value of bus_output_.
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if(test_mode_) {
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bus_.set_device_output(device_id_, SCSI::DefaultBusState);
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} else {
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bus_.set_device_output(device_id_, bus_output_);
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}
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}
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uint8_t NCR5380::read(int address, bool) {
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switch(address & 7) {
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case 0:
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LOG("[0] Get current SCSI bus state: " << PADHEX(2) << (bus_.get_state() & 0xff));
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if(dma_request_ && dma_operation_ == DMAOperation::InitiatorReceive) {
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return dma_acknowledge();
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}
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return uint8_t(bus_.get_state());
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case 1:
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LOG("[1] Initiator command register get: " << (arbitration_in_progress_ ? 'p' : '-') << (lost_arbitration_ ? 'l' : '-'));
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return
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// Bits repeated as they were set.
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(initiator_command_ & ~0x60) |
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// Arbitration in progress.
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(arbitration_in_progress_ ? 0x40 : 0x00) |
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// Lost arbitration.
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(lost_arbitration_ ? 0x20 : 0x00);
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case 2:
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LOG("[2] Get mode");
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return mode_;
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case 3:
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LOG("[3] Get target command");
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return target_command_;
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case 4: {
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const auto bus_state = bus_.get_state();
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const uint8_t result =
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((bus_state & Line::Reset) ? 0x80 : 0x00) |
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((bus_state & Line::Busy) ? 0x40 : 0x00) |
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((bus_state & Line::Request) ? 0x20 : 0x00) |
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((bus_state & Line::Message) ? 0x10 : 0x00) |
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((bus_state & Line::Control) ? 0x08 : 0x00) |
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((bus_state & Line::Input) ? 0x04 : 0x00) |
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((bus_state & Line::SelectTarget) ? 0x02 : 0x00) |
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((bus_state & Line::Parity) ? 0x01 : 0x00);
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LOG("[4] Get current bus state: " << PADHEX(2) << int(result));
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return result;
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}
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case 5: {
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const auto bus_state = bus_.get_state();
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const uint8_t result =
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(end_of_dma_ ? 0x80 : 0x00) |
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((dma_request_ && state_ == ExecutionState::PerformingDMA) ? 0x40 : 0x00) |
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/* b5 = parity error */
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(irq_ ? 0x10 : 0x00) |
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(phase_matches() ? 0x08 : 0x00) |
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/* b2 = busy error */
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((bus_state & Line::Attention) ? 0x02 : 0x00) |
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((bus_state & Line::Acknowledge) ? 0x01 : 0x00);
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LOG("[5] Get bus and status: " << PADHEX(2) << int(result));
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return result;
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}
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case 6:
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LOG("[6] Get input data");
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return 0xff;
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case 7:
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LOG("[7] Reset parity/interrupt");
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irq_ = false;
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return 0xff;
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}
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return 0;
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}
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SCSI::BusState NCR5380::target_output() const {
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SCSI::BusState output = SCSI::DefaultBusState;
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if(target_command_ & 0x08) output |= Line::Request;
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if(target_command_ & 0x04) output |= Line::Message;
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if(target_command_ & 0x02) output |= Line::Control;
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if(target_command_ & 0x01) output |= Line::Input;
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return output;
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}
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void NCR5380::update_control_output() {
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bus_output_ &= ~(Line::Request | Line::Message | Line::Control | Line::Input | Line::Acknowledge | Line::Attention);
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if(mode_ & 0x40) {
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// This is a target; C/D, I/O, /MSG and /REQ are signalled on the bus.
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bus_output_ |= target_output();
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} else {
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// This is an initiator; /ATN and /ACK are signalled on the bus.
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if(
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(initiator_command_ & 0x10) ||
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(state_ == ExecutionState::PerformingDMA && dma_acknowledge_)
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) bus_output_ |= Line::Acknowledge;
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if(initiator_command_ & 0x02) bus_output_ |= Line::Attention;
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}
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}
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void NCR5380::scsi_bus_did_change(SCSI::Bus *, SCSI::BusState new_state, double time_since_change) {
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/*
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When connected as an Initiator with DMA Mode True,
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if the phase lines I//O, C//D, and /MSG do not match the
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phase bits in the Target Command Register, a phase mismatch
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interrupt is generated when /REQ goes active.
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*/
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if((mode_ & 0x42) == 0x02 && new_state & SCSI::Line::Request && !phase_matches()) {
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irq_ = true;
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phase_mismatch_ = true;
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}
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switch(state_) {
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default: break;
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/*
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Official documentation:
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Arbitration is accomplished using a bus-free filter to continuously monitor BSY.
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If BSY remains inactive for at least 400 nsec then the SCSI bus is considered free
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and arbitration may begin. Arbitration will begin if the bus is free, SEL is inactive
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and the ARBITRATION bit (port 2, bit 0) is active. Once arbitration has begun
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(BSY asserted), an arbitration delay of 2.2 /Lsec must elapse before the data bus
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can be examined to deter- mine if arbitration has been won. This delay must be
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implemented in the controlling software driver.
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Personal notes:
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I'm discounting that "arbitratation is accomplished" opening, and assuming that what needs
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to happen is:
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(i) wait for BSY to be inactive;
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(ii) count 400 nsec;
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(iii) check that BSY and SEL are inactive.
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*/
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case ExecutionState::WaitingForBusy:
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if(!(new_state & SCSI::Line::Busy) || time_since_change < SCSI::DeskewDelay) return;
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state_ = ExecutionState::WatchingBusy;
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[[fallthrough]];
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case ExecutionState::WatchingBusy:
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if(!(new_state & SCSI::Line::Busy)) {
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lost_arbitration_ = true;
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set_execution_state(ExecutionState::None);
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}
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// Check for having hit 400ns (more or less) since BSY was inactive.
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if(time_since_change >= SCSI::BusSettleDelay) {
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// arbitration_in_progress_ = false;
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if(new_state & SCSI::Line::SelectTarget) {
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lost_arbitration_ = true;
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set_execution_state(ExecutionState::None);
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} else {
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bus_output_ &= ~SCSI::Line::Busy;
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set_execution_state(ExecutionState::None);
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}
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}
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/* TODO: there's a bug here, given that the dropping of Busy isn't communicated onward. */
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break;
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case ExecutionState::PerformingDMA:
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if(time_since_change < SCSI::DeskewDelay) return;
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// Signal a DMA request if the request line is active, i.e. meaningful data is
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// on the bus, and this device hasn't yet acknowledged it.
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switch(new_state & (SCSI::Line::Request | SCSI::Line::Acknowledge)) {
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case 0:
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dma_request_ = false;
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break;
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case SCSI::Line::Request:
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// Don't issue a new DMA request if a phase mismatch has
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// been detected and this is an intiator receiving.
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// This is a bit of reading between the lines.
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// (i.e. guesswork, partly)
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dma_request_ =
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!phase_mismatch_ ||
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(dma_operation_ != DMAOperation::InitiatorReceive);
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break;
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case SCSI::Line::Request | SCSI::Line::Acknowledge:
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dma_request_ = false;
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break;
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case SCSI::Line::Acknowledge:
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dma_acknowledge_ = false;
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dma_request_ = false;
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update_control_output();
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bus_.set_device_output(device_id_, bus_output_);
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break;
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}
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break;
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}
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}
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void NCR5380::set_execution_state(ExecutionState state) {
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state_ = state;
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if(state != ExecutionState::PerformingDMA) dma_operation_ = DMAOperation::Ready;
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}
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size_t NCR5380::scsi_id() {
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return device_id_;
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}
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bool NCR5380::dma_request() {
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return dma_request_;
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}
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uint8_t NCR5380::dma_acknowledge() {
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const uint8_t bus_state = uint8_t(bus_.get_state());
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dma_acknowledge_ = true;
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dma_request_ = false;
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update_control_output();
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bus_.set_device_output(device_id_, bus_output_);
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return bus_state;
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}
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void NCR5380::dma_acknowledge(uint8_t value) {
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data_bus_ = value;
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dma_acknowledge_ = true;
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dma_request_ = false;
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update_control_output();
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bus_.set_device_output(device_id_, bus_output_);
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}
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bool NCR5380::phase_matches() const {
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const auto bus_state = bus_.get_state();
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return
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(target_output() & (Line::Message | Line::Control | Line::Input)) ==
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(bus_state & (Line::Message | Line::Control | Line::Input));
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}
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