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CLK
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OSBindings
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Clock SignalTests
History
Thomas Harte
064f1dfdbc
Removes usages of deprecated initialiser.
2017-10-05 18:10:47 -04:00
..
AllSuiteA
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Atari ROMs
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BCDTest
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Bridges
Corrects 6522 bridge per has-a-not-is-a template switch.
2017-09-04 21:56:21 -04:00
FUSE
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Klaus Dormann
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Wolfgang Lorenz 6502 test suite
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Zexall
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6502InterruptTests.swift
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6502TimingTests.swift
Corrected timestamp return, and its testing by the 6502 timing tests.
2017-07-27 21:19:16 -04:00
6522Tests.swift
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6532Tests.swift
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AllSuiteATests.swift
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ArrayBuilderTests.mm
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AtariStaticAnalyserTests.mm
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BCDTest.swift
Completed fixture of the 6502 BCD test.
2017-07-25 22:55:45 -04:00
C1540Tests.swift
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CRCTests.mm
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DPLLTests.swift
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FUSETests.swift
Removes usages of deprecated initialiser.
2017-10-05 18:10:47 -04:00
Info.plist
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KlausDormannTests.swift
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PCMPatchedTrackTests.mm
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
PCMSegmentEventSourceTests.mm
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PCMTrackTests.mm
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TIATests.mm
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TimeTests.mm
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WolfgangLorenzTests.swift
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Z80InterruptTests.swift
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Z80MachineCycleTests.swift
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
Z80MemptrTests.swift
Added test for 16-bit arithmetic, and fixed implementation.
2017-07-26 19:04:52 -04:00
ZexallTests.swift
…