mirror of https://github.com/TomHarte/CLK.git
237 lines
8.2 KiB
C++
237 lines
8.2 KiB
C++
//
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// Instruction.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 15/01/21.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include <cstdint>
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#include <iomanip>
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#include <string>
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#include <sstream>
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#include "../AccessType.hpp"
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namespace InstructionSet::M50740 {
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enum class AddressingMode {
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Implied, Accumulator, Immediate,
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Absolute, AbsoluteX, AbsoluteY,
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ZeroPage, ZeroPageX, ZeroPageY,
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XIndirect, IndirectY,
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Relative,
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AbsoluteIndirect, ZeroPageIndirect,
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SpecialPage,
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ImmediateZeroPage,
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AccumulatorRelative, ZeroPageRelative
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};
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static constexpr auto MaxAddressingMode = int(AddressingMode::ZeroPageRelative);
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static constexpr auto MinAddressingMode = int(AddressingMode::Implied);
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constexpr int size(AddressingMode mode) {
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// This is coupled to the AddressingMode list above; be careful!
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constexpr int sizes[] = {
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0, 0, 1,
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2, 2, 2,
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1, 1, 1,
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1, 1,
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1,
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2, 1,
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1,
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2,
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1, 2
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};
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static_assert(sizeof(sizes)/sizeof(*sizes) == int(MaxAddressingMode) + 1);
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return sizes[int(mode)];
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}
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enum class Operation: uint8_t {
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Invalid,
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// Operations that don't access memory.
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BBC0, BBC1, BBC2, BBC3, BBC4, BBC5, BBC6, BBC7,
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BBS0, BBS1, BBS2, BBS3, BBS4, BBS5, BBS6, BBS7,
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BCC, BCS,
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BEQ, BMI, BNE, BPL,
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BVC, BVS, BRA, BRK,
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JMP, JSR,
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RTI, RTS,
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CLC, CLD, CLI, CLT, CLV,
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SEC, SED, SEI, SET,
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INX, INY, DEX, DEY,
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FST, SLW,
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NOP,
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PHA, PHP, PLA, PLP,
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STP,
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TAX, TAY, TSX, TXA,
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TXS, TYA,
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// Read operations.
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ADC, SBC,
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AND, ORA, EOR, BIT,
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CMP, CPX, CPY,
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LDA, LDX, LDY,
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TST,
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// Read-modify-write operations.
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ASL, LSR,
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CLB0, CLB1, CLB2, CLB3, CLB4, CLB5, CLB6, CLB7,
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SEB0, SEB1, SEB2, SEB3, SEB4, SEB5, SEB6, SEB7,
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COM,
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DEC, INC,
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ROL, ROR, RRF,
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// Write operations.
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LDM,
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STA, STX, STY,
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};
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static constexpr auto MaxOperation = int(Operation::STY);
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static constexpr auto MinOperation = int(Operation::BBC0);
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constexpr AccessType access_type(Operation operation) {
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if(operation < Operation::ADC) return AccessType::None;
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if(operation < Operation::ASL) return AccessType::Read;
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if(operation < Operation::LDM) return AccessType::ReadModifyWrite;
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return AccessType::Write;
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}
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constexpr bool uses_index_mode(Operation operation) {
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return
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operation == Operation::ADC || operation == Operation::AND ||
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operation == Operation::CMP || operation == Operation::EOR ||
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operation == Operation::LDA || operation == Operation::ORA ||
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operation == Operation::SBC;
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}
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/*!
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@returns The name of @c operation.
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*/
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inline constexpr const char *operation_name(Operation operation) {
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#define MAP(x) case Operation::x: return #x;
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switch(operation) {
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default: break;
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MAP(BBC0); MAP(BBC1); MAP(BBC2); MAP(BBC3); MAP(BBC4); MAP(BBC5); MAP(BBC6); MAP(BBC7);
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MAP(BBS0); MAP(BBS1); MAP(BBS2); MAP(BBS3); MAP(BBS4); MAP(BBS5); MAP(BBS6); MAP(BBS7);
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MAP(BCC); MAP(BCS); MAP(BEQ); MAP(BMI); MAP(BNE); MAP(BPL); MAP(BVC); MAP(BVS);
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MAP(BRA); MAP(BRK); MAP(JMP); MAP(JSR); MAP(RTI); MAP(RTS); MAP(CLC); MAP(CLD);
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MAP(CLI); MAP(CLT); MAP(CLV); MAP(SEC); MAP(SED); MAP(SEI); MAP(SET); MAP(INX);
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MAP(INY); MAP(DEX); MAP(DEY); MAP(FST); MAP(SLW); MAP(NOP); MAP(PHA); MAP(PHP);
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MAP(PLA); MAP(PLP); MAP(STP); MAP(TAX); MAP(TAY); MAP(TSX); MAP(TXA); MAP(TXS);
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MAP(TYA); MAP(ADC); MAP(SBC); MAP(AND); MAP(ORA); MAP(EOR); MAP(BIT); MAP(CMP);
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MAP(CPX); MAP(CPY); MAP(LDA); MAP(LDX); MAP(LDY); MAP(TST); MAP(ASL); MAP(LSR);
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MAP(CLB0); MAP(CLB1); MAP(CLB2); MAP(CLB3); MAP(CLB4); MAP(CLB5); MAP(CLB6); MAP(CLB7);
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MAP(SEB0); MAP(SEB1); MAP(SEB2); MAP(SEB3); MAP(SEB4); MAP(SEB5); MAP(SEB6); MAP(SEB7);
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MAP(COM); MAP(DEC); MAP(INC); MAP(ROL); MAP(ROR); MAP(RRF); MAP(LDM); MAP(STA);
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MAP(STX); MAP(STY);
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}
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#undef MAP
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return "???";
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}
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inline std::ostream &operator <<(std::ostream &stream, Operation operation) {
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stream << operation_name(operation);
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return stream;
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}
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/*!
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@returns The name of @c addressing_mode.
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*/
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inline constexpr const char *addressing_mode_name(AddressingMode addressing_mode) {
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switch(addressing_mode) {
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default: break;
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case AddressingMode::Implied: return "";
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case AddressingMode::Accumulator: return "A";
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case AddressingMode::Immediate: return "#";
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case AddressingMode::Absolute: return "abs";
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case AddressingMode::AbsoluteX: return "abs, x";
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case AddressingMode::AbsoluteY: return "abs, y";
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case AddressingMode::ZeroPage: return "zp";
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case AddressingMode::ZeroPageX: return "zp, x";
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case AddressingMode::ZeroPageY: return "zp, y";
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case AddressingMode::XIndirect: return "((zp, x))";
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case AddressingMode::IndirectY: return "((zp), y)";
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case AddressingMode::Relative: return "rel";
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case AddressingMode::AbsoluteIndirect: return "(abs)";
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case AddressingMode::ZeroPageIndirect: return "(zp)";
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case AddressingMode::SpecialPage: return "\\sp";
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case AddressingMode::ImmediateZeroPage: return "#, zp";
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case AddressingMode::AccumulatorRelative: return "A, rel";
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case AddressingMode::ZeroPageRelative: return "zp, rel";
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}
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return "???";
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}
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inline std::ostream &operator <<(std::ostream &stream, AddressingMode mode) {
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stream << addressing_mode_name(mode);
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return stream;
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}
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/*!
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@returns The way that the address for an operation with @c addressing_mode and encoded starting from @c operation
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would appear in an assembler. E.g. '$5a' for that zero page address, or '$5a, x' for zero-page indexed from $5a. This function
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may access up to three bytes from @c operation onwards.
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*/
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inline std::string address(AddressingMode addressing_mode, const uint8_t *operation, uint16_t program_counter) {
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std::stringstream output;
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output << std::hex;
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#define NUM(x) std::setfill('0') << std::setw(2) << int(x)
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#define NUM4(x) std::setfill('0') << std::setw(4) << int(x)
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switch(addressing_mode) {
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default: return "???";
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case AddressingMode::Implied: return "";
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case AddressingMode::Accumulator: return "A ";
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case AddressingMode::Immediate: output << "#$" << NUM(operation[1]); break;
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case AddressingMode::Absolute: output << "$" << NUM(operation[2]) << NUM(operation[1]); break;
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case AddressingMode::AbsoluteX: output << "$" << NUM(operation[2]) << NUM(operation[1]) << ", x"; break;
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case AddressingMode::AbsoluteY: output << "$" << NUM(operation[2]) << NUM(operation[1]) << ", y"; break;
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case AddressingMode::ZeroPage: output << "$" << NUM(operation[1]); break;
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case AddressingMode::ZeroPageX: output << "$" << NUM(operation[1]) << ", x"; break;
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case AddressingMode::ZeroPageY: output << "$" << NUM(operation[1]) << ", y"; break;
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case AddressingMode::XIndirect: output << "(($" << NUM(operation[1]) << ", x))"; break;
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case AddressingMode::IndirectY: output << "(($" << NUM(operation[1]) << "), y)"; break;
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case AddressingMode::Relative: output << "#$" << NUM4(2 + program_counter + int8_t(operation[1])); break;
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case AddressingMode::AbsoluteIndirect: output << "($" << NUM(operation[2]) << NUM(operation[1]) << ") "; break;
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case AddressingMode::ZeroPageIndirect: output << "($" << NUM(operation[1]) << ")"; break;
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case AddressingMode::SpecialPage: output << "$1f" << NUM(operation[1]); break;
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case AddressingMode::ImmediateZeroPage: output << "#$" << NUM(operation[1]) << ", $" << NUM(operation[2]); break;
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case AddressingMode::AccumulatorRelative: output << "A, $" << NUM4(2 + program_counter + int8_t(operation[1])); break;
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case AddressingMode::ZeroPageRelative:
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output << "$" << NUM(operation[1]) << ", $" << NUM4(3 + program_counter + int8_t(operation[2]));
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break;
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}
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#undef NUM4
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#undef NUM
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return output.str();
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}
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/*!
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Models a complete M50740-style instruction, including its operation, addressing mode and opcode.
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*/
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struct Instruction {
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Operation operation = Operation::Invalid;
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AddressingMode addressing_mode = AddressingMode::Implied;
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uint8_t opcode = 0;
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Instruction(Operation operation, AddressingMode addressing_mode, uint8_t opcode) : operation(operation), addressing_mode(addressing_mode), opcode(opcode) {}
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Instruction(uint8_t opcode) : opcode(opcode) {}
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Instruction() = default;
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};
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/*!
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Outputs a description of @c instruction to @c stream.
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*/
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inline std::ostream &operator <<(std::ostream &stream, const Instruction &instruction) {
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stream << operation_name(instruction.operation) << " " << addressing_mode_name(instruction.addressing_mode);
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return stream;
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}
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}
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