mirror of https://github.com/TomHarte/CLK.git
499 lines
14 KiB
C++
499 lines
14 KiB
C++
//
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// Instruction.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/04/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "Model.hpp"
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#include <cassert>
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#include <cstdint>
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#include <string>
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namespace InstructionSet::M68k {
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enum class Operation: uint8_t {
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Undefined,
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//
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// 68000 operations.
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//
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NOP,
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ABCD, SBCD, NBCD,
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ADDb, ADDw, ADDl,
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ADDAw, ADDAl,
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ADDXb, ADDXw, ADDXl,
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SUBb, SUBw, SUBl,
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SUBAw, SUBAl,
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SUBXb, SUBXw, SUBXl,
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MOVEb, MOVEw, MOVEl,
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MOVEAw, MOVEAl,
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LEA, PEA,
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MOVEtoSR, MOVEfromSR,
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MOVEtoCCR,
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MOVEtoUSP, MOVEfromUSP,
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ORItoSR, ORItoCCR,
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ANDItoSR, ANDItoCCR,
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EORItoSR, EORItoCCR,
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BTST, BCLR,
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BCHG, BSET,
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CMPb, CMPw, CMPl,
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CMPAw, CMPAl,
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TSTb, TSTw, TSTl,
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JMP,
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JSR, RTS,
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DBcc,
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Scc,
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Bccb, Bccw,
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BSRb, BSRw,
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CLRb, CLRw, CLRl,
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NEGXb, NEGXw, NEGXl,
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NEGb, NEGw, NEGl,
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ASLb, ASLw, ASLl, ASLm,
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ASRb, ASRw, ASRl, ASRm,
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LSLb, LSLw, LSLl, LSLm,
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LSRb, LSRw, LSRl, LSRm,
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ROLb, ROLw, ROLl, ROLm,
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RORb, RORw, RORl, RORm,
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ROXLb, ROXLw, ROXLl, ROXLm,
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ROXRb, ROXRw, ROXRl, ROXRm,
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MOVEMtoRl, MOVEMtoRw,
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MOVEMtoMl, MOVEMtoMw,
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MOVEPl, MOVEPw,
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ANDb, ANDw, ANDl,
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EORb, EORw, EORl,
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NOTb, NOTw, NOTl,
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ORb, ORw, ORl,
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MULUw, MULSw,
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DIVUw, DIVSw,
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RTE, RTR,
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TRAP, TRAPV,
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CHKw,
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EXG, SWAP,
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TAS,
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EXTbtow, EXTwtol,
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LINKw, UNLINK,
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STOP, RESET,
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//
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// 68010 additions.
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//
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MOVEfromCCR,
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MOVEtoC, MOVEfromC,
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MOVESb, MOVESw, MOVESl,
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BKPT, RTD,
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//
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// 68020 additions.
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//
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TRAPcc,
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CALLM, RTM,
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BFCHG, BFCLR,
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BFEXTS, BFEXTU,
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BFFFO, BFINS,
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BFSET, BFTST,
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PACK, UNPK,
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CASb, CASw, CASl,
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CAS2w, CAS2l,
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// CHK2 and CMP2 are distinguished by their extension word;
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// since this code deals in Preinstructions, i.e. as much
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// as can be derived from the instruction word alone, in addition
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// to the full things, the following enums result.
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CHKorCMP2b, CHKorCMP2w, CHKorCMP2l,
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// DIVS.l, DIVSL.l, DIVU.l and DIVUL.l are all distinguishable
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// only by the extension word.
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DIVSorDIVUl,
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// MULS.l, MULSL.l, MULU.l and MULUL.l are all distinguishable
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// only by the extension word.
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MULSorMULUl,
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Bccl, BSRl,
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LINKl, CHKl,
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EXTbtol,
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// Coprocessor instructions are omitted for now, until I can
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// determine by what mechanism the number of
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// "OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS" is determined.
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// cpBcc, cpDBcc, cpGEN,
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// cpScc, cpTRAPcc, cpRESTORE,
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// cpSAVE,
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//
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// 68030 additions.
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//
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PFLUSH, PFLUSHA,
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PLOADR, PLOADW,
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PMOVE, PMOVEFD,
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PTESTR, PTESTW,
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//
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// 68040 additions.
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//
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// TODO: the big addition of the 68040 is incorporation of the FPU; should I make decoding of those instructions
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// dependent upon a 68040 being selected, or should I offer a separate decoder in order to support systems with
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// a coprocessor?
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//
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// Introspection.
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//
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Max68000 = RESET,
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Max68010 = RTD,
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Max68020 = EXTbtol,
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Max68030 = PTESTW,
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Max68040 = PTESTW,
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};
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// Provide per-model max entries in Operation.
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template <Model> struct OperationMax {};
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template <> struct OperationMax<Model::M68000> {
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static constexpr Operation value = Operation::Max68000;
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};
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template <> struct OperationMax<Model::M68010> {
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static constexpr Operation value = Operation::Max68010;
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};
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template <> struct OperationMax<Model::M68020> {
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static constexpr Operation value = Operation::Max68020;
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};
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template <> struct OperationMax<Model::M68030> {
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static constexpr Operation value = Operation::Max68030;
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};
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template <> struct OperationMax<Model::M68040> {
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static constexpr Operation value = Operation::Max68040;
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};
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const char *to_string(Operation op);
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template <Model model>
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constexpr bool requires_supervisor(Operation op) {
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switch(op) {
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case Operation::MOVEfromSR:
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if constexpr (model == Model::M68000) {
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return false;
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}
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[[fallthrough]];
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case Operation::ORItoSR: case Operation::ANDItoSR:
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case Operation::EORItoSR: case Operation::RTE:
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case Operation::RESET: case Operation::STOP:
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case Operation::MOVEtoUSP: case Operation::MOVEfromUSP:
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case Operation::MOVEtoC: case Operation::MOVEfromC:
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case Operation::MOVEtoSR:
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return true;
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default:
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return false;
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}
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}
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enum class DataSize {
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Byte = 0,
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Word = 1,
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LongWord = 2,
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};
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/// Classifies operations by the size of their memory accesses, if any.
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///
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/// For any operations that don't fit the neat model of reading one or two operands,
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/// then writing zero or one, the size determines the data size of the operands only,
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/// not any other accesses.
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template <Operation t_operation = Operation::Undefined>
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constexpr DataSize operand_size(Operation operation = Operation::Undefined);
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template <Operation t_op = Operation::Undefined>
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constexpr uint32_t quick(uint16_t instruction, Operation r_op = Operation::Undefined) {
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switch((t_op != Operation::Undefined) ? t_op : r_op) {
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case Operation::Bccb:
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case Operation::BSRb:
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case Operation::MOVEl: return uint32_t(int8_t(instruction));
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case Operation::TRAP: return uint32_t(instruction & 15);
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case Operation::BKPT: return uint32_t(instruction & 7);
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default: {
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uint32_t value = (instruction >> 9) & 7;
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value |= (value - 1)&8;
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return value;
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}
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}
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}
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static constexpr uint8_t FetchOp1 = (1 << 0);
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static constexpr uint8_t FetchOp2 = (1 << 1);
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static constexpr uint8_t StoreOp1 = (1 << 2);
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static constexpr uint8_t StoreOp2 = (1 << 3);
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/*!
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Provides a bitfield with a value in the range 0–15 indicating which of the provided operation's
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operands are accessed via standard fetch and store cycles; the bitfield is composted of
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[Fetch/Store]Op[1/2] as defined above.
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Unusual bus sequences, such as TAS or MOVEM, are not described here.
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*/
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template <Model model, Operation t_operation = Operation::Undefined>
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constexpr uint8_t operand_flags(Operation r_operation = Operation::Undefined);
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/// Lists the various condition codes used by the 680x0.
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enum class Condition {
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True = 0x00, False = 0x01,
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High = 0x02, LowOrSame = 0x03,
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CarryClear = 0x04, CarrySet = 0x05,
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NotEqual = 0x06, Equal = 0x07,
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OverflowClear = 0x08, OverflowSet = 0x09,
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Positive = 0x0a, Negative = 0x0b,
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GreaterThanOrEqual = 0x0c, LessThan = 0x0d,
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GreaterThan = 0x0e, LessThanOrEqual = 0x0f,
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};
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/// Indicates the addressing mode applicable to an operand.
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///
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/// Implementation notes:
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///
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/// Those entries starting 0b00 or 0b01 are mapped as per the 68000's native encoding;
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/// those starting 0b00 are those which are indicated directly by a mode field and those starting
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/// 0b01 are those which are indicated by a register field given a mode of 0b111. The only minor
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/// exception is AddressRegisterDirect, which exists on a 68000 but isn't specifiable by a
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/// mode and register, it's contextual based on the instruction.
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///
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/// Those modes starting in 0b10 are the various extended addressing modes introduced as
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/// of the 68020, which can be detected only after interpreting an extension word. At the
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/// Preinstruction stage:
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///
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/// * AddressRegisterIndirectWithIndexBaseDisplacement, MemoryIndirectPostindexed
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/// and MemoryIndirectPreindexed will have been partially decoded as
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/// AddressRegisterIndirectWithIndex8bitDisplacement; and
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/// * ProgramCounterIndirectWithIndexBaseDisplacement,
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/// ProgramCounterMemoryIndirectPostindexed and
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/// ProgramCounterMemoryIndirectPreindexed will have been partially decoded
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/// as ProgramCounterIndirectWithIndex8bitDisplacement.
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enum class AddressingMode: uint8_t {
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/// No adddressing mode; this operand doesn't exist.
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None = 0b01'101,
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/// Dn
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DataRegisterDirect = 0b00'000,
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/// An
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AddressRegisterDirect = 0b00'001,
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/// (An)
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AddressRegisterIndirect = 0b00'010,
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/// (An)+
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AddressRegisterIndirectWithPostincrement = 0b00'011,
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/// -(An)
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AddressRegisterIndirectWithPredecrement = 0b00'100,
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/// (d16, An)
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AddressRegisterIndirectWithDisplacement = 0b00'101,
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/// (d8, An, Xn)
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AddressRegisterIndirectWithIndex8bitDisplacement = 0b00'110,
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/// (bd, An, Xn) [68020+]
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AddressRegisterIndirectWithIndexBaseDisplacement = 0b10'000,
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/// ([bd, An, Xn], od) [68020+]
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MemoryIndirectPostindexed = 0b10'001,
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/// ([bd, An], Xn, od) [68020+]
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MemoryIndirectPreindexed = 0b10'010,
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/// (d16, PC)
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ProgramCounterIndirectWithDisplacement = 0b01'010,
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/// (d8, PC, Xn)
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ProgramCounterIndirectWithIndex8bitDisplacement = 0b01'011,
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/// (bd, PC, Xn) [68020+]
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ProgramCounterIndirectWithIndexBaseDisplacement = 0b10'011,
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/// ([bd, PC, Xn], od) [68020+]
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ProgramCounterMemoryIndirectPostindexed = 0b10'100,
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/// ([bc, PC], Xn, od) [68020+]
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ProgramCounterMemoryIndirectPreindexed = 0b10'101,
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/// (xxx).W
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AbsoluteShort = 0b01'000,
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/// (xxx).L
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AbsoluteLong = 0b01'001,
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/// #
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ImmediateData = 0b01'100,
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/// An additional word of data. Differs from ImmediateData by being
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/// a fixed size, rather than the @c operand_size of the operation.
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ExtensionWord = 0b01'111,
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/// .q; value is embedded in the opcode.
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Quick = 0b01'110,
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};
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/// Guaranteed to be 1+[largest value used by AddressingMode].
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static constexpr int AddressingModeCount = 0b10'110;
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/*!
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A preinstruction is as much of an instruction as can be decoded with
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only the first instruction word — i.e. an operation, and:
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* on the 68000 and 68010, the complete addressing modes;
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* on subsequent, a decent proportion of the addressing mode. See
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the notes on @c AddressingMode for potential aliasing.
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*/
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class Preinstruction {
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public:
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Operation operation = Operation::Undefined;
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// Instructions come with 0, 1 or 2 operands;
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// the getters below act to provide a list of operands
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// that is terminated by an AddressingMode::None.
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//
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// For two-operand instructions, argument 0 is a source
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// and argument 1 is a destination.
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//
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// For one-operand instructions, only argument 0 will
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// be provided, and will be a source and/or destination as
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// per the semantics of the operation.
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//
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// The versions templated on index do a range check;
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// if using the runtime versions then results for indices
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// other than 0 and 1 are undefined.
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AddressingMode mode(int index) const {
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return AddressingMode(operands_[index] >> 3);
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}
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template <int index> AddressingMode mode() const {
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if constexpr (index > 1) {
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return AddressingMode::None;
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}
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return mode(index);
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}
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int reg(int index) const {
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return operands_[index] & 7;
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}
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template <int index> int reg() const {
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if constexpr (index > 1) {
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return 0;
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}
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return reg(index);
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}
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/// @returns 0–7 to indicate data registers 0 to 7, or 8–15 to indicate address registers 0 to 7 respectively.
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/// Provides undefined results if the addressing mode is not either @c DataRegisterDirect or
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/// @c AddressRegisterDirect.
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int lreg(int index) const {
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return operands_[index] & 0xf;
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}
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/// @returns @c true if this instruction requires supervisor privileges; @c false otherwise.
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bool requires_supervisor() const {
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return flags_ & Flags::IsSupervisor;
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}
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/// @returns @c true if this instruction will require further fetching than can be encoded in a
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/// @c Preinstruction. In practice this means it is one of a very small quantity of 68020+
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/// instructions; those that can rationalise extension words into one of the two operands will
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/// do so. Use the free function @c extension_words(instruction.operation) to
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/// look up the number of additional words required.
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///
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/// (specifically affected, at least: PACK, UNPK, CAS, CAS2)
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bool requires_further_extension() const {
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return flags_ & Flags::RequiresFurtherExtension;
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}
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/// @returns The number of additional extension words required, beyond those encoded as operands.
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int additional_extension_words() const {
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return flags_ & Flags::RequiresFurtherExtension ? (flags_ & Flags::ConditionMask) >> Flags::ConditionShift : 0;
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}
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/// @returns The @c DataSize used for operands of this instruction, i.e. byte, word or longword.
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DataSize operand_size() const {
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return DataSize((flags_ & Flags::SizeMask) >> Flags::SizeShift);
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}
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/// @returns The condition code evaluated by this instruction if applicable. If this instruction is not
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/// conditional, the result is undefined.
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Condition condition() const {
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return Condition((flags_ & Flags::ConditionMask) >> Flags::ConditionShift);
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}
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private:
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uint8_t operands_[2] = { uint8_t(AddressingMode::None), uint8_t(AddressingMode::None)};
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uint8_t flags_ = 0;
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std::string operand_description(int index, int opcode) const;
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public:
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Preinstruction(
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Operation operation,
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AddressingMode op1_mode, int op1_reg,
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AddressingMode op2_mode, int op2_reg,
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bool is_supervisor,
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int extension_words,
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DataSize size,
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Condition condition) : operation(operation)
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{
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operands_[0] = uint8_t((uint8_t(op1_mode) << 3) | op1_reg);
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operands_[1] = uint8_t((uint8_t(op2_mode) << 3) | op2_reg);
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flags_ = uint8_t(
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(is_supervisor ? Flags::IsSupervisor : 0x00) |
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(extension_words ? Flags::RequiresFurtherExtension : 0x00) |
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(int(condition) << Flags::ConditionShift) |
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(extension_words << Flags::ConditionShift) |
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(int(size) << Flags::SizeShift)
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);
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}
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struct Flags {
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static constexpr uint8_t IsSupervisor = 0b1000'0000;
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static constexpr uint8_t RequiresFurtherExtension = 0b0100'0000;
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static constexpr uint8_t ConditionMask = 0b0011'1100;
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static constexpr uint8_t SizeMask = 0b0000'0011;
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static constexpr int IsSupervisorShift = 7;
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static constexpr int RequiresFurtherExtensionShift = 6;
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static constexpr int ConditionShift = 2;
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static constexpr int SizeShift = 0;
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};
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Preinstruction() = default;
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/// Produces a string description of this instruction; if @c opcode
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/// is supplied then any quick fields in this instruction will be decoded;
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/// otherwise they'll be printed as just 'Q'.
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std::string to_string(int opcode = -1) const;
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/// Produces a slightly-more-idiomatic version of the operation name than
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/// a direct to_string(instruction.operation) would, given that this decoder
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/// sometimes aliases operations, disambiguating based on addressing mode
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/// (e.g. MOVEQ is MOVE.l with the Q addressing mode).
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const char *operation_string() const;
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};
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}
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#include "Implementation/InstructionOperandSize.hpp"
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#include "Implementation/InstructionOperandFlags.hpp"
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