mirror of https://github.com/TomHarte/CLK.git
128 lines
3.2 KiB
C++
128 lines
3.2 KiB
C++
//
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// Blitter.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 22/07/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include <cstddef>
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#include <cstdint>
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#include <string>
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#include <vector>
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#include "../../ClockReceiver/ClockReceiver.hpp"
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#include "BlitterSequencer.hpp"
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#include "DMADevice.hpp"
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namespace Amiga {
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/*!
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If @c record_bus is @c true then all bus interactions will be recorded
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and can subsequently be retrieved. This is included for testing purposes.
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*/
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template <bool record_bus = false> class Blitter: public DMADevice<4, 4> {
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public:
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using DMADevice::DMADevice;
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template <int id, int shift> void set_pointer(uint16_t value) {
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DMADevice<4, 4>::set_pointer<id, shift>(value);
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}
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// Various setters; it's assumed that address decoding is handled externally.
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//
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// In all cases where a channel is identified numerically, it's taken that
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// 0 = A, 1 = B, 2 = C, 3 = D.
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void set_control(int index, uint16_t value);
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void set_first_word_mask(uint16_t value);
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void set_last_word_mask(uint16_t value);
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void set_size(uint16_t value);
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void set_minterms(uint16_t value);
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// void set_vertical_size(uint16_t value);
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// void set_horizontal_size(uint16_t value);
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void set_data(int channel, uint16_t value);
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uint16_t get_status();
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template <bool complete_immediately> bool advance_dma();
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struct Transaction {
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enum class Type {
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SkippedSlot,
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ReadA,
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ReadB,
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ReadC,
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AddToPipeline,
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WriteFromPipeline
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} type = Type::SkippedSlot;
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uint32_t address = 0;
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uint16_t value = 0;
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Transaction() = default;
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Transaction(Type type) : type(type) {}
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Transaction(Type type, uint32_t address, uint16_t value) : type(type), address(address), value(value) {}
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std::string to_string() const {
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std::string result;
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switch(type) {
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case Type::SkippedSlot: result = "SkippedSlot"; break;
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case Type::ReadA: result = "ReadA"; break;
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case Type::ReadB: result = "ReadB"; break;
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case Type::ReadC: result = "ReadC"; break;
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case Type::AddToPipeline: result = "AddToPipeline"; break;
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case Type::WriteFromPipeline: result = "WriteFromPipeline"; break;
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}
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result += " address:" + std::to_string(address) + " value:" + std::to_string(value);
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return result;
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}
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};
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std::vector<Transaction> get_and_reset_transactions();
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private:
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int width_ = 0, height_ = 0;
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int shifts_[2]{};
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uint16_t a_mask_[2] = {0xffff, 0xffff};
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bool line_mode_ = false;
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bool one_dot_ = false;
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int line_direction_ = 0;
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int line_sign_ = 1;
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uint32_t direction_ = 1;
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bool inclusive_fill_ = false;
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bool exclusive_fill_ = false;
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bool fill_carry_ = false;
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uint8_t minterms_ = 0;
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uint32_t a32_ = 0, b32_ = 0;
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uint16_t a_data_ = 0, b_data_ = 0, c_data_ = 0;
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bool not_zero_flag_ = false;
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BlitterSequencer sequencer_;
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uint32_t write_address_ = 0xffff'ffff;
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uint16_t write_value_ = 0;
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enum WritePhase {
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Starting, Full
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} write_phase_;
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int y_, x_;
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uint16_t transient_a_mask_;
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bool busy_ = false;
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int loop_index_ = -1;
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int error_ = 0;
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bool draw_ = false;
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bool has_c_data_ = false;
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void add_modulos();
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std::vector<Transaction> transactions_;
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};
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}
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