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818 lines
20 KiB
C++
818 lines
20 KiB
C++
//
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// 65816Implementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 27/09/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles cycles) {
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// Temporary storage for the next bus cycle.
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uint32_t bus_address = 0;
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uint8_t *bus_value = nullptr;
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uint8_t throwaway = 0;
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BusOperation bus_operation = BusOperation::None;
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#define perform_bus(address, value, operation) \
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bus_address = address; \
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bus_value = value; \
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bus_operation = operation
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#define read(address, value) perform_bus(address, value, MOS6502Esque::Read)
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#define write(address, value) perform_bus(address, value, MOS6502Esque::Write)
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#define m_flag() mx_flags_[0]
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#define x_flag() mx_flags_[1]
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#define x() (x_.full & x_masks_[1])
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#define y() (y_.full & x_masks_[1])
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Cycles number_of_cycles = cycles + cycles_left_to_run_;
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while(number_of_cycles > Cycles(0)) {
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const MicroOp operation = *next_op_;
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++next_op_;
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#ifndef NDEBUG
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// As a sanity check.
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bus_value = nullptr;
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#endif
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switch(operation) {
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//
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// Scheduling.
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//
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case OperationMoveToNextProgram: {
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// The exception program will determine the appropriate way to respond
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// based on the pending exception if one exists; otherwise just do a
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// standard fetch-decode-execute.
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const auto offset = instructions[pending_exceptions_ ? size_t(OperationSlot::Exception) : size_t(OperationSlot::FetchDecodeExecute)].program_offsets[0];
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next_op_ = µ_ops_[offset];
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instruction_buffer_.clear();
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data_buffer_.clear();
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last_operation_pc_ = pc_;
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} continue;
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case OperationDecode: {
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active_instruction_ = &instructions[instruction_buffer_.value];
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const auto size_flag = mx_flags_[active_instruction_->size_field];
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next_op_ = µ_ops_[active_instruction_->program_offsets[size_flag]];
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instruction_buffer_.clear();
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} continue;
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//
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// PC fetches.
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//
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case CycleFetchIncrementPC:
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read(pc_ | program_bank_, instruction_buffer_.next_input());
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++pc_;
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break;
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case CycleFetchOpcode:
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perform_bus(pc_ | program_bank_, instruction_buffer_.next_input(), MOS6502Esque::ReadOpcode);
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++pc_;
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break;
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case CycleFetchPC:
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read(pc_ | program_bank_, instruction_buffer_.next_input());
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break;
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case CycleFetchPCThrowaway:
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read(pc_ | program_bank_, &throwaway);
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break;
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//
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// Data fetches and stores.
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//
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#define increment_data_address() data_address_ = (data_address_ & 0xff0000) + ((data_address_ + 1) & 0xffff)
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#define decrement_data_address() data_address_ = (data_address_ & 0xff0000) + ((data_address_ - 1) & 0xffff)
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case CycleFetchData:
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read(data_address_, data_buffer_.next_input());
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break;
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case CycleFetchIncorrectDataAddress:
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read(incorrect_data_address_, &throwaway);
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break;
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case CycleFetchIncrementData:
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read(data_address_, data_buffer_.next_input());
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increment_data_address();
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break;
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case CycleStoreData:
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write(data_address_, data_buffer_.next_output());
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break;
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case CycleStoreDataThrowaway:
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write(data_address_, data_buffer_.preview_output());
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break;
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case CycleStoreIncrementData:
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write(data_address_, data_buffer_.next_output());
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increment_data_address();
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break;
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case CycleStoreDecrementData:
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write(data_address_, data_buffer_.next_output());
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decrement_data_address();
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break;
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case CycleFetchBlockX:
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read(((instruction_buffer_.value & 0xff00) << 8) | x(), data_buffer_.any_byte());
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break;
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case CycleFetchBlockY:
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read(((instruction_buffer_.value & 0xff00) << 8) | y(), &throwaway);
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break;
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case CycleStoreBlockY:
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write(((instruction_buffer_.value & 0xff00) << 8) | x(), data_buffer_.any_byte());
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break;
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#undef increment_data_address
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#undef decrement_data_address
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//
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// Stack accesses.
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//
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#define stack_access(value, operation) \
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if(emulation_flag_) { \
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bus_address = s_.halves.low | 0x100; \
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} else { \
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bus_address = s_.full; \
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} \
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bus_value = value; \
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bus_operation = operation;
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case CyclePush:
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stack_access(data_buffer_.next_stack(), MOS6502Esque::Write);
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--s_.full;
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break;
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case CyclePull:
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++s_.full;
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stack_access(data_buffer_.next_input(), MOS6502Esque::Read);
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break;
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case CycleAccessStack:
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stack_access(&throwaway, MOS6502Esque::Read);
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break;
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#undef stack_access
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//
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// Data movement.
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//
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case OperationCopyPCToData:
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data_buffer_.size = 2;
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data_buffer_.value = pc_;
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continue;
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case OperationCopyInstructionToData:
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data_buffer_ = instruction_buffer_;
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continue;
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case OperationCopyDataToInstruction:
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instruction_buffer_ = data_buffer_;
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continue;
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case OperationCopyAToData:
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data_buffer_.value = a_.full & m_masks_[1];
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data_buffer_.size = 2 - m_flag();
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continue;
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case OperationCopyDataToA:
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a_.full = (a_.full & m_masks_[0]) + (data_buffer_.value & m_masks_[1]);
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continue;
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case OperationCopyPBRToData:
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data_buffer_.size = 1;
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data_buffer_.value = program_bank_ >> 16;
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continue;
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case OperationCopyDataToPC:
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pc_ = uint16_t(data_buffer_.value);
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continue;
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//
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// Address construction.
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//
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case OperationConstructAbsolute:
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data_address_ = instruction_buffer_.value + data_bank_;
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continue;
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case OperationConstructAbsoluteIndexedIndirect:
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data_address_ = (instruction_buffer_.value + x()) & 0xffff;
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continue;
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case OperationConstructAbsoluteLongX:
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data_address_ = (instruction_buffer_.value + x()) & 0xffff + instruction_buffer_.value & 0xff0000;
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continue;
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case OperationConstructAbsoluteXRead:
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case OperationConstructAbsoluteX:
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data_address_ = ((instruction_buffer_.value + x()) & 0xffff) + data_bank_;
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incorrect_data_address_ = (data_address_ & 0xff) | (instruction_buffer_.value & 0xff00) + data_bank_;
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// If the incorrect address isn't actually incorrect, skip its usage.
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if(operation == OperationConstructAbsoluteXRead && data_address_ == incorrect_data_address_) {
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++next_op_;
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}
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continue;
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case OperationConstructAbsoluteYRead:
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case OperationConstructAbsoluteY:
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data_address_ = ((instruction_buffer_.value + y()) & 0xffff) + data_bank_;
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incorrect_data_address_ = (data_address_ & 0xff) + (instruction_buffer_.value & 0xff00) + data_bank_;
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// If the incorrect address isn't actually incorrect, skip its usage.
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if(operation == OperationConstructAbsoluteYRead && data_address_ == incorrect_data_address_) {
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++next_op_;
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}
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continue;
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case OperationConstructDirect:
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data_address_ = (direct_ + instruction_buffer_.value) & 0xffff;
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if(!(direct_&0xff)) {
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++next_op_;
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}
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continue;
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case OperationConstructDirectIndexedIndirect:
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data_address_ = data_bank_ + (direct_ + x() + instruction_buffer_.value) & 0xffff;
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if(!(direct_&0xff)) {
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++next_op_;
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}
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continue;
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case OperationConstructDirectIndirect:
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data_address_ = data_bank_ + (direct_ + instruction_buffer_.value) & 0xffff;
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if(!(direct_&0xff)) {
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++next_op_;
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}
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continue;
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case OperationConstructDirectIndirectIndexedLong:
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// TODO: assumed here is that the low 16-bit calculation can't carry into
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// the high byte. Test this!
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data_address_ = (y() + instruction_buffer_.value) & 0xffff + instruction_buffer_.value & 0xff0000;
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continue;
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case OperationConstructDirectIndirectLong:
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data_address_ = instruction_buffer_.value;
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continue;
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case OperationConstructDirectX: {
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data_address_ = (
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(direct_ & e_masks_[0]) +
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((instruction_buffer_.value + direct_ + x()) & e_masks_[1])
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) & 0xffff;
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incorrect_data_address_ = (direct_ & 0xff00) + (data_address_ & 0x00ff);
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if(!(direct_&0xff)) {
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++next_op_;
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}
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} continue;
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case OperationConstructDirectY:
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data_address_ = (
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(direct_ & e_masks_[0]) +
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((instruction_buffer_.value + direct_ + y()) & e_masks_[1])
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) & 0xffff;
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// TODO: given the 16-bit internal arithmetic, confirm this is the correct spurious address.
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incorrect_data_address_ = (direct_ & 0xff00) + (data_address_ & 0x00ff);
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if(!(direct_&0xff)) {
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++next_op_;
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}
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continue;
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case OperationConstructPER:
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data_buffer_.value = instruction_buffer_.value + pc_;
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data_buffer_.size = 2;
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continue;
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case OperationConstructStackRelative:
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data_address_ = (s_.full + instruction_buffer_.value) & 0xffff;
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continue;
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case OperationConstructStackRelativeIndexedIndirect:
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data_address_ = data_bank_ + (instruction_buffer_.value + y()) & 0xffff;
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continue;
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case OperationPrepareException: {
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// Put the proper exception vector into the data address, put the flags and PC
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// into the data buffer (possibly also PBR), and skip an instruction if in
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// emulation mode.
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bool is_brk = false;
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if(pending_exceptions_ & (Reset | PowerOn)) {
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// TODO: set emulation mode, etc.
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pending_exceptions_ &= ~(Reset | PowerOn);
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data_address_ = 0xfffc;
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} else if(pending_exceptions_ & NMI) {
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pending_exceptions_ &= ~NMI;
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data_address_ = 0xfffa;
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} else if(pending_exceptions_ & IRQ) {
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pending_exceptions_ &= ~IRQ;
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data_address_ = 0xfffe;
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} else {
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is_brk = active_instruction_ == instructions;
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if(is_brk) {
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data_address_ = emulation_flag_ ? 0xfffe : 0xfff6;
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} else {
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// Implicitly: COP.
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data_address_ = 0xfff4;
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}
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}
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data_buffer_.value = (pc_ << 8) | flags_.get();
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if(emulation_flag_) {
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if(is_brk) data_buffer_.value |= Flag::Break;
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data_buffer_.size = 3;
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++next_op_;
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} else {
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data_buffer_.value |= program_bank_ << 24;
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data_buffer_.size = 4;
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program_bank_ = 0;
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assert(false); // TODO: proper flags, still.
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}
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flags_.inverse_interrupt = 0;
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} continue;
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//
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// Performance.
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//
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#define LD(dest, src, masks) dest.full = (dest.full & masks[0]) | (src & masks[1])
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#define m_top() (instruction_buffer_.value >> m_shift_) & 0xff
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#define x_top() (x_.full >> x_shift_) & 0xff
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#define y_top() (y_.full >> x_shift_) & 0xff
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#define a_top() (a_.full >> m_shift_) & 0xff
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case OperationPerform:
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switch(active_instruction_->operation) {
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//
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// Loads, stores and transfers (and NOP).
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//
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case LDA:
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LD(a_, data_buffer_.value, m_masks_);
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flags_.set_nz(a_.full, m_shift_);
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break;
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case LDX:
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LD(x_, data_buffer_.value, x_masks_);
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flags_.set_nz(x_.full, x_shift_);
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break;
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case LDY:
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LD(y_, data_buffer_.value, x_masks_);
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flags_.set_nz(y_.full, x_shift_);
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break;
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case PLB:
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data_bank_ = (data_buffer_.value & 0xff) << 16;
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flags_.set_nz(instruction_buffer_.value);
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break;
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case PLD:
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direct_ = data_buffer_.value;
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flags_.set_nz(instruction_buffer_.value);
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break;
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case PLP:
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flags_.set(data_buffer_.value);
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if(!emulation_flag_) {
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assert(false); // TODO: M and X.
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}
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break;
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case STA:
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data_buffer_.value = a_.full & m_masks_[1];
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data_buffer_.size = 2 - m_flag();
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break;
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case STZ:
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data_buffer_.value = 0;
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data_buffer_.size = 2 - m_flag();
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break;
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case STX:
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data_buffer_.value = x_.full & x_masks_[1];
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data_buffer_.size = 2 - x_flag();
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break;
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case STY:
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data_buffer_.value = y_.full & x_masks_[1];
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data_buffer_.size = 2 - m_flag();
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break;
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case PHB:
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data_buffer_.value = data_bank_ >> 16;
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data_buffer_.size = 1;
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break;
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case PHK:
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data_buffer_.value = program_bank_ >> 16;
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data_buffer_.size = 1;
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break;
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case PHD:
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data_buffer_.value = direct_;
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data_buffer_.size = 2;
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break;
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case PHP:
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data_buffer_.value = flags_.get();
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data_buffer_.size = 1;
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if(!emulation_flag_) {
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assert(false); // TODO: M and X.
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} else {
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// On the 6502, the break flag is set during a PHP.
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data_buffer_.value |= Flag::Break;
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}
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break;
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case NOP: break;
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// The below attempt to obey the 8/16-bit mixed transfer rules
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// as documented in https://softpixel.com/~cwright/sianse/docs/65816NFO.HTM
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// (and makes reasonable guesses as to the N flag)
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case TXS:
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s_ = x_.full & x_masks_[1];
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break;
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case TSX:
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LD(x_, s_.full, x_masks_);
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flags_.set_nz(x_.full, x_shift_);
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break;
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case TXY:
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LD(y_, x_.full, x_masks_);
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flags_.set_nz(y_.full, x_shift_);
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break;
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case TYX:
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LD(x_, y_.full, x_masks_);
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flags_.set_nz(x_.full, x_shift_);
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break;
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case TAX:
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LD(x_, a_.full, x_masks_);
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flags_.set_nz(x_.full, x_shift_);
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break;
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case TAY:
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LD(y_, a_.full, x_masks_);
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flags_.set_nz(y_.full, x_shift_);
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break;
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case TXA:
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LD(a_, x_.full, m_masks_);
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flags_.set_nz(a_.full, m_shift_);
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break;
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case TYA:
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LD(a_, y_.full, m_masks_);
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flags_.set_nz(a_.full, m_shift_);
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break;
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//
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// Jumps and returns.
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//
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case JML:
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program_bank_ = instruction_buffer_.value & 0xff0000;
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[[fallthrough]];
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case JMP:
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pc_ = uint16_t(instruction_buffer_.value);
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break;
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case JMPind:
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pc_ = data_buffer_.value;
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break;
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case RTS:
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pc_ = data_buffer_.value + 1;
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break;
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case JSL:
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program_bank_ = instruction_buffer_.value & 0xff0000;
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[[fallthrough]];
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case JSR:
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data_buffer_.value = pc_;
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data_buffer_.size = 2;
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pc_ = instruction_buffer_.value;
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break;
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case RTI:
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pc_ = uint16_t(data_buffer_.value >> 8);
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flags_.set(uint8_t(data_buffer_.value));
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if(!emulation_flag_) {
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program_bank_ = (data_buffer_.value & 0xff000000) >> 8;
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assert(false); // Extra flags to unpack!
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}
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break;
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//
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// Block moves.
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//
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case MVP:
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data_bank_ = (instruction_buffer_.value & 0xff) << 16;
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--x_.full;
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--y_.full;
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--a_.full;
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if(a_.full) pc_ -= 3;
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break;
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case MVN:
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data_bank_ = (instruction_buffer_.value & 0xff) << 16;
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++x_.full;
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++y_.full;
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--a_.full;
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if(a_.full) pc_ -= 3;
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break;
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//
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// Flag manipulation.
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//
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case CLC: flags_.carry = 0; break;
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case CLI: flags_.inverse_interrupt = Flag::Interrupt; break;
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case CLV: flags_.overflow = 0; break;
|
|
case CLD: flags_.decimal = 0; break;
|
|
|
|
case SEC: flags_.carry = Flag::Carry; break;
|
|
case SEI: flags_.inverse_interrupt = 0; break;
|
|
case SED: flags_.decimal = Flag::Decimal; break;
|
|
|
|
//
|
|
// Increments and decrements.
|
|
//
|
|
|
|
case INC:
|
|
++data_buffer_.value;
|
|
flags_.set_nz(data_buffer_.value, m_shift_);
|
|
break;;
|
|
|
|
case DEC:
|
|
--data_buffer_.value;
|
|
flags_.set_nz(data_buffer_.value, m_shift_);
|
|
break;
|
|
|
|
case INX: {
|
|
const uint16_t x_inc = x_.full + 1;
|
|
LD(x_, x_inc, x_masks_);
|
|
flags_.set_nz(x_.full, x_shift_);
|
|
} break;
|
|
|
|
case DEX: {
|
|
const uint16_t x_dec = x_.full - 1;
|
|
LD(x_, x_dec, x_masks_);
|
|
flags_.set_nz(x_.full, x_shift_);
|
|
} break;
|
|
|
|
case INY: {
|
|
const uint16_t y_inc = y_.full + 1;
|
|
LD(y_, y_inc, x_masks_);
|
|
flags_.set_nz(y_.full, x_shift_);
|
|
} break;
|
|
|
|
case DEY: {
|
|
const uint16_t y_dec = y_.full - 1;
|
|
LD(y_, y_dec, x_masks_);
|
|
flags_.set_nz(y_.full, x_shift_);
|
|
} break;
|
|
|
|
//
|
|
// Bitwise operations.
|
|
//
|
|
|
|
case AND:
|
|
a_.full &= instruction_buffer_.value | m_masks_[0];
|
|
flags_.set_nz(a_.full, m_shift_);
|
|
break;
|
|
|
|
case EOR:
|
|
a_.full ^= instruction_buffer_.value;
|
|
flags_.set_nz(a_.full, m_shift_);
|
|
break;
|
|
|
|
case ORA:
|
|
a_.full |= instruction_buffer_.value;
|
|
flags_.set_nz(a_.full, m_shift_);
|
|
break;
|
|
|
|
case BIT:
|
|
flags_.set_nz(data_buffer_.value & a_.full, m_shift_);
|
|
flags_.overflow = data_buffer_.value & Flag::Overflow;
|
|
break;
|
|
|
|
case BITimm:
|
|
flags_.set_z(data_buffer_.value & a_.full, m_shift_);
|
|
break;
|
|
|
|
//
|
|
// Branches.
|
|
//
|
|
|
|
#define BRA(condition) \
|
|
if(!(condition)) { \
|
|
next_op_ += 3; \
|
|
} else { \
|
|
data_buffer_.size = 2; \
|
|
data_buffer_.value = pc_ + int8_t(instruction_buffer_.value); \
|
|
\
|
|
if((pc_ & 0xff00) == (instruction_buffer_.value & 0xff00)) { \
|
|
++next_op_; \
|
|
} \
|
|
}
|
|
|
|
case BPL: BRA(!(flags_.negative_result&0x80)); break;
|
|
case BMI: BRA(flags_.negative_result&0x80); break;
|
|
case BVC: BRA(!flags_.overflow); break;
|
|
case BVS: BRA(flags_.overflow); break;
|
|
case BCC: BRA(!flags_.carry); break;
|
|
case BCS: BRA(flags_.carry); break;
|
|
case BNE: BRA(flags_.zero_result); break;
|
|
case BEQ: BRA(!flags_.zero_result); break;
|
|
case BRA: BRA(true); break;
|
|
|
|
#undef BRA
|
|
|
|
case BRL:
|
|
pc_ += int16_t(instruction_buffer_.value);
|
|
break;
|
|
|
|
//
|
|
// Shifts and rolls.
|
|
//
|
|
|
|
case ASL:
|
|
flags_.carry = data_buffer_.value >> (7 + m_shift_);
|
|
data_buffer_.value <<= 1;
|
|
flags_.set_nz(instruction_buffer_.value, m_shift_);
|
|
break;
|
|
|
|
case LSR:
|
|
flags_.carry = data_buffer_.value & 1;
|
|
data_buffer_.value >>= 1;
|
|
flags_.set_nz(instruction_buffer_.value, m_shift_);
|
|
break;
|
|
|
|
case ROL:
|
|
data_buffer_.value = (data_buffer_.value << 1) | flags_.carry;
|
|
flags_.carry = data_buffer_.value >> (7 + m_shift_);
|
|
flags_.set_nz(instruction_buffer_.value, m_shift_);
|
|
break;
|
|
|
|
case ROR: {
|
|
const uint8_t next_carry = data_buffer_.value & 1;
|
|
data_buffer_.value = (data_buffer_.value >> 1) | (flags_.carry << (7 + m_shift_));
|
|
flags_.carry = next_carry;
|
|
flags_.set_nz(instruction_buffer_.value, m_shift_);
|
|
} break;
|
|
|
|
//
|
|
// Arithmetic.
|
|
//
|
|
|
|
#define cp(v, shift, masks) {\
|
|
const uint32_t temp32 = (v.full & masks[1]) - (data_buffer_.value & masks[1]); \
|
|
flags_.set_nz(uint16_t(temp32), shift); \
|
|
flags_.carry = ((~temp32) >> (8 + shift))&1; \
|
|
}
|
|
|
|
case CMP: cp(a_, m_shift_, m_masks_); break;
|
|
case CPX: cp(x_, x_shift_, x_masks_); break;
|
|
case CPY: cp(y_, x_shift_, x_masks_); break;
|
|
|
|
#undef cp
|
|
|
|
case SBC:
|
|
data_buffer_.value = ~data_buffer_.value & m_masks_[1];
|
|
[[fallthrough]];
|
|
|
|
case ADC: {
|
|
int result;
|
|
const uint16_t a = a_.full & m_masks_[1];
|
|
|
|
if(flags_.decimal) {
|
|
result = flags_.carry;
|
|
const int nibble_adjustment = (active_instruction_->operation == SBC) ? 0xa : 0x6;
|
|
|
|
// TODO: this still isn't quite correct for SBC as the limit test is wrong, I think.
|
|
|
|
#define nibble(mask, limit, addition, carry) \
|
|
result += (a & mask) + (data_buffer_.value & mask); \
|
|
if(result >= limit) result = ((result + (addition)) & (carry - 1)) + carry;
|
|
|
|
nibble(0x000f, 0x000a, nibble_adjustment << 0, 0x00010);
|
|
nibble(0x00f0, 0x00a0, nibble_adjustment << 8, 0x00100);
|
|
nibble(0x0f00, 0x0a00, nibble_adjustment << 16, 0x01000);
|
|
nibble(0xf000, 0xa000, nibble_adjustment << 24, 0x10000);
|
|
|
|
#undef nibble
|
|
|
|
} else {
|
|
result = a + data_buffer_.value + flags_.carry;
|
|
}
|
|
|
|
flags_.overflow = (( (result ^ a_.full) & (result ^ data_buffer_.value) ) >> (1 + m_shift_))&0x40;
|
|
flags_.set_nz(result, m_shift_);
|
|
flags_.carry = (result >> (8 + m_shift_))&1;
|
|
LD(a_, result, m_masks_);
|
|
} break;
|
|
|
|
// TODO:
|
|
// TRB, TSB,
|
|
// REP, SEP,
|
|
// XCE, XBA,
|
|
// STP, WAI,
|
|
// RTL,
|
|
// TCD, TCS, TDC, TSC
|
|
|
|
default:
|
|
assert(false);
|
|
}
|
|
continue;
|
|
|
|
default:
|
|
assert(false);
|
|
}
|
|
|
|
#undef LD
|
|
#undef m_top
|
|
#undef x_top
|
|
#undef y_top
|
|
#undef a_top
|
|
|
|
number_of_cycles -= bus_handler_.perform_bus_operation(bus_operation, bus_address, bus_value);
|
|
}
|
|
|
|
#undef read
|
|
#undef write
|
|
#undef bus_operation
|
|
#undef x
|
|
#undef y
|
|
#undef m_flag
|
|
#undef x_flag
|
|
|
|
cycles_left_to_run_ = number_of_cycles;
|
|
}
|
|
|
|
void ProcessorBase::set_power_on(bool active) {
|
|
if(active) {
|
|
pending_exceptions_ |= PowerOn;
|
|
} else {
|
|
pending_exceptions_ &= ~PowerOn;
|
|
}
|
|
}
|
|
|
|
void ProcessorBase::set_irq_line(bool active) {
|
|
if(active) {
|
|
pending_exceptions_ |= IRQ;
|
|
} else {
|
|
pending_exceptions_ &= ~IRQ;
|
|
}
|
|
}
|
|
|
|
void ProcessorBase::set_reset_line(bool active) {
|
|
if(active) {
|
|
pending_exceptions_ |= Reset;
|
|
} else {
|
|
pending_exceptions_ &= ~Reset;
|
|
}
|
|
}
|
|
|
|
void ProcessorBase::set_nmi_line(bool active) {
|
|
// This is edge triggered.
|
|
if(active) {
|
|
pending_exceptions_ |= NMI;
|
|
}
|
|
}
|
|
|
|
// The 65816 can't jam.
|
|
bool ProcessorBase::is_jammed() const { return false; }
|